Lines Matching +full:dc +full:- +full:to +full:- +full:dc
1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
32 #include "dc.h"
43 stats->frames = 0; in tegra_dc_stats_reset()
44 stats->vblank = 0; in tegra_dc_stats_reset()
45 stats->underflow = 0; in tegra_dc_stats_reset()
46 stats->overflow = 0; in tegra_dc_stats_reset()
50 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
54 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
55 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
56 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
65 offset = 0x000 + (offset - 0x500); in tegra_plane_offset()
66 return plane->offset + offset; in tegra_plane_offset()
70 offset = 0x180 + (offset - 0x700); in tegra_plane_offset()
71 return plane->offset + offset; in tegra_plane_offset()
75 offset = 0x1c0 + (offset - 0x800); in tegra_plane_offset()
76 return plane->offset + offset; in tegra_plane_offset()
79 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
81 return plane->offset + offset; in tegra_plane_offset()
87 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
93 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
96 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) in tegra_dc_has_output() argument
98 struct device_node *np = dc->dev->of_node; in tegra_dc_has_output()
103 if (it.node == dev->of_node) in tegra_dc_has_output()
110 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
115 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
121 void tegra_dc_commit(struct tegra_dc *dc) in tegra_dc_commit() argument
123 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
124 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
152 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); in compute_dda_inc()
153 inf.full -= dfixed_const(1); in compute_dda_inc()
181 /* disable blending for non-overlapping case */ in tegra_plane_setup_blending_legacy()
185 state = to_tegra_plane_state(plane->base.state); in tegra_plane_setup_blending_legacy()
187 if (state->opaque) { in tegra_plane_setup_blending_legacy()
189 * Since custom fix-weight blending isn't utilized and weight in tegra_plane_setup_blending_legacy()
190 * of top window is set to max, we can enforce dependent in tegra_plane_setup_blending_legacy()
203 * to the area if all of the windows on top of it have an alpha in tegra_plane_setup_blending_legacy()
206 switch (state->base.normalized_zpos) { in tegra_plane_setup_blending_legacy()
208 if (state->blending[0].alpha && in tegra_plane_setup_blending_legacy()
209 state->blending[1].alpha) in tegra_plane_setup_blending_legacy()
231 if (state->blending[i].alpha && in tegra_plane_setup_blending_legacy()
232 state->blending[i].top) in tegra_plane_setup_blending_legacy()
236 switch (state->base.normalized_zpos) { in tegra_plane_setup_blending_legacy()
238 if (state->blending[0].alpha && in tegra_plane_setup_blending_legacy()
239 state->blending[1].alpha) in tegra_plane_setup_blending_legacy()
249 if (state->blending[0].alpha && in tegra_plane_setup_blending_legacy()
250 state->blending[0].top) in tegra_plane_setup_blending_legacy()
253 if (state->blending[1].alpha && in tegra_plane_setup_blending_legacy()
254 state->blending[1].top) in tegra_plane_setup_blending_legacy()
260 switch (state->base.normalized_zpos) { in tegra_plane_setup_blending_legacy()
273 if (!state->blending[0].top && state->blending[1].top) { in tegra_plane_setup_blending_legacy()
309 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos); in tegra_plane_setup_blending()
317 struct tegra_dc *dc = plane->dc; in tegra_plane_use_horizontal_filtering() local
319 if (window->src.w == window->dst.w) in tegra_plane_use_horizontal_filtering()
322 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_horizontal_filtering()
332 struct tegra_dc *dc = plane->dc; in tegra_plane_use_vertical_filtering() local
334 if (window->src.h == window->dst.h) in tegra_plane_use_vertical_filtering()
337 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_vertical_filtering()
340 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter) in tegra_plane_use_vertical_filtering()
350 struct tegra_dc *dc = plane->dc; in tegra_dc_setup_window() local
359 yuv = tegra_plane_format_is_yuv(window->format, &planes, NULL); in tegra_dc_setup_window()
361 bpp = window->bits_per_pixel / 8; in tegra_dc_setup_window()
365 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH); in tegra_dc_setup_window()
366 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP); in tegra_dc_setup_window()
368 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); in tegra_dc_setup_window()
371 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); in tegra_dc_setup_window()
374 h_offset = window->src.x * bpp; in tegra_dc_setup_window()
375 v_offset = window->src.y; in tegra_dc_setup_window()
376 h_size = window->src.w * bpp; in tegra_dc_setup_window()
377 v_size = window->src.h; in tegra_dc_setup_window()
379 if (window->reflect_x) in tegra_dc_setup_window()
380 h_offset += (window->src.w - 1) * bpp; in tegra_dc_setup_window()
382 if (window->reflect_y) in tegra_dc_setup_window()
383 v_offset += window->src.h - 1; in tegra_dc_setup_window()
390 * modes needs to take into account all Y, U and V components. in tegra_dc_setup_window()
395 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); in tegra_dc_setup_window()
396 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); in tegra_dc_setup_window()
401 h_dda = compute_initial_dda(window->src.x); in tegra_dc_setup_window()
402 v_dda = compute_initial_dda(window->src.y); in tegra_dc_setup_window()
410 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR); in tegra_dc_setup_window()
413 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U); in tegra_dc_setup_window()
416 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V); in tegra_dc_setup_window()
418 value = window->stride[1] << 16 | window->stride[0]; in tegra_dc_setup_window()
421 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE); in tegra_dc_setup_window()
427 if (dc->soc->supports_block_linear) { in tegra_dc_setup_window()
428 unsigned long height = window->tiling.value; in tegra_dc_setup_window()
430 switch (window->tiling.mode) { in tegra_dc_setup_window()
447 switch (window->tiling.mode) { in tegra_dc_setup_window()
460 * No need to handle this here because ->atomic_check in tegra_dc_setup_window()
483 } else if (window->bits_per_pixel < 24) { in tegra_dc_setup_window()
487 if (window->reflect_x) in tegra_dc_setup_window()
490 if (window->reflect_y) in tegra_dc_setup_window()
495 * Enable horizontal 6-tap filter and set filtering in tegra_dc_setup_window()
496 * coefficients to the default values defined in TRM. in tegra_dc_setup_window()
522 * Enable vertical 2-tap filter and set filtering in tegra_dc_setup_window()
523 * coefficients to the default values defined in TRM. in tegra_dc_setup_window()
525 for (i = 0, k = 128; i < 16; i++, k -= 8) in tegra_dc_setup_window()
533 if (dc->soc->has_legacy_blending) in tegra_dc_setup_window()
546 /* non-native formats */
626 unsigned int rotation = new_plane_state->rotation; in tegra_plane_atomic_check()
627 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_plane_atomic_check()
629 struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc); in tegra_plane_atomic_check() local
632 plane_state->peak_memory_bandwidth = 0; in tegra_plane_atomic_check()
633 plane_state->avg_memory_bandwidth = 0; in tegra_plane_atomic_check()
636 if (!new_plane_state->crtc) { in tegra_plane_atomic_check()
637 plane_state->total_peak_memory_bandwidth = 0; in tegra_plane_atomic_check()
641 err = tegra_plane_format(new_plane_state->fb->format->format, in tegra_plane_atomic_check()
642 &plane_state->format, in tegra_plane_atomic_check()
643 &plane_state->swap); in tegra_plane_atomic_check()
653 if (dc->soc->has_legacy_blending) { in tegra_plane_atomic_check()
659 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); in tegra_plane_atomic_check()
663 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_plane_atomic_check()
664 !dc->soc->supports_block_linear) { in tegra_plane_atomic_check()
666 return -EINVAL; in tegra_plane_atomic_check()
670 * Older userspace used custom BO flag in order to specify the Y in tegra_plane_atomic_check()
672 * property in order to achieve the same result. The legacy BO flag in tegra_plane_atomic_check()
675 if (tegra_fb_is_bottom_up(new_plane_state->fb)) in tegra_plane_atomic_check()
681 plane_state->reflect_x = true; in tegra_plane_atomic_check()
683 plane_state->reflect_x = false; in tegra_plane_atomic_check()
686 plane_state->reflect_y = true; in tegra_plane_atomic_check()
688 plane_state->reflect_y = false; in tegra_plane_atomic_check()
692 * error out if the user tries to display a framebuffer with such a in tegra_plane_atomic_check()
695 if (new_plane_state->fb->format->num_planes > 2) { in tegra_plane_atomic_check()
696 if (new_plane_state->fb->pitches[2] != new_plane_state->fb->pitches[1]) { in tegra_plane_atomic_check()
697 DRM_ERROR("unsupported UV-plane configuration\n"); in tegra_plane_atomic_check()
698 return -EINVAL; in tegra_plane_atomic_check()
718 if (!old_state || !old_state->crtc) in tegra_plane_atomic_disable()
732 struct drm_framebuffer *fb = new_state->fb; in tegra_plane_atomic_update()
738 if (!new_state->crtc || !new_state->fb) in tegra_plane_atomic_update()
741 if (!new_state->visible) in tegra_plane_atomic_update()
745 window.src.x = new_state->src.x1 >> 16; in tegra_plane_atomic_update()
746 window.src.y = new_state->src.y1 >> 16; in tegra_plane_atomic_update()
747 window.src.w = drm_rect_width(&new_state->src) >> 16; in tegra_plane_atomic_update()
748 window.src.h = drm_rect_height(&new_state->src) >> 16; in tegra_plane_atomic_update()
749 window.dst.x = new_state->dst.x1; in tegra_plane_atomic_update()
750 window.dst.y = new_state->dst.y1; in tegra_plane_atomic_update()
751 window.dst.w = drm_rect_width(&new_state->dst); in tegra_plane_atomic_update()
752 window.dst.h = drm_rect_height(&new_state->dst); in tegra_plane_atomic_update()
753 window.bits_per_pixel = fb->format->cpp[0] * 8; in tegra_plane_atomic_update()
754 window.reflect_x = tegra_plane_state->reflect_x; in tegra_plane_atomic_update()
755 window.reflect_y = tegra_plane_state->reflect_y; in tegra_plane_atomic_update()
758 window.zpos = new_state->normalized_zpos; in tegra_plane_atomic_update()
759 window.tiling = tegra_plane_state->tiling; in tegra_plane_atomic_update()
760 window.format = tegra_plane_state->format; in tegra_plane_atomic_update()
761 window.swap = tegra_plane_state->swap; in tegra_plane_atomic_update()
763 for (i = 0; i < fb->format->num_planes; i++) { in tegra_plane_atomic_update()
764 window.base[i] = tegra_plane_state->iova[i] + fb->offsets[i]; in tegra_plane_atomic_update()
769 * function, so it's safe to ignore the V-plane pitch here. in tegra_plane_atomic_update()
772 window.stride[i] = fb->pitches[i]; in tegra_plane_atomic_update()
790 * CRTC to already be in the mode_config's list of CRTCs. However, it in tegra_plane_get_possible_crtcs()
791 * will only be added to that list in the drm_crtc_init_with_planes() in tegra_plane_get_possible_crtcs()
800 return 1 << drm->mode_config.num_crtc; in tegra_plane_get_possible_crtcs()
804 struct tegra_dc *dc) in tegra_primary_plane_create() argument
816 return ERR_PTR(-ENOMEM); in tegra_primary_plane_create()
819 plane->offset = 0xa00; in tegra_primary_plane_create()
820 plane->index = 0; in tegra_primary_plane_create()
821 plane->dc = dc; in tegra_primary_plane_create()
823 num_formats = dc->soc->num_primary_formats; in tegra_primary_plane_create()
824 formats = dc->soc->primary_formats; in tegra_primary_plane_create()
825 modifiers = dc->soc->modifiers; in tegra_primary_plane_create()
833 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, in tegra_primary_plane_create()
841 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); in tegra_primary_plane_create()
842 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); in tegra_primary_plane_create()
844 err = drm_plane_create_rotation_property(&plane->base, in tegra_primary_plane_create()
851 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_primary_plane_create()
854 return &plane->base; in tegra_primary_plane_create()
874 plane_state->peak_memory_bandwidth = 0; in tegra_cursor_atomic_check()
875 plane_state->avg_memory_bandwidth = 0; in tegra_cursor_atomic_check()
878 if (!new_plane_state->crtc) { in tegra_cursor_atomic_check()
879 plane_state->total_peak_memory_bandwidth = 0; in tegra_cursor_atomic_check()
884 if ((new_plane_state->src_w >> 16 != new_plane_state->crtc_w) || in tegra_cursor_atomic_check()
885 (new_plane_state->src_h >> 16 != new_plane_state->crtc_h)) in tegra_cursor_atomic_check()
886 return -EINVAL; in tegra_cursor_atomic_check()
889 if (new_plane_state->src_w != new_plane_state->src_h) in tegra_cursor_atomic_check()
890 return -EINVAL; in tegra_cursor_atomic_check()
892 if (new_plane_state->crtc_w != 32 && new_plane_state->crtc_w != 64 && in tegra_cursor_atomic_check()
893 new_plane_state->crtc_w != 128 && new_plane_state->crtc_w != 256) in tegra_cursor_atomic_check()
894 return -EINVAL; in tegra_cursor_atomic_check()
907 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); in __tegra_cursor_atomic_update() local
908 struct tegra_drm *tegra = plane->dev->dev_private; in __tegra_cursor_atomic_update()
910 u64 dma_mask = *dc->dev->dma_mask; in __tegra_cursor_atomic_update()
916 if (!new_state->crtc || !new_state->fb) in __tegra_cursor_atomic_update()
921 * nvdisplay relies on software to clip the cursor to the screen. in __tegra_cursor_atomic_update()
923 if (!dc->soc->has_nvdisplay) in __tegra_cursor_atomic_update()
926 switch (new_state->crtc_w) { in __tegra_cursor_atomic_update()
945 new_state->crtc_w, new_state->crtc_h); in __tegra_cursor_atomic_update()
949 value |= (tegra_plane_state->iova[0] >> 10) & 0x3fffff; in __tegra_cursor_atomic_update()
950 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); in __tegra_cursor_atomic_update()
953 value = (tegra_plane_state->iova[0] >> 32) & (dma_mask >> 32); in __tegra_cursor_atomic_update()
954 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); in __tegra_cursor_atomic_update()
958 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in __tegra_cursor_atomic_update()
960 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in __tegra_cursor_atomic_update()
962 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); in __tegra_cursor_atomic_update()
966 if (dc->soc->has_nvdisplay) in __tegra_cursor_atomic_update()
974 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); in __tegra_cursor_atomic_update()
977 if (dc->soc->has_nvdisplay) { in __tegra_cursor_atomic_update()
980 x = new_state->dst.x1; in __tegra_cursor_atomic_update()
981 y = new_state->dst.y1; in __tegra_cursor_atomic_update()
983 drm_rect_fp_to_int(&src, &new_state->src); in __tegra_cursor_atomic_update()
985 value = (src.y1 & tegra->vmask) << 16 | (src.x1 & tegra->hmask); in __tegra_cursor_atomic_update()
986 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR); in __tegra_cursor_atomic_update()
988 value = (drm_rect_height(&src) & tegra->vmask) << 16 | in __tegra_cursor_atomic_update()
989 (drm_rect_width(&src) & tegra->hmask); in __tegra_cursor_atomic_update()
990 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR); in __tegra_cursor_atomic_update()
992 x = new_state->crtc_x; in __tegra_cursor_atomic_update()
993 y = new_state->crtc_y; in __tegra_cursor_atomic_update()
997 value = ((y & tegra->vmask) << 16) | (x & tegra->hmask); in __tegra_cursor_atomic_update()
998 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); in __tegra_cursor_atomic_update()
1014 struct tegra_dc *dc; in tegra_cursor_atomic_disable() local
1018 if (!old_state || !old_state->crtc) in tegra_cursor_atomic_disable()
1021 dc = to_tegra_dc(old_state->crtc); in tegra_cursor_atomic_disable()
1023 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
1025 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
1035 crtc_state = drm_atomic_get_existing_crtc_state(state, new_state->crtc); in tegra_cursor_atomic_async_check()
1037 return -EINVAL; in tegra_cursor_atomic_async_check()
1039 if (!crtc_state->active) in tegra_cursor_atomic_async_check()
1040 return -EINVAL; in tegra_cursor_atomic_async_check()
1042 if (plane->state->crtc != new_state->crtc || in tegra_cursor_atomic_async_check()
1043 plane->state->src_w != new_state->src_w || in tegra_cursor_atomic_async_check()
1044 plane->state->src_h != new_state->src_h || in tegra_cursor_atomic_async_check()
1045 plane->state->crtc_w != new_state->crtc_w || in tegra_cursor_atomic_async_check()
1046 plane->state->crtc_h != new_state->crtc_h || in tegra_cursor_atomic_async_check()
1047 plane->state->fb != new_state->fb || in tegra_cursor_atomic_async_check()
1048 plane->state->fb == NULL) in tegra_cursor_atomic_async_check()
1049 return -EINVAL; in tegra_cursor_atomic_async_check()
1059 if (new_state->visible != plane->state->visible) in tegra_cursor_atomic_async_check()
1060 return -EINVAL; in tegra_cursor_atomic_async_check()
1069 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); in tegra_cursor_atomic_async_update() local
1071 plane->state->src_x = new_state->src_x; in tegra_cursor_atomic_async_update()
1072 plane->state->src_y = new_state->src_y; in tegra_cursor_atomic_async_update()
1073 plane->state->crtc_x = new_state->crtc_x; in tegra_cursor_atomic_async_update()
1074 plane->state->crtc_y = new_state->crtc_y; in tegra_cursor_atomic_async_update()
1076 if (new_state->visible) { in tegra_cursor_atomic_async_update()
1082 value = (WIN_A_ACT_REQ << p->index) << 8 | GENERAL_UPDATE; in tegra_cursor_atomic_async_update()
1083 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_cursor_atomic_async_update()
1084 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_cursor_atomic_async_update()
1086 value = (WIN_A_ACT_REQ << p->index) | GENERAL_ACT_REQ; in tegra_cursor_atomic_async_update()
1087 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_cursor_atomic_async_update()
1088 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_cursor_atomic_async_update()
1108 struct tegra_dc *dc) in tegra_dc_cursor_plane_create() argument
1118 return ERR_PTR(-ENOMEM); in tegra_dc_cursor_plane_create()
1124 * code in tegra_add_plane_state() to do the right thing without the in tegra_dc_cursor_plane_create()
1125 * need to special-casing the cursor plane. in tegra_dc_cursor_plane_create()
1127 plane->index = 6; in tegra_dc_cursor_plane_create()
1128 plane->dc = dc; in tegra_dc_cursor_plane_create()
1130 if (!dc->soc->has_nvdisplay) { in tegra_dc_cursor_plane_create()
1144 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, in tegra_dc_cursor_plane_create()
1153 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); in tegra_dc_cursor_plane_create()
1154 drm_plane_create_zpos_immutable_property(&plane->base, 255); in tegra_dc_cursor_plane_create()
1156 return &plane->base; in tegra_dc_cursor_plane_create()
1166 /* non-native formats */
1203 /* semi-planar formats */
1243 /* semi-planar formats */
1253 struct tegra_dc *dc, in tegra_dc_overlay_plane_create() argument
1266 return ERR_PTR(-ENOMEM); in tegra_dc_overlay_plane_create()
1268 plane->offset = 0xa00 + 0x200 * index; in tegra_dc_overlay_plane_create()
1269 plane->index = index; in tegra_dc_overlay_plane_create()
1270 plane->dc = dc; in tegra_dc_overlay_plane_create()
1272 num_formats = dc->soc->num_overlay_formats; in tegra_dc_overlay_plane_create()
1273 formats = dc->soc->overlay_formats; in tegra_dc_overlay_plane_create()
1286 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, in tegra_dc_overlay_plane_create()
1295 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); in tegra_dc_overlay_plane_create()
1296 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); in tegra_dc_overlay_plane_create()
1298 err = drm_plane_create_rotation_property(&plane->base, in tegra_dc_overlay_plane_create()
1305 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_dc_overlay_plane_create()
1308 return &plane->base; in tegra_dc_overlay_plane_create()
1312 struct tegra_dc *dc) in tegra_dc_add_shared_planes() argument
1317 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_add_shared_planes()
1318 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_add_shared_planes()
1320 if (wgrp->dc == dc->pipe) { in tegra_dc_add_shared_planes()
1321 for (j = 0; j < wgrp->num_windows; j++) { in tegra_dc_add_shared_planes()
1322 unsigned int index = wgrp->windows[j]; in tegra_dc_add_shared_planes()
1324 plane = tegra_shared_plane_create(drm, dc, in tegra_dc_add_shared_planes()
1325 wgrp->index, in tegra_dc_add_shared_planes()
1335 plane->type = DRM_PLANE_TYPE_PRIMARY; in tegra_dc_add_shared_planes()
1346 struct tegra_dc *dc) in tegra_dc_add_planes() argument
1353 primary = tegra_primary_plane_create(drm, dc); in tegra_dc_add_planes()
1357 if (dc->soc->supports_cursor) in tegra_dc_add_planes()
1363 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i, in tegra_dc_add_planes()
1368 while (i--) in tegra_dc_add_planes()
1369 planes[i]->funcs->destroy(planes[i]); in tegra_dc_add_planes()
1371 primary->funcs->destroy(primary); in tegra_dc_add_planes()
1388 if (crtc->state) in tegra_crtc_reset()
1389 tegra_crtc_atomic_destroy_state(crtc, crtc->state); in tegra_crtc_reset()
1391 __drm_atomic_helper_crtc_reset(crtc, &state->base); in tegra_crtc_reset()
1397 struct tegra_dc_state *state = to_dc_state(crtc->state); in tegra_crtc_atomic_duplicate_state()
1404 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base); in tegra_crtc_atomic_duplicate_state()
1405 copy->clk = state->clk; in tegra_crtc_atomic_duplicate_state()
1406 copy->pclk = state->pclk; in tegra_crtc_atomic_duplicate_state()
1407 copy->div = state->div; in tegra_crtc_atomic_duplicate_state()
1408 copy->planes = state->planes; in tegra_crtc_atomic_duplicate_state()
1410 return ©->base; in tegra_crtc_atomic_duplicate_state()
1639 struct drm_info_node *node = s->private; in tegra_dc_show_regs()
1640 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_regs() local
1644 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_regs()
1646 if (!dc->base.state->active) { in tegra_dc_show_regs()
1647 err = -EBUSY; in tegra_dc_show_regs()
1654 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name, in tegra_dc_show_regs()
1655 offset, tegra_dc_readl(dc, offset)); in tegra_dc_show_regs()
1659 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_regs()
1665 struct drm_info_node *node = s->private; in tegra_dc_show_crc()
1666 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_crc() local
1670 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_crc()
1672 if (!dc->base.state->active) { in tegra_dc_show_crc()
1673 err = -EBUSY; in tegra_dc_show_crc()
1678 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1679 tegra_dc_commit(dc); in tegra_dc_show_crc()
1681 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1682 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1684 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); in tegra_dc_show_crc()
1687 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1690 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_crc()
1696 struct drm_info_node *node = s->private; in tegra_dc_show_stats()
1697 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_stats() local
1699 seq_printf(s, "frames: %lu\n", dc->stats.frames); in tegra_dc_show_stats()
1700 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); in tegra_dc_show_stats()
1701 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); in tegra_dc_show_stats()
1702 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); in tegra_dc_show_stats()
1704 seq_printf(s, "frames total: %lu\n", dc->stats.frames_total); in tegra_dc_show_stats()
1705 seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total); in tegra_dc_show_stats()
1706 seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total); in tegra_dc_show_stats()
1707 seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total); in tegra_dc_show_stats()
1721 struct drm_minor *minor = crtc->dev->primary; in tegra_dc_late_register()
1723 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_late_register() local
1726 root = crtc->debugfs_entry; in tegra_dc_late_register()
1731 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_dc_late_register()
1733 if (!dc->debugfs_files) in tegra_dc_late_register()
1734 return -ENOMEM; in tegra_dc_late_register()
1737 dc->debugfs_files[i].data = dc; in tegra_dc_late_register()
1739 drm_debugfs_create_files(dc->debugfs_files, count, root, minor); in tegra_dc_late_register()
1747 struct drm_minor *minor = crtc->dev->primary; in tegra_dc_early_unregister()
1748 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_early_unregister() local
1750 drm_debugfs_remove_files(dc->debugfs_files, count, minor); in tegra_dc_early_unregister()
1751 kfree(dc->debugfs_files); in tegra_dc_early_unregister()
1752 dc->debugfs_files = NULL; in tegra_dc_early_unregister()
1757 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_get_vblank_counter() local
1760 if (dc->syncpt && !dc->soc->has_nvdisplay) in tegra_dc_get_vblank_counter()
1761 return host1x_syncpt_read(dc->syncpt); in tegra_dc_get_vblank_counter()
1763 /* fallback to software emulated VBLANK counter */ in tegra_dc_get_vblank_counter()
1764 return (u32)drm_crtc_vblank_count(&dc->base); in tegra_dc_get_vblank_counter()
1769 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_enable_vblank() local
1772 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1774 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1781 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_disable_vblank() local
1784 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1786 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1803 static int tegra_dc_set_timings(struct tegra_dc *dc, in tegra_dc_set_timings() argument
1810 if (!dc->soc->has_nvdisplay) { in tegra_dc_set_timings()
1811 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); in tegra_dc_set_timings()
1814 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); in tegra_dc_set_timings()
1817 value = ((mode->vsync_end - mode->vsync_start) << 16) | in tegra_dc_set_timings()
1818 ((mode->hsync_end - mode->hsync_start) << 0); in tegra_dc_set_timings()
1819 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); in tegra_dc_set_timings()
1821 value = ((mode->vtotal - mode->vsync_end) << 16) | in tegra_dc_set_timings()
1822 ((mode->htotal - mode->hsync_end) << 0); in tegra_dc_set_timings()
1823 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); in tegra_dc_set_timings()
1825 value = ((mode->vsync_start - mode->vdisplay) << 16) | in tegra_dc_set_timings()
1826 ((mode->hsync_start - mode->hdisplay) << 0); in tegra_dc_set_timings()
1827 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); in tegra_dc_set_timings()
1829 value = (mode->vdisplay << 16) | mode->hdisplay; in tegra_dc_set_timings()
1830 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); in tegra_dc_set_timings()
1836 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1838 * @dc: display controller
1845 * 0 on success or a negative error-code on failure.
1847 int tegra_dc_state_setup_clock(struct tegra_dc *dc, in tegra_dc_state_setup_clock() argument
1854 if (!clk_has_parent(dc->clk, clk)) in tegra_dc_state_setup_clock()
1855 return -EINVAL; in tegra_dc_state_setup_clock()
1857 state->clk = clk; in tegra_dc_state_setup_clock()
1858 state->pclk = pclk; in tegra_dc_state_setup_clock()
1859 state->div = div; in tegra_dc_state_setup_clock()
1864 static void tegra_dc_update_voltage_state(struct tegra_dc *dc, in tegra_dc_update_voltage_state() argument
1871 if (!dc->has_opp_table) in tegra_dc_update_voltage_state()
1875 rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2); in tegra_dc_update_voltage_state()
1878 opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate); in tegra_dc_update_voltage_state()
1882 * above the characterized maximum. In this case it's okay to fall in tegra_dc_update_voltage_state()
1883 * back to the characterized maximum. in tegra_dc_update_voltage_state()
1885 if (opp == ERR_PTR(-ERANGE)) in tegra_dc_update_voltage_state()
1886 opp = dev_pm_opp_find_freq_floor(dc->dev, &rate); in tegra_dc_update_voltage_state()
1889 dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n", in tegra_dc_update_voltage_state()
1904 err = dev_pm_genpd_set_performance_state(dc->dev, pstate); in tegra_dc_update_voltage_state()
1906 dev_err(dc->dev, "failed to set power domain state to %lu: %d\n", in tegra_dc_update_voltage_state()
1910 static void tegra_dc_set_clock_rate(struct tegra_dc *dc, in tegra_dc_set_clock_rate() argument
1915 err = clk_set_parent(dc->clk, state->clk); in tegra_dc_set_clock_rate()
1917 dev_err(dc->dev, "failed to set parent clock: %d\n", err); in tegra_dc_set_clock_rate()
1920 * Outputs may not want to change the parent clock rate. This is only in tegra_dc_set_clock_rate()
1921 * relevant to Tegra20 where only a single display PLL is available. in tegra_dc_set_clock_rate()
1923 * panel would need to be driven by some other clock such as PLL_P in tegra_dc_set_clock_rate()
1927 if (state->pclk > 0) { in tegra_dc_set_clock_rate()
1928 err = clk_set_rate(state->clk, state->pclk); in tegra_dc_set_clock_rate()
1930 dev_err(dc->dev, in tegra_dc_set_clock_rate()
1931 "failed to set clock rate to %lu Hz\n", in tegra_dc_set_clock_rate()
1932 state->pclk); in tegra_dc_set_clock_rate()
1934 err = clk_set_rate(dc->clk, state->pclk); in tegra_dc_set_clock_rate()
1936 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", in tegra_dc_set_clock_rate()
1937 dc->clk, state->pclk, err); in tegra_dc_set_clock_rate()
1940 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), in tegra_dc_set_clock_rate()
1941 state->div); in tegra_dc_set_clock_rate()
1942 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); in tegra_dc_set_clock_rate()
1944 tegra_dc_update_voltage_state(dc, state); in tegra_dc_set_clock_rate()
1947 static void tegra_dc_stop(struct tegra_dc *dc) in tegra_dc_stop() argument
1952 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1954 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1956 tegra_dc_commit(dc); in tegra_dc_stop()
1959 static bool tegra_dc_idle(struct tegra_dc *dc) in tegra_dc_idle() argument
1963 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_idle()
1968 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) in tegra_dc_wait_idle() argument
1973 if (tegra_dc_idle(dc)) in tegra_dc_wait_idle()
1979 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); in tegra_dc_wait_idle()
1980 return -ETIMEDOUT; in tegra_dc_wait_idle()
1993 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_update_memory_bandwidth() local
1997 if (dc->soc->has_nvdisplay) in tegra_crtc_update_memory_bandwidth()
2002 if (!crtc->state->active) { in tegra_crtc_update_memory_bandwidth()
2003 if (!old_crtc_state->active) in tegra_crtc_update_memory_bandwidth()
2008 * is kept unchanged. Hence we need to enforce removal of the in tegra_crtc_update_memory_bandwidth()
2014 icc_set_bw(tegra->icc_mem, 0, 0); in tegra_crtc_update_memory_bandwidth()
2015 icc_set_bw(tegra->icc_mem_vfilter, 0, 0); in tegra_crtc_update_memory_bandwidth()
2021 for_each_old_plane_in_state(old_crtc_state->state, plane, in tegra_crtc_update_memory_bandwidth()
2024 new_tegra_state = to_const_tegra_plane_state(plane->state); in tegra_crtc_update_memory_bandwidth()
2029 * planes from another CRTC, hence we need to filter out the in tegra_crtc_update_memory_bandwidth()
2030 * planes unrelated to this CRTC. in tegra_crtc_update_memory_bandwidth()
2032 if (tegra->dc != dc) in tegra_crtc_update_memory_bandwidth()
2035 new_avg_bw = new_tegra_state->avg_memory_bandwidth; in tegra_crtc_update_memory_bandwidth()
2036 old_avg_bw = old_tegra_state->avg_memory_bandwidth; in tegra_crtc_update_memory_bandwidth()
2038 new_peak_bw = new_tegra_state->total_peak_memory_bandwidth; in tegra_crtc_update_memory_bandwidth()
2039 old_peak_bw = old_tegra_state->total_peak_memory_bandwidth; in tegra_crtc_update_memory_bandwidth()
2042 * See the comment related to !crtc->state->active above, in tegra_crtc_update_memory_bandwidth()
2043 * which explains why bandwidths need to be updated when in tegra_crtc_update_memory_bandwidth()
2047 old_crtc_state->active) in tegra_crtc_update_memory_bandwidth()
2050 window.src.h = drm_rect_height(&plane->state->src) >> 16; in tegra_crtc_update_memory_bandwidth()
2051 window.dst.h = drm_rect_height(&plane->state->dst); in tegra_crtc_update_memory_bandwidth()
2053 old_window.src.h = drm_rect_height(&old_plane_state->src) >> 16; in tegra_crtc_update_memory_bandwidth()
2054 old_window.dst.h = drm_rect_height(&old_plane_state->dst); in tegra_crtc_update_memory_bandwidth()
2058 * freq should go high before the DC changes are committed in tegra_crtc_update_memory_bandwidth()
2060 * should to stay high if BW requirement goes down. The in tegra_crtc_update_memory_bandwidth()
2061 * opposite applies to the completion phase (post_commit). in tegra_crtc_update_memory_bandwidth()
2071 icc_set_bw(tegra->icc_mem, new_avg_bw, new_peak_bw); in tegra_crtc_update_memory_bandwidth()
2074 icc_set_bw(tegra->icc_mem_vfilter, new_avg_bw, new_peak_bw); in tegra_crtc_update_memory_bandwidth()
2076 icc_set_bw(tegra->icc_mem_vfilter, 0, 0); in tegra_crtc_update_memory_bandwidth()
2083 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_disable() local
2087 if (!tegra_dc_idle(dc)) { in tegra_crtc_atomic_disable()
2088 tegra_dc_stop(dc); in tegra_crtc_atomic_disable()
2091 * Ignore the return value, there isn't anything useful to do in tegra_crtc_atomic_disable()
2094 tegra_dc_wait_idle(dc, 100); in tegra_crtc_atomic_disable()
2099 * these bits has the side-effect of stopping the display controller. in tegra_crtc_atomic_disable()
2102 * above code is always going to timeout waiting for the controller in tegra_crtc_atomic_disable()
2103 * to go idle. in tegra_crtc_atomic_disable()
2107 * encoder drivers require these bits to be cleared. in tegra_crtc_atomic_disable()
2113 if (dc->rgb) { in tegra_crtc_atomic_disable()
2114 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_disable()
2117 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_disable()
2120 tegra_dc_stats_reset(&dc->stats); in tegra_crtc_atomic_disable()
2123 spin_lock_irq(&crtc->dev->event_lock); in tegra_crtc_atomic_disable()
2125 if (crtc->state->event) { in tegra_crtc_atomic_disable()
2126 drm_crtc_send_vblank_event(crtc, crtc->state->event); in tegra_crtc_atomic_disable()
2127 crtc->state->event = NULL; in tegra_crtc_atomic_disable()
2130 spin_unlock_irq(&crtc->dev->event_lock); in tegra_crtc_atomic_disable()
2132 err = host1x_client_suspend(&dc->client); in tegra_crtc_atomic_disable()
2134 dev_err(dc->dev, "failed to suspend: %d\n", err); in tegra_crtc_atomic_disable()
2136 if (dc->has_opp_table) { in tegra_crtc_atomic_disable()
2137 err = dev_pm_genpd_set_performance_state(dc->dev, 0); in tegra_crtc_atomic_disable()
2139 dev_err(dc->dev, in tegra_crtc_atomic_disable()
2140 "failed to clear power domain state: %d\n", err); in tegra_crtc_atomic_disable()
2147 struct drm_display_mode *mode = &crtc->state->adjusted_mode; in tegra_crtc_atomic_enable()
2148 struct tegra_dc_state *crtc_state = to_dc_state(crtc->state); in tegra_crtc_atomic_enable()
2149 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_enable() local
2154 tegra_dc_set_clock_rate(dc, crtc_state); in tegra_crtc_atomic_enable()
2156 err = host1x_client_resume(&dc->client); in tegra_crtc_atomic_enable()
2158 dev_err(dc->dev, "failed to resume: %d\n", err); in tegra_crtc_atomic_enable()
2163 if (dc->syncpt) { in tegra_crtc_atomic_enable()
2164 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; in tegra_crtc_atomic_enable()
2166 if (dc->soc->has_nvdisplay) in tegra_crtc_atomic_enable()
2172 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); in tegra_crtc_atomic_enable()
2175 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); in tegra_crtc_atomic_enable()
2178 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2181 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
2188 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_crtc_atomic_enable()
2192 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_crtc_atomic_enable()
2195 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
2197 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_crtc_atomic_enable()
2201 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
2205 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_crtc_atomic_enable()
2210 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); in tegra_crtc_atomic_enable()
2214 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); in tegra_crtc_atomic_enable()
2218 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_crtc_atomic_enable()
2222 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
2225 if (dc->soc->supports_background_color) in tegra_crtc_atomic_enable()
2226 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR); in tegra_crtc_atomic_enable()
2228 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); in tegra_crtc_atomic_enable()
2231 if (!dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2232 value = SHIFT_CLK_DIVIDER(crtc_state->div) | PIXEL_CLK_DIVIDER_PCD1; in tegra_crtc_atomic_enable()
2233 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); in tegra_crtc_atomic_enable()
2237 tegra_dc_set_timings(dc, mode); in tegra_crtc_atomic_enable()
2240 if (dc->soc->supports_interlacing) { in tegra_crtc_atomic_enable()
2241 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_atomic_enable()
2243 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_atomic_enable()
2246 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_atomic_enable()
2249 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_atomic_enable()
2251 if (!dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2252 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_enable()
2255 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_enable()
2259 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2261 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW); in tegra_crtc_atomic_enable()
2264 if (dc->rgb) { in tegra_crtc_atomic_enable()
2267 tegra_dc_writel(dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS); in tegra_crtc_atomic_enable()
2270 tegra_dc_commit(dc); in tegra_crtc_atomic_enable()
2282 if (crtc->state->event) { in tegra_crtc_atomic_begin()
2283 spin_lock_irqsave(&crtc->dev->event_lock, flags); in tegra_crtc_atomic_begin()
2286 drm_crtc_send_vblank_event(crtc, crtc->state->event); in tegra_crtc_atomic_begin()
2288 drm_crtc_arm_vblank_event(crtc, crtc->state->event); in tegra_crtc_atomic_begin()
2290 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in tegra_crtc_atomic_begin()
2292 crtc->state->event = NULL; in tegra_crtc_atomic_begin()
2302 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_flush() local
2305 value = dc_state->planes << 8 | GENERAL_UPDATE; in tegra_crtc_atomic_flush()
2306 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2307 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2309 value = dc_state->planes | GENERAL_ACT_REQ; in tegra_crtc_atomic_flush()
2310 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2311 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2316 const struct tegra_dc_soc_info *soc = to_tegra_dc(state->crtc)->soc; in tegra_plane_is_cursor()
2317 const struct drm_format_info *fmt = state->fb->format; in tegra_plane_is_cursor()
2318 unsigned int src_w = drm_rect_width(&state->src) >> 16; in tegra_plane_is_cursor()
2319 unsigned int dst_w = drm_rect_width(&state->dst); in tegra_plane_is_cursor()
2321 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) in tegra_plane_is_cursor()
2324 if (soc->supports_cursor) in tegra_plane_is_cursor()
2327 if (src_w != dst_w || fmt->num_planes != 1 || src_w * fmt->cpp[0] > 256) in tegra_plane_is_cursor()
2343 if (!plane_state->visible || !plane_state->fb) in tegra_plane_overlap_mask()
2347 * Data-prefetch FIFO will easily help to overcome temporal memory in tegra_plane_overlap_mask()
2354 rect = plane_state->dst; in tegra_plane_overlap_mask()
2356 tegra = to_tegra_plane(other_state->plane); in tegra_plane_overlap_mask()
2358 if (!other_state->visible || !other_state->fb) in tegra_plane_overlap_mask()
2362 * Ignore cursor plane overlaps because it's not practical to in tegra_plane_overlap_mask()
2363 * assume that it contributes to the bandwidth in overlapping in tegra_plane_overlap_mask()
2369 if (drm_rect_intersect(&rect, &other_state->dst)) in tegra_plane_overlap_mask()
2370 overlap_mask |= BIT(tegra->index); in tegra_plane_overlap_mask()
2384 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_calculate_memory_bandwidth() local
2390 * The nv-display uses shared planes. The algorithm below assumes in tegra_crtc_calculate_memory_bandwidth()
2391 * maximum 3 planes per-CRTC, this assumption isn't applicable to in tegra_crtc_calculate_memory_bandwidth()
2392 * the nv-display. Note that T124 support has additional windows, in tegra_crtc_calculate_memory_bandwidth()
2395 if (dc->soc->has_nvdisplay) in tegra_crtc_calculate_memory_bandwidth()
2403 * This needs to be taken into account for calculating total bandwidth in tegra_crtc_calculate_memory_bandwidth()
2409 * to make further code nicer and simpler. in tegra_crtc_calculate_memory_bandwidth()
2415 if (WARN_ON_ONCE(tegra->index >= TEGRA_DC_LEGACY_PLANES_NUM)) in tegra_crtc_calculate_memory_bandwidth()
2416 return -EINVAL; in tegra_crtc_calculate_memory_bandwidth()
2418 plane_peak_bw[tegra->index] = tegra_state->peak_memory_bandwidth; in tegra_crtc_calculate_memory_bandwidth()
2420 overlap_mask[tegra->index] = mask; in tegra_crtc_calculate_memory_bandwidth()
2429 * overlapping planes, where "simultaneously" means areas where DC in tegra_crtc_calculate_memory_bandwidth()
2430 * fetches from the planes simultaneously during of scan-out process. in tegra_crtc_calculate_memory_bandwidth()
2434 * A-and-B or A-and-C planes overlap. in tegra_crtc_calculate_memory_bandwidth()
2438 * in order to set up latency allowance based on the peak BW, see in tegra_crtc_calculate_memory_bandwidth()
2453 for_each_set_bit(i, &overlap_mask[tegra->index], 3) { in tegra_crtc_calculate_memory_bandwidth()
2454 if (i == tegra->index) in tegra_crtc_calculate_memory_bandwidth()
2463 new_peak_bw = plane_peak_bw[tegra->index] + overlap_bw; in tegra_crtc_calculate_memory_bandwidth()
2464 old_peak_bw = tegra_state->total_peak_memory_bandwidth; in tegra_crtc_calculate_memory_bandwidth()
2469 * then add plane to the state in order to have the bandwidth in tegra_crtc_calculate_memory_bandwidth()
2481 new_tegra_state->total_peak_memory_bandwidth = new_peak_bw; in tegra_crtc_calculate_memory_bandwidth()
2504 * Display bandwidth is allowed to go down only once hardware state in tegra_crtc_atomic_post_commit()
2505 * is known to be armed, i.e. state was committed and VBLANK event in tegra_crtc_atomic_post_commit()
2521 struct tegra_dc *dc = data; in tegra_dc_irq() local
2524 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); in tegra_dc_irq()
2525 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); in tegra_dc_irq()
2529 dev_dbg(dc->dev, "%s(): frame end\n", __func__); in tegra_dc_irq()
2531 dc->stats.frames_total++; in tegra_dc_irq()
2532 dc->stats.frames++; in tegra_dc_irq()
2537 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); in tegra_dc_irq()
2539 drm_crtc_handle_vblank(&dc->base); in tegra_dc_irq()
2540 dc->stats.vblank_total++; in tegra_dc_irq()
2541 dc->stats.vblank++; in tegra_dc_irq()
2546 dev_dbg(dc->dev, "%s(): underflow\n", __func__); in tegra_dc_irq()
2548 dc->stats.underflow_total++; in tegra_dc_irq()
2549 dc->stats.underflow++; in tegra_dc_irq()
2554 dev_dbg(dc->dev, "%s(): overflow\n", __func__); in tegra_dc_irq()
2556 dc->stats.overflow_total++; in tegra_dc_irq()
2557 dc->stats.overflow++; in tegra_dc_irq()
2561 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); in tegra_dc_irq()
2562 dc->stats.underflow_total++; in tegra_dc_irq()
2563 dc->stats.underflow++; in tegra_dc_irq()
2569 static bool tegra_dc_has_window_groups(struct tegra_dc *dc) in tegra_dc_has_window_groups() argument
2573 if (!dc->soc->wgrps) in tegra_dc_has_window_groups()
2576 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_has_window_groups()
2577 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_has_window_groups()
2579 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) in tegra_dc_has_window_groups()
2588 struct drm_device *drm = dev_get_drvdata(client->host); in tegra_dc_early_init()
2589 struct tegra_drm *tegra = drm->dev_private; in tegra_dc_early_init()
2591 tegra->num_crtcs++; in tegra_dc_early_init()
2598 struct drm_device *drm = dev_get_drvdata(client->host); in tegra_dc_init()
2600 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_init() local
2601 struct tegra_drm *tegra = drm->dev_private; in tegra_dc_init()
2607 * DC has been reset by now, so VBLANK syncpoint can be released in tegra_dc_init()
2610 host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe); in tegra_dc_init()
2614 * assign a primary plane to them, which in turn will cause KMS to in tegra_dc_init()
2617 if (!tegra_dc_has_window_groups(dc)) in tegra_dc_init()
2626 if (dc->soc->has_nvdisplay) in tegra_dc_init()
2627 client->parent = &tegra->hub->client; in tegra_dc_init()
2629 dc->syncpt = host1x_syncpt_request(client, flags); in tegra_dc_init()
2630 if (!dc->syncpt) in tegra_dc_init()
2631 dev_warn(dc->dev, "failed to allocate syncpoint\n"); in tegra_dc_init()
2634 if (err < 0 && err != -ENODEV) { in tegra_dc_init()
2635 dev_err(client->dev, "failed to attach to domain: %d\n", err); in tegra_dc_init()
2639 if (dc->soc->wgrps) in tegra_dc_init()
2640 primary = tegra_dc_add_shared_planes(drm, dc); in tegra_dc_init()
2642 primary = tegra_dc_add_planes(drm, dc); in tegra_dc_init()
2649 if (dc->soc->supports_cursor) { in tegra_dc_init()
2650 cursor = tegra_dc_cursor_plane_create(drm, dc); in tegra_dc_init()
2656 /* dedicate one overlay to mouse cursor */ in tegra_dc_init()
2657 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true); in tegra_dc_init()
2664 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, in tegra_dc_init()
2669 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); in tegra_dc_init()
2675 if (dc->soc->pitch_align > tegra->pitch_align) in tegra_dc_init()
2676 tegra->pitch_align = dc->soc->pitch_align; in tegra_dc_init()
2679 if (dc->soc->has_nvdisplay) in tegra_dc_init()
2680 drm->mode_config.max_width = drm->mode_config.max_height = 16384; in tegra_dc_init()
2682 drm->mode_config.max_width = drm->mode_config.max_height = 4096; in tegra_dc_init()
2684 err = tegra_dc_rgb_init(drm, dc); in tegra_dc_init()
2685 if (err < 0 && err != -ENODEV) { in tegra_dc_init()
2686 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); in tegra_dc_init()
2690 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, in tegra_dc_init()
2691 dev_name(dc->dev), dc); in tegra_dc_init()
2693 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, in tegra_dc_init()
2702 client->dev->dma_parms = client->host->dma_parms; in tegra_dc_init()
2714 host1x_syncpt_put(dc->syncpt); in tegra_dc_init()
2721 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_exit() local
2724 if (!tegra_dc_has_window_groups(dc)) in tegra_dc_exit()
2728 client->dev->dma_parms = NULL; in tegra_dc_exit()
2730 devm_free_irq(dc->dev, dc->irq, dc); in tegra_dc_exit()
2732 err = tegra_dc_rgb_exit(dc); in tegra_dc_exit()
2734 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); in tegra_dc_exit()
2739 host1x_syncpt_put(dc->syncpt); in tegra_dc_exit()
2746 struct drm_device *drm = dev_get_drvdata(client->host); in tegra_dc_late_exit()
2747 struct tegra_drm *tegra = drm->dev_private; in tegra_dc_late_exit()
2749 tegra->num_crtcs--; in tegra_dc_late_exit()
2756 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_runtime_suspend() local
2757 struct device *dev = client->dev; in tegra_dc_runtime_suspend()
2760 err = reset_control_assert(dc->rst); in tegra_dc_runtime_suspend()
2762 dev_err(dev, "failed to assert reset: %d\n", err); in tegra_dc_runtime_suspend()
2766 if (dc->soc->has_powergate) in tegra_dc_runtime_suspend()
2767 tegra_powergate_power_off(dc->powergate); in tegra_dc_runtime_suspend()
2769 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_suspend()
2777 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_runtime_resume() local
2778 struct device *dev = client->dev; in tegra_dc_runtime_resume()
2783 dev_err(dev, "failed to get runtime PM: %d\n", err); in tegra_dc_runtime_resume()
2787 if (dc->soc->has_powergate) { in tegra_dc_runtime_resume()
2788 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, in tegra_dc_runtime_resume()
2789 dc->rst); in tegra_dc_runtime_resume()
2791 dev_err(dev, "failed to power partition: %d\n", err); in tegra_dc_runtime_resume()
2795 err = clk_prepare_enable(dc->clk); in tegra_dc_runtime_resume()
2797 dev_err(dev, "failed to enable clock: %d\n", err); in tegra_dc_runtime_resume()
2801 err = reset_control_deassert(dc->rst); in tegra_dc_runtime_resume()
2803 dev_err(dev, "failed to deassert reset: %d\n", err); in tegra_dc_runtime_resume()
2811 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_resume()
2944 .dc = 0,
2949 .dc = 1,
2954 .dc = 1,
2959 .dc = 2,
2964 .dc = 2,
2969 .dc = 2,
2995 .dc = 0,
3000 .dc = 1,
3005 .dc = 1,
3010 .dc = 2,
3015 .dc = 2,
3020 .dc = 2,
3045 .compatible = "nvidia,tegra194-dc",
3048 .compatible = "nvidia,tegra186-dc",
3051 .compatible = "nvidia,tegra210-dc",
3054 .compatible = "nvidia,tegra124-dc",
3057 .compatible = "nvidia,tegra114-dc",
3060 .compatible = "nvidia,tegra30-dc",
3063 .compatible = "nvidia,tegra20-dc",
3071 static int tegra_dc_parse_dt(struct tegra_dc *dc) in tegra_dc_parse_dt() argument
3077 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); in tegra_dc_parse_dt()
3079 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); in tegra_dc_parse_dt()
3082 * If the nvidia,head property isn't present, try to find the in tegra_dc_parse_dt()
3094 if (np == dc->dev->of_node) { in tegra_dc_parse_dt()
3103 dc->pipe = value; in tegra_dc_parse_dt()
3110 struct tegra_dc *dc = dev_get_drvdata(dev); in tegra_dc_match_by_pipe() local
3113 return dc->pipe == pipe; in tegra_dc_match_by_pipe()
3116 static int tegra_dc_couple(struct tegra_dc *dc) in tegra_dc_couple() argument
3119 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to in tegra_dc_couple()
3120 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND / in tegra_dc_couple()
3123 if (dc->soc->coupled_pm && dc->pipe == 1) { in tegra_dc_couple()
3127 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0, in tegra_dc_couple()
3130 return -EPROBE_DEFER; in tegra_dc_couple()
3133 dc->client.parent = &parent->client; in tegra_dc_couple()
3135 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion)); in tegra_dc_couple()
3141 static int tegra_dc_init_opp_table(struct tegra_dc *dc) in tegra_dc_init_opp_table() argument
3146 err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params); in tegra_dc_init_opp_table()
3147 if (err && err != -ENODEV) in tegra_dc_init_opp_table()
3151 dc->has_opp_table = false; in tegra_dc_init_opp_table()
3153 dc->has_opp_table = true; in tegra_dc_init_opp_table()
3160 u64 dma_mask = dma_get_mask(pdev->dev.parent); in tegra_dc_probe()
3161 struct tegra_dc *dc; in tegra_dc_probe() local
3164 err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask); in tegra_dc_probe()
3166 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); in tegra_dc_probe()
3170 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); in tegra_dc_probe()
3171 if (!dc) in tegra_dc_probe()
3172 return -ENOMEM; in tegra_dc_probe()
3174 dc->soc = of_device_get_match_data(&pdev->dev); in tegra_dc_probe()
3176 INIT_LIST_HEAD(&dc->list); in tegra_dc_probe()
3177 dc->dev = &pdev->dev; in tegra_dc_probe()
3179 err = tegra_dc_parse_dt(dc); in tegra_dc_probe()
3183 err = tegra_dc_couple(dc); in tegra_dc_probe()
3187 dc->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dc_probe()
3188 if (IS_ERR(dc->clk)) { in tegra_dc_probe()
3189 dev_err(&pdev->dev, "failed to get clock\n"); in tegra_dc_probe()
3190 return PTR_ERR(dc->clk); in tegra_dc_probe()
3193 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); in tegra_dc_probe()
3194 if (IS_ERR(dc->rst)) { in tegra_dc_probe()
3195 dev_err(&pdev->dev, "failed to get reset\n"); in tegra_dc_probe()
3196 return PTR_ERR(dc->rst); in tegra_dc_probe()
3200 err = clk_prepare_enable(dc->clk); in tegra_dc_probe()
3206 err = reset_control_assert(dc->rst); in tegra_dc_probe()
3208 clk_disable_unprepare(dc->clk); in tegra_dc_probe()
3214 clk_disable_unprepare(dc->clk); in tegra_dc_probe()
3216 if (dc->soc->has_powergate) { in tegra_dc_probe()
3217 if (dc->pipe == 0) in tegra_dc_probe()
3218 dc->powergate = TEGRA_POWERGATE_DIS; in tegra_dc_probe()
3220 dc->powergate = TEGRA_POWERGATE_DISB; in tegra_dc_probe()
3222 tegra_powergate_power_off(dc->powergate); in tegra_dc_probe()
3225 err = tegra_dc_init_opp_table(dc); in tegra_dc_probe()
3229 dc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_dc_probe()
3230 if (IS_ERR(dc->regs)) in tegra_dc_probe()
3231 return PTR_ERR(dc->regs); in tegra_dc_probe()
3233 dc->irq = platform_get_irq(pdev, 0); in tegra_dc_probe()
3234 if (dc->irq < 0) in tegra_dc_probe()
3235 return -ENXIO; in tegra_dc_probe()
3237 err = tegra_dc_rgb_probe(dc); in tegra_dc_probe()
3238 if (err < 0 && err != -ENODEV) in tegra_dc_probe()
3239 return dev_err_probe(&pdev->dev, err, in tegra_dc_probe()
3240 "failed to probe RGB output\n"); in tegra_dc_probe()
3242 platform_set_drvdata(pdev, dc); in tegra_dc_probe()
3243 pm_runtime_enable(&pdev->dev); in tegra_dc_probe()
3245 INIT_LIST_HEAD(&dc->client.list); in tegra_dc_probe()
3246 dc->client.ops = &dc_client_ops; in tegra_dc_probe()
3247 dc->client.dev = &pdev->dev; in tegra_dc_probe()
3249 err = host1x_client_register(&dc->client); in tegra_dc_probe()
3251 dev_err(&pdev->dev, "failed to register host1x client: %d\n", in tegra_dc_probe()
3259 pm_runtime_disable(&pdev->dev); in tegra_dc_probe()
3260 tegra_dc_rgb_remove(dc); in tegra_dc_probe()
3267 struct tegra_dc *dc = platform_get_drvdata(pdev); in tegra_dc_remove() local
3269 host1x_client_unregister(&dc->client); in tegra_dc_remove()
3271 tegra_dc_rgb_remove(dc); in tegra_dc_remove()
3273 pm_runtime_disable(&pdev->dev); in tegra_dc_remove()
3278 .name = "tegra-dc",