Lines Matching +full:0 +full:x41c
19 #define LDDCKPAT1R 0x400
20 #define LDDCKPAT2R 0x404
21 #define LDDCKR 0x410
22 #define LDDCKR_ICKSEL_BUS (0 << 16)
28 #define LDDCKSTPR 0x414
30 #define LDDCKSTPR_DCKSTP (1 << 0)
31 #define LDMT1R 0x418
40 #define LDMT1R_MIFTYP_RGB8 (0x0 << 0)
41 #define LDMT1R_MIFTYP_RGB9 (0x4 << 0)
42 #define LDMT1R_MIFTYP_RGB12A (0x5 << 0)
43 #define LDMT1R_MIFTYP_RGB12B (0x6 << 0)
44 #define LDMT1R_MIFTYP_RGB16 (0x7 << 0)
45 #define LDMT1R_MIFTYP_RGB18 (0xa << 0)
46 #define LDMT1R_MIFTYP_RGB24 (0xb << 0)
47 #define LDMT1R_MIFTYP_YCBCR (0xf << 0)
48 #define LDMT1R_MIFTYP_SYS8A (0x0 << 0)
49 #define LDMT1R_MIFTYP_SYS8B (0x1 << 0)
50 #define LDMT1R_MIFTYP_SYS8C (0x2 << 0)
51 #define LDMT1R_MIFTYP_SYS8D (0x3 << 0)
52 #define LDMT1R_MIFTYP_SYS9 (0x4 << 0)
53 #define LDMT1R_MIFTYP_SYS12 (0x5 << 0)
54 #define LDMT1R_MIFTYP_SYS16A (0x7 << 0)
55 #define LDMT1R_MIFTYP_SYS16B (0x8 << 0)
56 #define LDMT1R_MIFTYP_SYS16C (0x9 << 0)
57 #define LDMT1R_MIFTYP_SYS18 (0xa << 0)
58 #define LDMT1R_MIFTYP_SYS24 (0xb << 0)
59 #define LDMT1R_MIFTYP_MASK (0xf << 0)
60 #define LDMT2R 0x41c
65 #define LDMT2R_WCSC_MASK (0xff << 16)
67 #define LDMT2R_WCEC_MASK (0xff << 8)
69 #define LDMT2R_WCLW_MASK (0xff << 0)
70 #define LDMT2R_WCLW_SHIFT 0
71 #define LDMT3R 0x420
72 #define LDMT3R_RDLC_MASK (0x3f << 24)
74 #define LDMT3R_RCSC_MASK (0xff << 16)
76 #define LDMT3R_RCEC_MASK (0xff << 8)
78 #define LDMT3R_RCLW_MASK (0xff << 0)
79 #define LDMT3R_RCLW_SHIFT 0
80 #define LDDFR 0x424
84 #define LDDFR_YF_420 (0 << 8)
88 #define LDDFR_PKF_ARGB32 (0x00 << 0)
89 #define LDDFR_PKF_RGB16 (0x03 << 0)
90 #define LDDFR_PKF_RGB24 (0x0b << 0)
91 #define LDDFR_PKF_MASK (0x1f << 0)
92 #define LDSM1R 0x428
93 #define LDSM1R_OS (1 << 0)
94 #define LDSM2R 0x42c
95 #define LDSM2R_OSTRG (1 << 0)
96 #define LDSA1R 0x430
97 #define LDSA2R 0x434
98 #define LDMLSR 0x438
99 #define LDWBFR 0x43c
100 #define LDWBCNTR 0x440
101 #define LDWBAR 0x444
102 #define LDHCNR 0x448
103 #define LDHSYNR 0x44c
104 #define LDVLNR 0x450
105 #define LDVSYNR 0x454
106 #define LDHPDR 0x458
107 #define LDVPDR 0x45c
108 #define LDPMR 0x460
109 #define LDPMR_LPS (3 << 0)
110 #define LDINTR 0x468
116 #define LDINTR_VES (1 << 0)
117 #define LDINTR_STATUS_MASK (0xff << 0)
118 #define LDSR 0x46c
122 #define LDCNT1R 0x470
123 #define LDCNT1R_DE (1 << 0)
124 #define LDCNT2R 0x474
129 #define LDCNT2R_DO (1 << 0)
130 #define LDRCNTR 0x478
134 #define LDRCNTR_MRC (1 << 0)
135 #define LDDDSR 0x47c
138 #define LDDDSR_BS (1 << 0)
139 #define LDHAJR 0x4a0
141 #define LDDWD0R 0x800
144 #define LDDRDR 0x840
146 #define LDDRDR_DRD_MASK (0x3ffff << 0)
147 #define LDDWAR 0x900
148 #define LDDWAR_WA (1 << 0)
149 #define LDDRAR 0x904
150 #define LDDRAR_RA (1 << 0)
152 #define LDBCR 0xb00
155 #define LDBCR_UPD(n) (1 << ((n) + 0))
156 #define LDBnBSIFR(n) (0xb20 + (n) * 0x20 + 0x00)
165 #define LDBBSIFR_CV0 (0 << 24)
167 #define LDBBSIFR_LAY_MASK (0xff << 16)
169 #define LDBBSIFR_ROP3_MASK (0xff << 16)
174 #define LDBBSIFR_AL_1 (0 << 14)
180 #define LDBBSIFR_CHRR_420 (2 << 0)
181 #define LDBBSIFR_CHRR_422 (1 << 0)
182 #define LDBBSIFR_CHRR_444 (0 << 0)
183 #define LDBBSIFR_RPKF_ARGB32 (0x00 << 0)
184 #define LDBBSIFR_RPKF_RGB16 (0x03 << 0)
185 #define LDBBSIFR_RPKF_RGB24 (0x0b << 0)
186 #define LDBBSIFR_RPKF_MASK (0x1f << 0)
187 #define LDBnBSSZR(n) (0xb20 + (n) * 0x20 + 0x04)
188 #define LDBBSSZR_BVSS_MASK (0xfff << 16)
190 #define LDBBSSZR_BHSS_MASK (0xfff << 0)
191 #define LDBBSSZR_BHSS_SHIFT 0
192 #define LDBnBLOCR(n) (0xb20 + (n) * 0x20 + 0x08)
193 #define LDBBLOCR_CVLC_MASK (0xfff << 16)
195 #define LDBBLOCR_CHLC_MASK (0xfff << 0)
196 #define LDBBLOCR_CHLC_SHIFT 0
197 #define LDBnBSMWR(n) (0xb20 + (n) * 0x20 + 0x0c)
198 #define LDBBSMWR_BSMWA_MASK (0xffff << 16)
200 #define LDBBSMWR_BSMW_MASK (0xffff << 0)
201 #define LDBBSMWR_BSMW_SHIFT 0
202 #define LDBnBSAYR(n) (0xb20 + (n) * 0x20 + 0x10)
203 #define LDBBSAYR_FG1A_MASK (0xff << 24)
205 #define LDBBSAYR_FG1R_MASK (0xff << 16)
207 #define LDBBSAYR_FG1G_MASK (0xff << 8)
209 #define LDBBSAYR_FG1B_MASK (0xff << 0)
210 #define LDBBSAYR_FG1B_SHIFT 0
211 #define LDBnBSACR(n) (0xb20 + (n) * 0x20 + 0x14)
212 #define LDBBSACR_FG2A_MASK (0xff << 24)
214 #define LDBBSACR_FG2R_MASK (0xff << 16)
216 #define LDBBSACR_FG2G_MASK (0xff << 8)
218 #define LDBBSACR_FG2B_MASK (0xff << 0)
219 #define LDBBSACR_FG2B_SHIFT 0
220 #define LDBnBSAAR(n) (0xb20 + (n) * 0x20 + 0x18)
221 #define LDBBSAAR_AP_MASK (0xff << 24)
223 #define LDBBSAAR_R_MASK (0xff << 16)
225 #define LDBBSAAR_GY_MASK (0xff << 8)
227 #define LDBBSAAR_B_MASK (0xff << 0)
228 #define LDBBSAAR_B_SHIFT 0
229 #define LDBnBPPCR(n) (0xb20 + (n) * 0x20 + 0x1c)
230 #define LDBBPPCR_AP_MASK (0xff << 24)
232 #define LDBBPPCR_R_MASK (0xff << 16)
234 #define LDBBPPCR_GY_MASK (0xff << 8)
236 #define LDBBPPCR_B_MASK (0xff << 0)
237 #define LDBBPPCR_B_SHIFT 0
238 #define LDBnBBGCL(n) (0xb10 + (n) * 0x04)
239 #define LDBBBGCL_BGA_MASK (0xff << 24)
241 #define LDBBBGCL_BGR_MASK (0xff << 16)
243 #define LDBBBGCL_BGG_MASK (0xff << 8)
245 #define LDBBBGCL_BGB_MASK (0xff << 0)
246 #define LDBBBGCL_BGB_SHIFT 0
248 #define LCDC_SIDE_B_OFFSET 0x1000
249 #define LCDC_MIRROR_OFFSET 0x2000
274 return reg >= LDBnBBGCL(0) && reg <= LDBnBPPCR(3); in lcdc_is_banked()
307 return 0; in lcdc_wait_bit()