Lines Matching +full:battery +full:- +full:profile
306 struct trinity_ps *ps = rps->ps_priv; in trinity_get_ps()
313 struct trinity_power_info *pi = rdev->pm.dpm.priv; in trinity_get_pi()
348 if (pi->override_dynamic_mgpg && (hw_rev == 0)) in trinity_gfx_powergating_initialize()
505 if (pi->enable_gfx_clock_gating) in trinity_enable_clock_power_gating()
507 if (pi->enable_mg_clock_gating) in trinity_enable_clock_power_gating()
509 if (pi->enable_gfx_power_gating) in trinity_enable_clock_power_gating()
511 if (pi->enable_mg_clock_gating) { in trinity_enable_clock_power_gating()
515 if (pi->enable_gfx_clock_gating) in trinity_enable_clock_power_gating()
517 if (pi->enable_gfx_dynamic_mgpg) in trinity_enable_clock_power_gating()
519 if (pi->enable_gfx_power_gating) in trinity_enable_clock_power_gating()
527 if (pi->enable_gfx_power_gating) in trinity_disable_clock_power_gating()
529 if (pi->enable_gfx_dynamic_mgpg) in trinity_disable_clock_power_gating()
531 if (pi->enable_gfx_clock_gating) in trinity_disable_clock_power_gating()
533 if (pi->enable_mg_clock_gating) { in trinity_disable_clock_power_gating()
595 u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid); in trinity_set_vid()
678 trinity_set_divider_value(rdev, index, pl->sclk); in trinity_program_power_level()
679 trinity_set_vid(rdev, index, pl->vddc_index); in trinity_program_power_level()
680 trinity_set_ss_dividers(rdev, index, pl->ss_divider_index); in trinity_program_power_level()
681 trinity_set_ds_dividers(rdev, index, pl->ds_divider_index); in trinity_program_power_level()
682 trinity_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow); in trinity_program_power_level()
683 trinity_set_force_nbp_state(rdev, index, pl->force_nbp_state); in trinity_program_power_level()
684 trinity_set_display_wm(rdev, index, pl->display_wm); in trinity_program_power_level()
685 trinity_set_vce_wm(rdev, index, pl->vce_wm); in trinity_program_power_level()
686 trinity_set_at(rdev, index, pi->at[index]); in trinity_program_power_level()
728 for (i = 0; i < rdev->usec_timeout; i++) { in trinity_wait_for_dpm_enabled()
733 for (i = 0; i < rdev->usec_timeout; i++) { in trinity_wait_for_dpm_enabled()
738 for (i = 0; i < rdev->usec_timeout; i++) { in trinity_wait_for_dpm_enabled()
773 for (i = 0; i < rdev->usec_timeout; i++) { in trinity_wait_for_level_0()
802 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; in trinity_program_power_levels_0_to_n()
804 for (i = 0; i < new_ps->num_levels; i++) { in trinity_program_power_levels_0_to_n()
805 trinity_program_power_level(rdev, &new_ps->levels[i], i); in trinity_program_power_levels_0_to_n()
809 for (i = new_ps->num_levels; i < n_current_state_levels; i++) in trinity_program_power_levels_0_to_n()
818 trinity_program_power_level(rdev, &pi->boot_pl, 0); in trinity_program_bootup_state()
829 u32 uvdstates = (ps->vclk_low_divider | in trinity_setup_uvd_clock_table()
830 ps->vclk_high_divider << 8 | in trinity_setup_uvd_clock_table()
831 ps->dclk_low_divider << 16 | in trinity_setup_uvd_clock_table()
832 ps->dclk_high_divider << 24); in trinity_setup_uvd_clock_table()
847 val = (p + tp - 1) / tp; in trinity_setup_uvd_dpm_interval()
854 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
866 if ((rps1->vclk == rps2->vclk) && in trinity_uvd_clocks_equal()
867 (rps1->dclk == rps2->dclk) && in trinity_uvd_clocks_equal()
868 (ps1->vclk_low_divider == ps2->vclk_low_divider) && in trinity_uvd_clocks_equal()
869 (ps1->vclk_high_divider == ps2->vclk_high_divider) && in trinity_uvd_clocks_equal()
870 (ps1->dclk_low_divider == ps2->dclk_low_divider) && in trinity_uvd_clocks_equal()
871 (ps1->dclk_high_divider == ps2->dclk_high_divider)) in trinity_uvd_clocks_equal()
883 if (pi->enable_gfx_power_gating) { in trinity_setup_uvd_clocks()
887 if (pi->uvd_dpm) { in trinity_setup_uvd_clocks()
899 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
910 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
913 if (pi->enable_gfx_power_gating) { in trinity_setup_uvd_clocks()
925 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
926 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
939 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
940 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
950 if ((old_rps->evclk != new_rps->evclk) || in trinity_set_vce_clock()
951 (old_rps->ecclk != new_rps->ecclk)) { in trinity_set_vce_clock()
953 if (new_rps->evclk || new_rps->ecclk) in trinity_set_vce_clock()
957 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in trinity_set_vce_clock()
967 value |= HT((pi->thermal_auto_throttling + 49) * 8); in trinity_program_ttt()
968 value |= LT((pi->thermal_auto_throttling + 49 - pi->sys_info.htc_hyst_lmt) * 8); in trinity_program_ttt()
991 ni = (p + tp - 1) / tp; in trinity_program_sclk_dpm()
1010 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); in trinity_set_thermal_temperature_range()
1011 return -EINVAL; in trinity_set_thermal_temperature_range()
1017 rdev->pm.dpm.thermal.min_temp = low_temp; in trinity_set_thermal_temperature_range()
1018 rdev->pm.dpm.thermal.max_temp = high_temp; in trinity_set_thermal_temperature_range()
1029 pi->current_rps = *rps; in trinity_update_current_ps()
1030 pi->current_ps = *new_ps; in trinity_update_current_ps()
1031 pi->current_rps.ps_priv = &pi->current_ps; in trinity_update_current_ps()
1040 pi->requested_rps = *rps; in trinity_update_requested_ps()
1041 pi->requested_ps = *new_ps; in trinity_update_requested_ps()
1042 pi->requested_rps.ps_priv = &pi->requested_ps; in trinity_update_requested_ps()
1049 if (pi->enable_bapm) { in trinity_dpm_enable_bapm()
1064 return -EINVAL; in trinity_dpm_enable()
1070 if (pi->enable_auto_thermal_throttling) { in trinity_dpm_enable()
1080 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in trinity_dpm_enable()
1092 if (rdev->irq.installed && in trinity_dpm_late_enable()
1093 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { in trinity_dpm_late_enable()
1099 rdev->irq.dpm_thermal = true; in trinity_dpm_late_enable()
1122 if (rdev->irq.installed && in trinity_dpm_disable()
1123 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { in trinity_dpm_disable()
1124 rdev->irq.dpm_thermal = false; in trinity_dpm_disable()
1128 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in trinity_dpm_disable()
1135 pi->min_sclk_did = in trinity_get_min_sclk_divider()
1146 if (pi->sys_info.nb_dpm_enable) { in trinity_setup_nbp_sim()
1149 nbpsconfig |= (Dpm0PgNbPsLo(new_ps->Dpm0PgNbPsLo) | in trinity_setup_nbp_sim()
1150 Dpm0PgNbPsHi(new_ps->Dpm0PgNbPsHi) | in trinity_setup_nbp_sim()
1151 DpmXNbPsLo(new_ps->DpmXNbPsLo) | in trinity_setup_nbp_sim()
1152 DpmXNbPsHi(new_ps->DpmXNbPsHi)); in trinity_setup_nbp_sim()
1161 struct radeon_ps *rps = &pi->current_rps; in trinity_dpm_force_performance_level()
1165 if (ps->num_levels <= 1) in trinity_dpm_force_performance_level()
1170 return -EINVAL; in trinity_dpm_force_performance_level()
1172 ret = trinity_dpm_n_levels_disabled(rdev, ps->num_levels - 1); in trinity_dpm_force_performance_level()
1176 for (i = 0; i < ps->num_levels; i++) { in trinity_dpm_force_performance_level()
1183 rdev->pm.dpm.forced_level = level; in trinity_dpm_force_performance_level()
1191 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in trinity_dpm_pre_set_power_state()
1197 &pi->requested_rps, in trinity_dpm_pre_set_power_state()
1198 &pi->current_rps); in trinity_dpm_pre_set_power_state()
1206 struct radeon_ps *new_ps = &pi->requested_rps; in trinity_dpm_set_power_state()
1207 struct radeon_ps *old_ps = &pi->current_rps; in trinity_dpm_set_power_state()
1210 if (pi->enable_dpm) { in trinity_dpm_set_power_state()
1211 if (pi->enable_bapm) in trinity_dpm_set_power_state()
1212 trinity_dpm_bapm_enable(rdev, rdev->pm.dpm.ac_power); in trinity_dpm_set_power_state()
1232 struct radeon_ps *new_ps = &pi->requested_rps; in trinity_dpm_post_set_power_state()
1252 if (pi->enable_dpm) {
1268 u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit); in trinity_convert_voltage_index_to_value()
1276 return (155000 - delta) / 100; in trinity_convert_voltage_index_to_value()
1284 ps->num_levels = 1; in trinity_patch_boot_state()
1285 ps->nbps_flags = 0; in trinity_patch_boot_state()
1286 ps->bapm_flags = 0; in trinity_patch_boot_state()
1287 ps->levels[0] = pi->boot_pl; in trinity_patch_boot_state()
1301 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; in trinity_construct_boot_state()
1302 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; in trinity_construct_boot_state()
1303 pi->boot_pl.ds_divider_index = 0; in trinity_construct_boot_state()
1304 pi->boot_pl.ss_divider_index = 0; in trinity_construct_boot_state()
1305 pi->boot_pl.allow_gnb_slow = 1; in trinity_construct_boot_state()
1306 pi->boot_pl.force_nbp_state = 0; in trinity_construct_boot_state()
1307 pi->boot_pl.display_wm = 0; in trinity_construct_boot_state()
1308 pi->boot_pl.vce_wm = 0; in trinity_construct_boot_state()
1309 pi->current_ps.num_levels = 1; in trinity_construct_boot_state()
1310 pi->current_ps.levels[0] = pi->boot_pl; in trinity_construct_boot_state()
1325 if (!pi->enable_sclk_ds) in trinity_get_sleep_divider_id_from_clock()
1328 for (i = TRINITY_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { in trinity_get_sleep_divider_id_from_clock()
1343 for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) { in trinity_get_valid_engine_clock()
1344 if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit) in trinity_get_valid_engine_clock()
1345 return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency; in trinity_get_valid_engine_clock()
1348 if (i == pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries) in trinity_get_valid_engine_clock()
1359 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ in trinity_patch_thermal_state()
1365 current_vddc = current_ps->levels[current_index].vddc_index; in trinity_patch_thermal_state()
1366 current_sclk = current_ps->levels[current_index].sclk; in trinity_patch_thermal_state()
1368 current_vddc = pi->boot_pl.vddc_index; in trinity_patch_thermal_state()
1369 current_sclk = pi->boot_pl.sclk; in trinity_patch_thermal_state()
1372 ps->levels[0].vddc_index = current_vddc; in trinity_patch_thermal_state()
1374 if (ps->levels[0].sclk > current_sclk) in trinity_patch_thermal_state()
1375 ps->levels[0].sclk = current_sclk; in trinity_patch_thermal_state()
1377 ps->levels[0].ds_divider_index = in trinity_patch_thermal_state()
1378 trinity_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr); in trinity_patch_thermal_state()
1379 ps->levels[0].ss_divider_index = ps->levels[0].ds_divider_index; in trinity_patch_thermal_state()
1380 ps->levels[0].allow_gnb_slow = 1; in trinity_patch_thermal_state()
1381 ps->levels[0].force_nbp_state = 0; in trinity_patch_thermal_state()
1382 ps->levels[0].display_wm = 0; in trinity_patch_thermal_state()
1383 ps->levels[0].vce_wm = in trinity_patch_thermal_state()
1384 trinity_calculate_vce_wm(rdev, ps->levels[0].sclk); in trinity_patch_thermal_state()
1390 if (ps == NULL || ps->num_levels <= 1) in trinity_calculate_display_wm()
1392 else if (ps->num_levels == 2) { in trinity_calculate_display_wm()
1400 else if (ps->levels[index].sclk < 30000) in trinity_calculate_display_wm()
1414 if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) && in trinity_get_uvd_clock_index()
1415 (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk)) in trinity_get_uvd_clock_index()
1434 if (pi->uvd_dpm && r600_is_uvd_state(rps->class, rps->class2)) { in trinity_adjust_uvd_state()
1449 ps->vclk_low_divider = in trinity_adjust_uvd_state()
1450 pi->sys_info.uvd_clock_table_entries[high_index].vclk_did; in trinity_adjust_uvd_state()
1451 ps->dclk_low_divider = in trinity_adjust_uvd_state()
1452 pi->sys_info.uvd_clock_table_entries[high_index].dclk_did; in trinity_adjust_uvd_state()
1453 ps->vclk_high_divider = in trinity_adjust_uvd_state()
1454 pi->sys_info.uvd_clock_table_entries[low_index].vclk_did; in trinity_adjust_uvd_state()
1455 ps->dclk_high_divider = in trinity_adjust_uvd_state()
1456 pi->sys_info.uvd_clock_table_entries[low_index].dclk_did; in trinity_adjust_uvd_state()
1464 int ret = -EINVAL; in trinity_get_vce_clock_voltage()
1466 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in trinity_get_vce_clock_voltage()
1469 (table && (table->count == 0))) { in trinity_get_vce_clock_voltage()
1474 for (i = 0; i < table->count; i++) { in trinity_get_vce_clock_voltage()
1475 if ((evclk <= table->entries[i].evclk) && in trinity_get_vce_clock_voltage()
1476 (ecclk <= table->entries[i].ecclk)) { in trinity_get_vce_clock_voltage()
1477 *voltage = table->entries[i].v; in trinity_get_vce_clock_voltage()
1485 *voltage = table->entries[table->count - 1].v; in trinity_get_vce_clock_voltage()
1498 u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */ in trinity_apply_state_adjust_rules()
1499 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ in trinity_apply_state_adjust_rules()
1503 u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count; in trinity_apply_state_adjust_rules()
1505 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) in trinity_apply_state_adjust_rules()
1510 if (new_rps->vce_active) { in trinity_apply_state_adjust_rules()
1511 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in trinity_apply_state_adjust_rules()
1512 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in trinity_apply_state_adjust_rules()
1514 new_rps->evclk = 0; in trinity_apply_state_adjust_rules()
1515 new_rps->ecclk = 0; in trinity_apply_state_adjust_rules()
1518 for (i = 0; i < ps->num_levels; i++) { in trinity_apply_state_adjust_rules()
1519 if (ps->levels[i].vddc_index < min_voltage) in trinity_apply_state_adjust_rules()
1520 ps->levels[i].vddc_index = min_voltage; in trinity_apply_state_adjust_rules()
1522 if (ps->levels[i].sclk < min_sclk) in trinity_apply_state_adjust_rules()
1523 ps->levels[i].sclk = in trinity_apply_state_adjust_rules()
1527 if (new_rps->vce_active) { in trinity_apply_state_adjust_rules()
1529 if (ps->levels[i].sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in trinity_apply_state_adjust_rules()
1530 ps->levels[i].sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in trinity_apply_state_adjust_rules()
1532 trinity_get_vce_clock_voltage(rdev, new_rps->evclk, new_rps->ecclk, &min_vce_voltage); in trinity_apply_state_adjust_rules()
1533 if (ps->levels[i].vddc_index < min_vce_voltage) in trinity_apply_state_adjust_rules()
1534 ps->levels[i].vddc_index = min_vce_voltage; in trinity_apply_state_adjust_rules()
1537 ps->levels[i].ds_divider_index = in trinity_apply_state_adjust_rules()
1538 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr); in trinity_apply_state_adjust_rules()
1540 ps->levels[i].ss_divider_index = ps->levels[i].ds_divider_index; in trinity_apply_state_adjust_rules()
1542 ps->levels[i].allow_gnb_slow = 1; in trinity_apply_state_adjust_rules()
1543 ps->levels[i].force_nbp_state = 0; in trinity_apply_state_adjust_rules()
1544 ps->levels[i].display_wm = in trinity_apply_state_adjust_rules()
1546 ps->levels[i].vce_wm = in trinity_apply_state_adjust_rules()
1547 trinity_calculate_vce_wm(rdev, ps->levels[0].sclk); in trinity_apply_state_adjust_rules()
1550 if ((new_rps->class & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) || in trinity_apply_state_adjust_rules()
1551 ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)) in trinity_apply_state_adjust_rules()
1552 ps->bapm_flags |= TRINITY_POWERSTATE_FLAGS_BAPM_DISABLE; in trinity_apply_state_adjust_rules()
1554 if (pi->sys_info.nb_dpm_enable) { in trinity_apply_state_adjust_rules()
1555 ps->Dpm0PgNbPsLo = 0x1; in trinity_apply_state_adjust_rules()
1556 ps->Dpm0PgNbPsHi = 0x0; in trinity_apply_state_adjust_rules()
1557 ps->DpmXNbPsLo = 0x2; in trinity_apply_state_adjust_rules()
1558 ps->DpmXNbPsHi = 0x1; in trinity_apply_state_adjust_rules()
1560 if ((new_rps->class & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) || in trinity_apply_state_adjust_rules()
1561 … ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)) { in trinity_apply_state_adjust_rules()
1562 force_high = ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) || in trinity_apply_state_adjust_rules()
1563 ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) && in trinity_apply_state_adjust_rules()
1564 (pi->sys_info.uma_channel_number == 1))); in trinity_apply_state_adjust_rules()
1566 ps->Dpm0PgNbPsLo = force_high ? 0x2 : 0x3; in trinity_apply_state_adjust_rules()
1567 ps->Dpm0PgNbPsHi = 0x1; in trinity_apply_state_adjust_rules()
1568 ps->DpmXNbPsLo = force_high ? 0x2 : 0x3; in trinity_apply_state_adjust_rules()
1569 ps->DpmXNbPsHi = 0x2; in trinity_apply_state_adjust_rules()
1570 ps->levels[ps->num_levels - 1].allow_gnb_slow = 0; in trinity_apply_state_adjust_rules()
1585 if (pi->voltage_drop_in_dce)
1593 u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count; in trinity_add_dccac_value()
1594 u64 disp_clk = rdev->clock.default_dispclk / 100; in trinity_add_dccac_value()
1601 (32 - gpu_cac_avrg_cntl_window_size)); in trinity_add_dccac_value()
1610 if (pi->voltage_drop_in_dce) in trinity_dpm_display_configuration_changed()
1643 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); in trinity_parse_pplib_non_clock_info()
1644 rps->class = le16_to_cpu(non_clock_info->usClassification); in trinity_parse_pplib_non_clock_info()
1645 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in trinity_parse_pplib_non_clock_info()
1648 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in trinity_parse_pplib_non_clock_info()
1649 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in trinity_parse_pplib_non_clock_info()
1651 rps->vclk = 0; in trinity_parse_pplib_non_clock_info()
1652 rps->dclk = 0; in trinity_parse_pplib_non_clock_info()
1655 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { in trinity_parse_pplib_non_clock_info()
1656 rdev->pm.dpm.boot_ps = rps; in trinity_parse_pplib_non_clock_info()
1659 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) in trinity_parse_pplib_non_clock_info()
1660 rdev->pm.dpm.uvd_ps = rps; in trinity_parse_pplib_non_clock_info()
1669 struct trinity_pl *pl = &ps->levels[index]; in trinity_parse_pplib_clock_info()
1672 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); in trinity_parse_pplib_clock_info()
1673 sclk |= clock_info->sumo.ucEngineClockHigh << 16; in trinity_parse_pplib_clock_info()
1674 pl->sclk = sclk; in trinity_parse_pplib_clock_info()
1675 pl->vddc_index = clock_info->sumo.vddcIndex; in trinity_parse_pplib_clock_info()
1677 ps->num_levels = index + 1; in trinity_parse_pplib_clock_info()
1679 if (pi->enable_sclk_ds) { in trinity_parse_pplib_clock_info()
1680 pl->ds_divider_index = 5; in trinity_parse_pplib_clock_info()
1681 pl->ss_divider_index = 5; in trinity_parse_pplib_clock_info()
1687 struct radeon_mode_info *mode_info = &rdev->mode_info; in trinity_parse_power_table()
1702 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, in trinity_parse_power_table()
1704 return -EINVAL; in trinity_parse_power_table()
1705 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); in trinity_parse_power_table()
1708 (mode_info->atom_context->bios + data_offset + in trinity_parse_power_table()
1709 le16_to_cpu(power_info->pplib.usStateArrayOffset)); in trinity_parse_power_table()
1711 (mode_info->atom_context->bios + data_offset + in trinity_parse_power_table()
1712 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); in trinity_parse_power_table()
1714 (mode_info->atom_context->bios + data_offset + in trinity_parse_power_table()
1715 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); in trinity_parse_power_table()
1717 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in trinity_parse_power_table()
1720 if (!rdev->pm.dpm.ps) in trinity_parse_power_table()
1721 return -ENOMEM; in trinity_parse_power_table()
1722 power_state_offset = (u8 *)state_array->states; in trinity_parse_power_table()
1723 for (i = 0; i < state_array->ucNumEntries; i++) { in trinity_parse_power_table()
1726 non_clock_array_index = power_state->v2.nonClockInfoIndex; in trinity_parse_power_table()
1728 &non_clock_info_array->nonClockInfo[non_clock_array_index]; in trinity_parse_power_table()
1729 if (!rdev->pm.power_state[i].clock_info) in trinity_parse_power_table()
1730 return -EINVAL; in trinity_parse_power_table()
1733 kfree(rdev->pm.dpm.ps); in trinity_parse_power_table()
1734 return -ENOMEM; in trinity_parse_power_table()
1736 rdev->pm.dpm.ps[i].ps_priv = ps; in trinity_parse_power_table()
1738 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; in trinity_parse_power_table()
1739 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in trinity_parse_power_table()
1741 if (clock_array_index >= clock_info_array->ucNumEntries) in trinity_parse_power_table()
1746 ((u8 *)&clock_info_array->clockInfo[0] + in trinity_parse_power_table()
1747 (clock_array_index * clock_info_array->ucEntrySize)); in trinity_parse_power_table()
1749 &rdev->pm.dpm.ps[i], k, in trinity_parse_power_table()
1753 trinity_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in trinity_parse_power_table()
1755 non_clock_info_array->ucEntrySize); in trinity_parse_power_table()
1756 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in trinity_parse_power_table()
1758 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in trinity_parse_power_table()
1763 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; in trinity_parse_power_table()
1765 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; in trinity_parse_power_table()
1766 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); in trinity_parse_power_table()
1767 sclk |= clock_info->sumo.ucEngineClockHigh << 16; in trinity_parse_power_table()
1768 rdev->pm.dpm.vce_states[i].sclk = sclk; in trinity_parse_power_table()
1769 rdev->pm.dpm.vce_states[i].mclk = 0; in trinity_parse_power_table()
1791 divider = (did - 64) * 50 + 1600; in trinity_convert_did_to_freq()
1793 divider = (did - 96) * 100 + 3200; in trinity_convert_did_to_freq()
1799 return ((pi->sys_info.dentist_vco_freq * 100) + (divider - 1)) / divider; in trinity_convert_did_to_freq()
1805 struct radeon_mode_info *mode_info = &rdev->mode_info; in trinity_parse_sys_info_table()
1812 if (atom_parse_data_header(mode_info->atom_context, index, NULL, in trinity_parse_sys_info_table()
1814 igp_info = (union igp_info *)(mode_info->atom_context->bios + in trinity_parse_sys_info_table()
1819 return -EINVAL; in trinity_parse_sys_info_table()
1821 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_7.ulBootUpEngineClock); in trinity_parse_sys_info_table()
1822 pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_7.ulMinEngineClock); in trinity_parse_sys_info_table()
1823 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_7.ulBootUpUMAClock); in trinity_parse_sys_info_table()
1824 pi->sys_info.dentist_vco_freq = le32_to_cpu(igp_info->info_7.ulDentistVCOFreq); in trinity_parse_sys_info_table()
1825 pi->sys_info.bootup_nb_voltage_index = in trinity_parse_sys_info_table()
1826 le16_to_cpu(igp_info->info_7.usBootUpNBVoltage); in trinity_parse_sys_info_table()
1827 if (igp_info->info_7.ucHtcTmpLmt == 0) in trinity_parse_sys_info_table()
1828 pi->sys_info.htc_tmp_lmt = 203; in trinity_parse_sys_info_table()
1830 pi->sys_info.htc_tmp_lmt = igp_info->info_7.ucHtcTmpLmt; in trinity_parse_sys_info_table()
1831 if (igp_info->info_7.ucHtcHystLmt == 0) in trinity_parse_sys_info_table()
1832 pi->sys_info.htc_hyst_lmt = 5; in trinity_parse_sys_info_table()
1834 pi->sys_info.htc_hyst_lmt = igp_info->info_7.ucHtcHystLmt; in trinity_parse_sys_info_table()
1835 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { in trinity_parse_sys_info_table()
1839 if (pi->enable_nbps_policy) in trinity_parse_sys_info_table()
1840 pi->sys_info.nb_dpm_enable = igp_info->info_7.ucNBDPMEnable; in trinity_parse_sys_info_table()
1842 pi->sys_info.nb_dpm_enable = 0; in trinity_parse_sys_info_table()
1845 pi->sys_info.nbp_mclk[i] = le32_to_cpu(igp_info->info_7.ulNbpStateMemclkFreq[i]); in trinity_parse_sys_info_table()
1846 pi->sys_info.nbp_nclk[i] = le32_to_cpu(igp_info->info_7.ulNbpStateNClkFreq[i]); in trinity_parse_sys_info_table()
1849 pi->sys_info.nbp_voltage_index[0] = le16_to_cpu(igp_info->info_7.usNBP0Voltage); in trinity_parse_sys_info_table()
1850 pi->sys_info.nbp_voltage_index[1] = le16_to_cpu(igp_info->info_7.usNBP1Voltage); in trinity_parse_sys_info_table()
1851 pi->sys_info.nbp_voltage_index[2] = le16_to_cpu(igp_info->info_7.usNBP2Voltage); in trinity_parse_sys_info_table()
1852 pi->sys_info.nbp_voltage_index[3] = le16_to_cpu(igp_info->info_7.usNBP3Voltage); in trinity_parse_sys_info_table()
1854 if (!pi->sys_info.nb_dpm_enable) { in trinity_parse_sys_info_table()
1856 pi->sys_info.nbp_mclk[i] = pi->sys_info.nbp_mclk[0]; in trinity_parse_sys_info_table()
1857 pi->sys_info.nbp_nclk[i] = pi->sys_info.nbp_nclk[0]; in trinity_parse_sys_info_table()
1858 pi->sys_info.nbp_voltage_index[i] = pi->sys_info.nbp_voltage_index[0]; in trinity_parse_sys_info_table()
1862 pi->sys_info.uma_channel_number = igp_info->info_7.ucUMAChannelNumber; in trinity_parse_sys_info_table()
1865 &pi->sys_info.sclk_voltage_mapping_table, in trinity_parse_sys_info_table()
1866 igp_info->info_7.sAvail_SCLK); in trinity_parse_sys_info_table()
1867 sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table, in trinity_parse_sys_info_table()
1868 igp_info->info_7.sAvail_SCLK); in trinity_parse_sys_info_table()
1870 pi->sys_info.uvd_clock_table_entries[0].vclk_did = in trinity_parse_sys_info_table()
1871 igp_info->info_7.ucDPMState0VclkFid; in trinity_parse_sys_info_table()
1872 pi->sys_info.uvd_clock_table_entries[1].vclk_did = in trinity_parse_sys_info_table()
1873 igp_info->info_7.ucDPMState1VclkFid; in trinity_parse_sys_info_table()
1874 pi->sys_info.uvd_clock_table_entries[2].vclk_did = in trinity_parse_sys_info_table()
1875 igp_info->info_7.ucDPMState2VclkFid; in trinity_parse_sys_info_table()
1876 pi->sys_info.uvd_clock_table_entries[3].vclk_did = in trinity_parse_sys_info_table()
1877 igp_info->info_7.ucDPMState3VclkFid; in trinity_parse_sys_info_table()
1879 pi->sys_info.uvd_clock_table_entries[0].dclk_did = in trinity_parse_sys_info_table()
1880 igp_info->info_7.ucDPMState0DclkFid; in trinity_parse_sys_info_table()
1881 pi->sys_info.uvd_clock_table_entries[1].dclk_did = in trinity_parse_sys_info_table()
1882 igp_info->info_7.ucDPMState1DclkFid; in trinity_parse_sys_info_table()
1883 pi->sys_info.uvd_clock_table_entries[2].dclk_did = in trinity_parse_sys_info_table()
1884 igp_info->info_7.ucDPMState2DclkFid; in trinity_parse_sys_info_table()
1885 pi->sys_info.uvd_clock_table_entries[3].dclk_did = in trinity_parse_sys_info_table()
1886 igp_info->info_7.ucDPMState3DclkFid; in trinity_parse_sys_info_table()
1889 pi->sys_info.uvd_clock_table_entries[i].vclk = in trinity_parse_sys_info_table()
1891 pi->sys_info.uvd_clock_table_entries[i].vclk_did); in trinity_parse_sys_info_table()
1892 pi->sys_info.uvd_clock_table_entries[i].dclk = in trinity_parse_sys_info_table()
1894 pi->sys_info.uvd_clock_table_entries[i].dclk_did); in trinity_parse_sys_info_table()
1910 return -ENOMEM; in trinity_dpm_init()
1911 rdev->pm.dpm.priv = pi; in trinity_dpm_init()
1914 pi->at[i] = TRINITY_AT_DFLT; in trinity_dpm_init()
1916 if (radeon_bapm == -1) { in trinity_dpm_init()
1918 * bapm enabled when switching between AC and battery in trinity_dpm_init()
1923 if (rdev->pdev->subsystem_vendor == 0x1462) in trinity_dpm_init()
1924 pi->enable_bapm = true; in trinity_dpm_init()
1926 pi->enable_bapm = false; in trinity_dpm_init()
1928 pi->enable_bapm = false; in trinity_dpm_init()
1930 pi->enable_bapm = true; in trinity_dpm_init()
1932 pi->enable_nbps_policy = true; in trinity_dpm_init()
1933 pi->enable_sclk_ds = true; in trinity_dpm_init()
1934 pi->enable_gfx_power_gating = true; in trinity_dpm_init()
1935 pi->enable_gfx_clock_gating = true; in trinity_dpm_init()
1936 pi->enable_mg_clock_gating = false; in trinity_dpm_init()
1937 pi->enable_gfx_dynamic_mgpg = false; in trinity_dpm_init()
1938 pi->override_dynamic_mgpg = false; in trinity_dpm_init()
1939 pi->enable_auto_thermal_throttling = true; in trinity_dpm_init()
1940 pi->voltage_drop_in_dce = false; /* need to restructure dpm/modeset interaction */ in trinity_dpm_init()
1941 pi->uvd_dpm = true; /* ??? */ in trinity_dpm_init()
1961 pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt; in trinity_dpm_init()
1962 pi->enable_dpm = true; in trinity_dpm_init()
1973 r600_dpm_print_class_info(rps->class, rps->class2); in trinity_dpm_print_power_state()
1974 r600_dpm_print_cap_info(rps->caps); in trinity_dpm_print_power_state()
1975 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
1976 for (i = 0; i < ps->num_levels; i++) { in trinity_dpm_print_power_state()
1977 struct trinity_pl *pl = &ps->levels[i]; in trinity_dpm_print_power_state()
1979 i, pl->sclk, in trinity_dpm_print_power_state()
1980 trinity_convert_voltage_index_to_value(rdev, pl->vddc_index)); in trinity_dpm_print_power_state()
1989 struct radeon_ps *rps = &pi->current_rps; in trinity_dpm_debugfs_print_current_performance_level()
1996 if (current_index >= ps->num_levels) { in trinity_dpm_debugfs_print_current_performance_level()
1997 seq_printf(m, "invalid dpm profile %d\n", current_index); in trinity_dpm_debugfs_print_current_performance_level()
1999 pl = &ps->levels[current_index]; in trinity_dpm_debugfs_print_current_performance_level()
2000 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
2002 current_index, pl->sclk, in trinity_dpm_debugfs_print_current_performance_level()
2003 trinity_convert_voltage_index_to_value(rdev, pl->vddc_index)); in trinity_dpm_debugfs_print_current_performance_level()
2010 struct radeon_ps *rps = &pi->current_rps; in trinity_dpm_get_current_sclk()
2017 if (current_index >= ps->num_levels) { in trinity_dpm_get_current_sclk()
2020 pl = &ps->levels[current_index]; in trinity_dpm_get_current_sclk()
2021 return pl->sclk; in trinity_dpm_get_current_sclk()
2029 return pi->sys_info.bootup_uma_clk; in trinity_dpm_get_current_mclk()
2038 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in trinity_dpm_fini()
2039 kfree(rdev->pm.dpm.ps[i].ps_priv); in trinity_dpm_fini()
2041 kfree(rdev->pm.dpm.ps); in trinity_dpm_fini()
2042 kfree(rdev->pm.dpm.priv); in trinity_dpm_fini()
2049 struct trinity_ps *requested_state = trinity_get_ps(&pi->requested_rps); in trinity_dpm_get_sclk()
2052 return requested_state->levels[0].sclk; in trinity_dpm_get_sclk()
2054 return requested_state->levels[requested_state->num_levels - 1].sclk; in trinity_dpm_get_sclk()
2061 return pi->sys_info.bootup_uma_clk; in trinity_dpm_get_mclk()