Lines Matching +full:battery +full:- +full:profile
24 #include <linux/hwmon-sysfs.h>
44 "Battery",
61 int found_instance = -1; in radeon_pm_get_type_index()
63 for (i = 0; i < rdev->pm.num_power_states; i++) { in radeon_pm_get_type_index()
64 if (rdev->pm.power_state[i].type == ps_type) { in radeon_pm_get_type_index()
71 return rdev->pm.default_power_state_index; in radeon_pm_get_type_index()
76 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in radeon_pm_acpi_event_handler()
77 mutex_lock(&rdev->pm.mutex); in radeon_pm_acpi_event_handler()
79 rdev->pm.dpm.ac_power = true; in radeon_pm_acpi_event_handler()
81 rdev->pm.dpm.ac_power = false; in radeon_pm_acpi_event_handler()
82 if (rdev->family == CHIP_ARUBA) { in radeon_pm_acpi_event_handler()
83 if (rdev->asic->dpm.enable_bapm) in radeon_pm_acpi_event_handler()
84 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); in radeon_pm_acpi_event_handler()
86 mutex_unlock(&rdev->pm.mutex); in radeon_pm_acpi_event_handler()
87 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { in radeon_pm_acpi_event_handler()
88 if (rdev->pm.profile == PM_PROFILE_AUTO) { in radeon_pm_acpi_event_handler()
89 mutex_lock(&rdev->pm.mutex); in radeon_pm_acpi_event_handler()
92 mutex_unlock(&rdev->pm.mutex); in radeon_pm_acpi_event_handler()
99 switch (rdev->pm.profile) { in radeon_pm_update_profile()
101 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; in radeon_pm_update_profile()
105 if (rdev->pm.active_crtc_count > 1) in radeon_pm_update_profile()
106 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; in radeon_pm_update_profile()
108 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; in radeon_pm_update_profile()
110 if (rdev->pm.active_crtc_count > 1) in radeon_pm_update_profile()
111 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; in radeon_pm_update_profile()
113 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; in radeon_pm_update_profile()
117 if (rdev->pm.active_crtc_count > 1) in radeon_pm_update_profile()
118 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; in radeon_pm_update_profile()
120 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; in radeon_pm_update_profile()
123 if (rdev->pm.active_crtc_count > 1) in radeon_pm_update_profile()
124 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; in radeon_pm_update_profile()
126 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; in radeon_pm_update_profile()
129 if (rdev->pm.active_crtc_count > 1) in radeon_pm_update_profile()
130 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; in radeon_pm_update_profile()
132 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; in radeon_pm_update_profile()
136 if (rdev->pm.active_crtc_count == 0) { in radeon_pm_update_profile()
137 rdev->pm.requested_power_state_index = in radeon_pm_update_profile()
138 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; in radeon_pm_update_profile()
139 rdev->pm.requested_clock_mode_index = in radeon_pm_update_profile()
140 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; in radeon_pm_update_profile()
142 rdev->pm.requested_power_state_index = in radeon_pm_update_profile()
143 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; in radeon_pm_update_profile()
144 rdev->pm.requested_clock_mode_index = in radeon_pm_update_profile()
145 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; in radeon_pm_update_profile()
153 if (list_empty(&rdev->gem.objects)) in radeon_unmap_vram_bos()
156 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { in radeon_unmap_vram_bos()
157 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) in radeon_unmap_vram_bos()
158 ttm_bo_unmap_virtual(&bo->tbo); in radeon_unmap_vram_bos()
164 if (rdev->pm.active_crtcs) { in radeon_sync_with_vblank()
165 rdev->pm.vblank_sync = false; in radeon_sync_with_vblank()
167 rdev->irq.vblank_queue, rdev->pm.vblank_sync, in radeon_sync_with_vblank()
177 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && in radeon_set_power_state()
178 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) in radeon_set_power_state()
182 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. in radeon_set_power_state()
183 clock_info[rdev->pm.requested_clock_mode_index].sclk; in radeon_set_power_state()
184 if (sclk > rdev->pm.default_sclk) in radeon_set_power_state()
185 sclk = rdev->pm.default_sclk; in radeon_set_power_state()
191 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && in radeon_set_power_state()
192 (rdev->family >= CHIP_BARTS) && in radeon_set_power_state()
193 rdev->pm.active_crtc_count && in radeon_set_power_state()
194 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || in radeon_set_power_state()
195 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) in radeon_set_power_state()
196 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. in radeon_set_power_state()
197 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; in radeon_set_power_state()
199 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. in radeon_set_power_state()
200 clock_info[rdev->pm.requested_clock_mode_index].mclk; in radeon_set_power_state()
202 if (mclk > rdev->pm.default_mclk) in radeon_set_power_state()
203 mclk = rdev->pm.default_mclk; in radeon_set_power_state()
206 if (sclk < rdev->pm.current_sclk) in radeon_set_power_state()
211 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { in radeon_set_power_state()
223 if (sclk != rdev->pm.current_sclk) { in radeon_set_power_state()
227 rdev->pm.current_sclk = sclk; in radeon_set_power_state()
232 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { in radeon_set_power_state()
236 rdev->pm.current_mclk = mclk; in radeon_set_power_state()
246 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; in radeon_set_power_state()
247 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; in radeon_set_power_state()
258 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && in radeon_pm_set_clocks()
259 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) in radeon_pm_set_clocks()
262 down_write(&rdev->pm.mclk_lock); in radeon_pm_set_clocks()
263 mutex_lock(&rdev->ring_lock); in radeon_pm_set_clocks()
267 struct radeon_ring *ring = &rdev->ring[i]; in radeon_pm_set_clocks()
268 if (!ring->ready) { in radeon_pm_set_clocks()
274 mutex_unlock(&rdev->ring_lock); in radeon_pm_set_clocks()
275 up_write(&rdev->pm.mclk_lock); in radeon_pm_set_clocks()
282 if (rdev->irq.installed) { in radeon_pm_set_clocks()
284 drm_for_each_crtc(crtc, rdev->ddev) { in radeon_pm_set_clocks()
285 if (rdev->pm.active_crtcs & (1 << i)) { in radeon_pm_set_clocks()
288 rdev->pm.req_vblank |= (1 << i); in radeon_pm_set_clocks()
299 if (rdev->irq.installed) { in radeon_pm_set_clocks()
301 drm_for_each_crtc(crtc, rdev->ddev) { in radeon_pm_set_clocks()
302 if (rdev->pm.req_vblank & (1 << i)) { in radeon_pm_set_clocks()
303 rdev->pm.req_vblank &= ~(1 << i); in radeon_pm_set_clocks()
312 if (rdev->pm.active_crtc_count) in radeon_pm_set_clocks()
315 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; in radeon_pm_set_clocks()
317 mutex_unlock(&rdev->ring_lock); in radeon_pm_set_clocks()
318 up_write(&rdev->pm.mclk_lock); in radeon_pm_set_clocks()
327 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); in radeon_pm_print_states()
328 for (i = 0; i < rdev->pm.num_power_states; i++) { in radeon_pm_print_states()
329 power_state = &rdev->pm.power_state[i]; in radeon_pm_print_states()
331 radeon_pm_state_type_name[power_state->type]); in radeon_pm_print_states()
332 if (i == rdev->pm.default_power_state_index) in radeon_pm_print_states()
334 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) in radeon_pm_print_states()
335 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); in radeon_pm_print_states()
336 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in radeon_pm_print_states()
338 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); in radeon_pm_print_states()
339 for (j = 0; j < power_state->num_clock_modes; j++) { in radeon_pm_print_states()
340 clock_info = &(power_state->clock_info[j]); in radeon_pm_print_states()
341 if (rdev->flags & RADEON_IS_IGP) in radeon_pm_print_states()
344 clock_info->sclk * 10); in radeon_pm_print_states()
348 clock_info->sclk * 10, in radeon_pm_print_states()
349 clock_info->mclk * 10, in radeon_pm_print_states()
350 clock_info->voltage.voltage); in radeon_pm_print_states()
360 struct radeon_device *rdev = ddev->dev_private; in radeon_get_pm_profile()
361 int cp = rdev->pm.profile; in radeon_get_pm_profile()
375 struct radeon_device *rdev = ddev->dev_private; in radeon_set_pm_profile()
377 /* Can't set profile when the card is off */ in radeon_set_pm_profile()
378 if ((rdev->flags & RADEON_IS_PX) && in radeon_set_pm_profile()
379 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) in radeon_set_pm_profile()
380 return -EINVAL; in radeon_set_pm_profile()
382 mutex_lock(&rdev->pm.mutex); in radeon_set_pm_profile()
383 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { in radeon_set_pm_profile()
385 rdev->pm.profile = PM_PROFILE_DEFAULT; in radeon_set_pm_profile()
387 rdev->pm.profile = PM_PROFILE_AUTO; in radeon_set_pm_profile()
389 rdev->pm.profile = PM_PROFILE_LOW; in radeon_set_pm_profile()
391 rdev->pm.profile = PM_PROFILE_MID; in radeon_set_pm_profile()
393 rdev->pm.profile = PM_PROFILE_HIGH; in radeon_set_pm_profile()
395 count = -EINVAL; in radeon_set_pm_profile()
401 count = -EINVAL; in radeon_set_pm_profile()
404 mutex_unlock(&rdev->pm.mutex); in radeon_set_pm_profile()
414 struct radeon_device *rdev = ddev->dev_private; in radeon_get_pm_method()
415 int pm = rdev->pm.pm_method; in radeon_get_pm_method()
418 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); in radeon_get_pm_method()
427 struct radeon_device *rdev = ddev->dev_private; in radeon_set_pm_method()
430 if ((rdev->flags & RADEON_IS_PX) && in radeon_set_pm_method()
431 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { in radeon_set_pm_method()
432 count = -EINVAL; in radeon_set_pm_method()
437 if (rdev->pm.pm_method == PM_METHOD_DPM) { in radeon_set_pm_method()
438 count = -EINVAL; in radeon_set_pm_method()
443 mutex_lock(&rdev->pm.mutex); in radeon_set_pm_method()
444 rdev->pm.pm_method = PM_METHOD_DYNPM; in radeon_set_pm_method()
445 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; in radeon_set_pm_method()
446 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; in radeon_set_pm_method()
447 mutex_unlock(&rdev->pm.mutex); in radeon_set_pm_method()
448 } else if (strncmp("profile", buf, strlen("profile")) == 0) { in radeon_set_pm_method()
449 mutex_lock(&rdev->pm.mutex); in radeon_set_pm_method()
451 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; in radeon_set_pm_method()
452 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; in radeon_set_pm_method()
453 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_set_pm_method()
454 mutex_unlock(&rdev->pm.mutex); in radeon_set_pm_method()
455 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); in radeon_set_pm_method()
457 count = -EINVAL; in radeon_set_pm_method()
470 struct radeon_device *rdev = ddev->dev_private; in radeon_get_dpm_state()
471 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; in radeon_get_dpm_state()
474 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : in radeon_get_dpm_state()
484 struct radeon_device *rdev = ddev->dev_private; in radeon_set_dpm_state()
486 mutex_lock(&rdev->pm.mutex); in radeon_set_dpm_state()
487 if (strncmp("battery", buf, strlen("battery")) == 0) in radeon_set_dpm_state()
488 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; in radeon_set_dpm_state()
490 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in radeon_set_dpm_state()
492 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; in radeon_set_dpm_state()
494 mutex_unlock(&rdev->pm.mutex); in radeon_set_dpm_state()
495 count = -EINVAL; in radeon_set_dpm_state()
498 mutex_unlock(&rdev->pm.mutex); in radeon_set_dpm_state()
501 if (!(rdev->flags & RADEON_IS_PX) || in radeon_set_dpm_state()
502 (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) in radeon_set_dpm_state()
514 struct radeon_device *rdev = ddev->dev_private; in radeon_get_dpm_forced_performance_level()
515 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; in radeon_get_dpm_forced_performance_level()
517 if ((rdev->flags & RADEON_IS_PX) && in radeon_get_dpm_forced_performance_level()
518 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) in radeon_get_dpm_forced_performance_level()
532 struct radeon_device *rdev = ddev->dev_private; in radeon_set_dpm_forced_performance_level()
537 if ((rdev->flags & RADEON_IS_PX) && in radeon_set_dpm_forced_performance_level()
538 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) in radeon_set_dpm_forced_performance_level()
539 return -EINVAL; in radeon_set_dpm_forced_performance_level()
541 mutex_lock(&rdev->pm.mutex); in radeon_set_dpm_forced_performance_level()
549 count = -EINVAL; in radeon_set_dpm_forced_performance_level()
552 if (rdev->asic->dpm.force_performance_level) { in radeon_set_dpm_forced_performance_level()
553 if (rdev->pm.dpm.thermal_active) { in radeon_set_dpm_forced_performance_level()
554 count = -EINVAL; in radeon_set_dpm_forced_performance_level()
559 count = -EINVAL; in radeon_set_dpm_forced_performance_level()
562 mutex_unlock(&rdev->pm.mutex); in radeon_set_dpm_forced_performance_level()
574 if (rdev->asic->dpm.fan_ctrl_get_mode) in radeon_hwmon_get_pwm1_enable()
575 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev); in radeon_hwmon_get_pwm1_enable()
577 /* never 0 (full-speed), fuse or smc-controlled always */ in radeon_hwmon_get_pwm1_enable()
590 if(!rdev->asic->dpm.fan_ctrl_set_mode) in radeon_hwmon_set_pwm1_enable()
591 return -EINVAL; in radeon_hwmon_set_pwm1_enable()
598 case 1: /* manual, percent-based */ in radeon_hwmon_set_pwm1_enable()
599 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC); in radeon_hwmon_set_pwm1_enable()
602 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0); in radeon_hwmon_set_pwm1_enable()
637 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value); in radeon_hwmon_set_pwm1()
652 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed); in radeon_hwmon_get_pwm1()
673 struct drm_device *ddev = rdev->ddev; in radeon_hwmon_show_temp()
677 if ((rdev->flags & RADEON_IS_PX) && in radeon_hwmon_show_temp()
678 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) in radeon_hwmon_show_temp()
679 return -EINVAL; in radeon_hwmon_show_temp()
681 if (rdev->asic->pm.get_temperature) in radeon_hwmon_show_temp()
694 int hyst = to_sensor_dev_attr(attr)->index; in radeon_hwmon_show_temp_thresh()
698 temp = rdev->pm.dpm.thermal.min_temp; in radeon_hwmon_show_temp_thresh()
700 temp = rdev->pm.dpm.thermal.max_temp; in radeon_hwmon_show_temp_thresh()
717 struct drm_device *ddev = rdev->ddev; in radeon_hwmon_show_sclk()
721 if ((rdev->flags & RADEON_IS_PX) && in radeon_hwmon_show_sclk()
722 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) in radeon_hwmon_show_sclk()
723 return -EINVAL; in radeon_hwmon_show_sclk()
725 if (rdev->asic->dpm.get_current_sclk) in radeon_hwmon_show_sclk()
742 struct drm_device *ddev = rdev->ddev; in radeon_hwmon_show_vddc()
746 if ((rdev->flags & RADEON_IS_PX) && in radeon_hwmon_show_vddc()
747 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) in radeon_hwmon_show_vddc()
748 return -EINVAL; in radeon_hwmon_show_vddc()
750 if (rdev->asic->dpm.get_current_vddc) in radeon_hwmon_show_vddc()
751 vddc = rdev->asic->dpm.get_current_vddc(rdev); in radeon_hwmon_show_vddc()
777 umode_t effective_mode = attr->mode; in hwmon_attributes_visible()
780 if (rdev->pm.pm_method != PM_METHOD_DPM && in hwmon_attributes_visible()
793 !rdev->asic->dpm.get_current_vddc) in hwmon_attributes_visible()
797 if (rdev->pm.no_fan && in hwmon_attributes_visible()
805 if ((!rdev->asic->dpm.get_fan_speed_percent && in hwmon_attributes_visible()
807 (!rdev->asic->dpm.fan_ctrl_get_mode && in hwmon_attributes_visible()
811 if ((!rdev->asic->dpm.set_fan_speed_percent && in hwmon_attributes_visible()
813 (!rdev->asic->dpm.fan_ctrl_set_mode && in hwmon_attributes_visible()
818 if ((!rdev->asic->dpm.set_fan_speed_percent && in hwmon_attributes_visible()
819 !rdev->asic->dpm.get_fan_speed_percent) && in hwmon_attributes_visible()
841 switch (rdev->pm.int_thermal_type) { in radeon_hwmon_init()
850 if (rdev->asic->pm.get_temperature == NULL) in radeon_hwmon_init()
852 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev, in radeon_hwmon_init()
855 if (IS_ERR(rdev->pm.int_hwmon_dev)) { in radeon_hwmon_init()
856 err = PTR_ERR(rdev->pm.int_hwmon_dev); in radeon_hwmon_init()
857 dev_err(rdev->dev, in radeon_hwmon_init()
870 if (rdev->pm.int_hwmon_dev) in radeon_hwmon_fini()
871 hwmon_device_unregister(rdev->pm.int_hwmon_dev); in radeon_hwmon_fini()
882 if (!rdev->pm.dpm_enabled) in radeon_dpm_thermal_work_handler()
885 if (rdev->asic->pm.get_temperature) { in radeon_dpm_thermal_work_handler()
888 if (temp < rdev->pm.dpm.thermal.min_temp) in radeon_dpm_thermal_work_handler()
890 dpm_state = rdev->pm.dpm.user_state; in radeon_dpm_thermal_work_handler()
892 if (rdev->pm.dpm.thermal.high_to_low) in radeon_dpm_thermal_work_handler()
894 dpm_state = rdev->pm.dpm.user_state; in radeon_dpm_thermal_work_handler()
896 mutex_lock(&rdev->pm.mutex); in radeon_dpm_thermal_work_handler()
898 rdev->pm.dpm.thermal_active = true; in radeon_dpm_thermal_work_handler()
900 rdev->pm.dpm.thermal_active = false; in radeon_dpm_thermal_work_handler()
901 rdev->pm.dpm.state = dpm_state; in radeon_dpm_thermal_work_handler()
902 mutex_unlock(&rdev->pm.mutex); in radeon_dpm_thermal_work_handler()
909 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? in radeon_dpm_single_display()
913 if (single_display && rdev->asic->dpm.vblank_too_short) { in radeon_dpm_single_display()
946 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in radeon_dpm_pick_power_state()
947 ps = &rdev->pm.dpm.ps[i]; in radeon_dpm_pick_power_state()
948 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; in radeon_dpm_pick_power_state()
953 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { in radeon_dpm_pick_power_state()
962 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { in radeon_dpm_pick_power_state()
971 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { in radeon_dpm_pick_power_state()
980 if (rdev->pm.dpm.uvd_ps) in radeon_dpm_pick_power_state()
981 return rdev->pm.dpm.uvd_ps; in radeon_dpm_pick_power_state()
985 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) in radeon_dpm_pick_power_state()
989 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) in radeon_dpm_pick_power_state()
993 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) in radeon_dpm_pick_power_state()
997 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) in radeon_dpm_pick_power_state()
1001 return rdev->pm.dpm.boot_ps; in radeon_dpm_pick_power_state()
1003 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) in radeon_dpm_pick_power_state()
1007 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) in radeon_dpm_pick_power_state()
1011 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) in radeon_dpm_pick_power_state()
1015 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) in radeon_dpm_pick_power_state()
1030 if (rdev->pm.dpm.uvd_ps) { in radeon_dpm_pick_power_state()
1031 return rdev->pm.dpm.uvd_ps; in radeon_dpm_pick_power_state()
1063 if (!rdev->pm.dpm_enabled) in radeon_dpm_change_power_state_locked()
1066 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) { in radeon_dpm_change_power_state_locked()
1068 if ((!rdev->pm.dpm.thermal_active) && in radeon_dpm_change_power_state_locked()
1069 (!rdev->pm.dpm.uvd_active)) in radeon_dpm_change_power_state_locked()
1070 rdev->pm.dpm.state = rdev->pm.dpm.user_state; in radeon_dpm_change_power_state_locked()
1072 dpm_state = rdev->pm.dpm.state; in radeon_dpm_change_power_state_locked()
1076 rdev->pm.dpm.requested_ps = ps; in radeon_dpm_change_power_state_locked()
1081 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) { in radeon_dpm_change_power_state_locked()
1083 if (ps->vce_active != rdev->pm.dpm.vce_active) in radeon_dpm_change_power_state_locked()
1086 if (rdev->pm.dpm.single_display != single_display) in radeon_dpm_change_power_state_locked()
1088 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) { in radeon_dpm_change_power_state_locked()
1089 /* for pre-BTC and APUs if the num crtcs changed but state is the same, in radeon_dpm_change_power_state_locked()
1092 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) { in radeon_dpm_change_power_state_locked()
1097 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; in radeon_dpm_change_power_state_locked()
1098 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; in radeon_dpm_change_power_state_locked()
1106 if (rdev->pm.dpm.new_active_crtcs == in radeon_dpm_change_power_state_locked()
1107 rdev->pm.dpm.current_active_crtcs) { in radeon_dpm_change_power_state_locked()
1110 if ((rdev->pm.dpm.current_active_crtc_count > 1) && in radeon_dpm_change_power_state_locked()
1111 (rdev->pm.dpm.new_active_crtc_count > 1)) { in radeon_dpm_change_power_state_locked()
1116 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; in radeon_dpm_change_power_state_locked()
1117 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; in radeon_dpm_change_power_state_locked()
1127 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps); in radeon_dpm_change_power_state_locked()
1129 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps); in radeon_dpm_change_power_state_locked()
1132 down_write(&rdev->pm.mclk_lock); in radeon_dpm_change_power_state_locked()
1133 mutex_lock(&rdev->ring_lock); in radeon_dpm_change_power_state_locked()
1136 ps->vce_active = rdev->pm.dpm.vce_active; in radeon_dpm_change_power_state_locked()
1149 struct radeon_ring *ring = &rdev->ring[i]; in radeon_dpm_change_power_state_locked()
1150 if (ring->ready) in radeon_dpm_change_power_state_locked()
1158 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps; in radeon_dpm_change_power_state_locked()
1162 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; in radeon_dpm_change_power_state_locked()
1163 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; in radeon_dpm_change_power_state_locked()
1164 rdev->pm.dpm.single_display = single_display; in radeon_dpm_change_power_state_locked()
1166 if (rdev->asic->dpm.force_performance_level) { in radeon_dpm_change_power_state_locked()
1167 if (rdev->pm.dpm.thermal_active) { in radeon_dpm_change_power_state_locked()
1168 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; in radeon_dpm_change_power_state_locked()
1172 rdev->pm.dpm.forced_level = level; in radeon_dpm_change_power_state_locked()
1175 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level); in radeon_dpm_change_power_state_locked()
1180 mutex_unlock(&rdev->ring_lock); in radeon_dpm_change_power_state_locked()
1181 up_write(&rdev->pm.mclk_lock); in radeon_dpm_change_power_state_locked()
1188 if (rdev->asic->dpm.powergate_uvd) { in radeon_dpm_enable_uvd()
1189 mutex_lock(&rdev->pm.mutex); in radeon_dpm_enable_uvd()
1192 enable |= rdev->pm.dpm.sd > 0; in radeon_dpm_enable_uvd()
1193 enable |= rdev->pm.dpm.hd > 0; in radeon_dpm_enable_uvd()
1196 mutex_unlock(&rdev->pm.mutex); in radeon_dpm_enable_uvd()
1199 mutex_lock(&rdev->pm.mutex); in radeon_dpm_enable_uvd()
1200 rdev->pm.dpm.uvd_active = true; in radeon_dpm_enable_uvd()
1203 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) in radeon_dpm_enable_uvd()
1205 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) in radeon_dpm_enable_uvd()
1207 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1)) in radeon_dpm_enable_uvd()
1209 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) in radeon_dpm_enable_uvd()
1214 rdev->pm.dpm.state = dpm_state; in radeon_dpm_enable_uvd()
1215 mutex_unlock(&rdev->pm.mutex); in radeon_dpm_enable_uvd()
1217 mutex_lock(&rdev->pm.mutex); in radeon_dpm_enable_uvd()
1218 rdev->pm.dpm.uvd_active = false; in radeon_dpm_enable_uvd()
1219 mutex_unlock(&rdev->pm.mutex); in radeon_dpm_enable_uvd()
1229 mutex_lock(&rdev->pm.mutex); in radeon_dpm_enable_vce()
1230 rdev->pm.dpm.vce_active = true; in radeon_dpm_enable_vce()
1232 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL; in radeon_dpm_enable_vce()
1233 mutex_unlock(&rdev->pm.mutex); in radeon_dpm_enable_vce()
1235 mutex_lock(&rdev->pm.mutex); in radeon_dpm_enable_vce()
1236 rdev->pm.dpm.vce_active = false; in radeon_dpm_enable_vce()
1237 mutex_unlock(&rdev->pm.mutex); in radeon_dpm_enable_vce()
1245 mutex_lock(&rdev->pm.mutex); in radeon_pm_suspend_old()
1246 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { in radeon_pm_suspend_old()
1247 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) in radeon_pm_suspend_old()
1248 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; in radeon_pm_suspend_old()
1250 mutex_unlock(&rdev->pm.mutex); in radeon_pm_suspend_old()
1252 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); in radeon_pm_suspend_old()
1257 mutex_lock(&rdev->pm.mutex); in radeon_pm_suspend_dpm()
1261 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; in radeon_pm_suspend_dpm()
1262 rdev->pm.dpm_enabled = false; in radeon_pm_suspend_dpm()
1263 mutex_unlock(&rdev->pm.mutex); in radeon_pm_suspend_dpm()
1268 if (rdev->pm.pm_method == PM_METHOD_DPM) in radeon_pm_suspend()
1277 if ((rdev->family >= CHIP_BARTS) && in radeon_pm_resume_old()
1278 (rdev->family <= CHIP_CAYMAN) && in radeon_pm_resume_old()
1279 rdev->mc_fw) { in radeon_pm_resume_old()
1280 if (rdev->pm.default_vddc) in radeon_pm_resume_old()
1281 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, in radeon_pm_resume_old()
1283 if (rdev->pm.default_vddci) in radeon_pm_resume_old()
1284 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, in radeon_pm_resume_old()
1286 if (rdev->pm.default_sclk) in radeon_pm_resume_old()
1287 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); in radeon_pm_resume_old()
1288 if (rdev->pm.default_mclk) in radeon_pm_resume_old()
1289 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); in radeon_pm_resume_old()
1292 mutex_lock(&rdev->pm.mutex); in radeon_pm_resume_old()
1293 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; in radeon_pm_resume_old()
1294 rdev->pm.current_clock_mode_index = 0; in radeon_pm_resume_old()
1295 rdev->pm.current_sclk = rdev->pm.default_sclk; in radeon_pm_resume_old()
1296 rdev->pm.current_mclk = rdev->pm.default_mclk; in radeon_pm_resume_old()
1297 if (rdev->pm.power_state) { in radeon_pm_resume_old()
1298 …rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].vol… in radeon_pm_resume_old()
1299 …rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].vo… in radeon_pm_resume_old()
1301 if (rdev->pm.pm_method == PM_METHOD_DYNPM in radeon_pm_resume_old()
1302 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { in radeon_pm_resume_old()
1303 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; in radeon_pm_resume_old()
1304 schedule_delayed_work(&rdev->pm.dynpm_idle_work, in radeon_pm_resume_old()
1307 mutex_unlock(&rdev->pm.mutex); in radeon_pm_resume_old()
1316 mutex_lock(&rdev->pm.mutex); in radeon_pm_resume_dpm()
1317 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; in radeon_pm_resume_dpm()
1320 mutex_unlock(&rdev->pm.mutex); in radeon_pm_resume_dpm()
1323 rdev->pm.dpm_enabled = true; in radeon_pm_resume_dpm()
1328 if ((rdev->family >= CHIP_BARTS) && in radeon_pm_resume_dpm()
1329 (rdev->family <= CHIP_CAYMAN) && in radeon_pm_resume_dpm()
1330 rdev->mc_fw) { in radeon_pm_resume_dpm()
1331 if (rdev->pm.default_vddc) in radeon_pm_resume_dpm()
1332 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, in radeon_pm_resume_dpm()
1334 if (rdev->pm.default_vddci) in radeon_pm_resume_dpm()
1335 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, in radeon_pm_resume_dpm()
1337 if (rdev->pm.default_sclk) in radeon_pm_resume_dpm()
1338 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); in radeon_pm_resume_dpm()
1339 if (rdev->pm.default_mclk) in radeon_pm_resume_dpm()
1340 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); in radeon_pm_resume_dpm()
1346 if (rdev->pm.pm_method == PM_METHOD_DPM) in radeon_pm_resume()
1356 rdev->pm.profile = PM_PROFILE_DEFAULT; in radeon_pm_init_old()
1357 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; in radeon_pm_init_old()
1358 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; in radeon_pm_init_old()
1359 rdev->pm.dynpm_can_upclock = true; in radeon_pm_init_old()
1360 rdev->pm.dynpm_can_downclock = true; in radeon_pm_init_old()
1361 rdev->pm.default_sclk = rdev->clock.default_sclk; in radeon_pm_init_old()
1362 rdev->pm.default_mclk = rdev->clock.default_mclk; in radeon_pm_init_old()
1363 rdev->pm.current_sclk = rdev->clock.default_sclk; in radeon_pm_init_old()
1364 rdev->pm.current_mclk = rdev->clock.default_mclk; in radeon_pm_init_old()
1365 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; in radeon_pm_init_old()
1367 if (rdev->bios) { in radeon_pm_init_old()
1368 if (rdev->is_atom_bios) in radeon_pm_init_old()
1375 if ((rdev->family >= CHIP_BARTS) && in radeon_pm_init_old()
1376 (rdev->family <= CHIP_CAYMAN) && in radeon_pm_init_old()
1377 rdev->mc_fw) { in radeon_pm_init_old()
1378 if (rdev->pm.default_vddc) in radeon_pm_init_old()
1379 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, in radeon_pm_init_old()
1381 if (rdev->pm.default_vddci) in radeon_pm_init_old()
1382 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, in radeon_pm_init_old()
1384 if (rdev->pm.default_sclk) in radeon_pm_init_old()
1385 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); in radeon_pm_init_old()
1386 if (rdev->pm.default_mclk) in radeon_pm_init_old()
1387 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); in radeon_pm_init_old()
1396 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); in radeon_pm_init_old()
1398 if (rdev->pm.num_power_states > 1) { in radeon_pm_init_old()
1410 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in radeon_dpm_print_power_states()
1412 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]); in radeon_dpm_print_power_states()
1421 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; in radeon_pm_init_dpm()
1422 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in radeon_pm_init_dpm()
1423 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; in radeon_pm_init_dpm()
1424 rdev->pm.default_sclk = rdev->clock.default_sclk; in radeon_pm_init_dpm()
1425 rdev->pm.default_mclk = rdev->clock.default_mclk; in radeon_pm_init_dpm()
1426 rdev->pm.current_sclk = rdev->clock.default_sclk; in radeon_pm_init_dpm()
1427 rdev->pm.current_mclk = rdev->clock.default_mclk; in radeon_pm_init_dpm()
1428 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; in radeon_pm_init_dpm()
1430 if (rdev->bios && rdev->is_atom_bios) in radeon_pm_init_dpm()
1433 return -EINVAL; in radeon_pm_init_dpm()
1440 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler); in radeon_pm_init_dpm()
1441 mutex_lock(&rdev->pm.mutex); in radeon_pm_init_dpm()
1443 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; in radeon_pm_init_dpm()
1448 mutex_unlock(&rdev->pm.mutex); in radeon_pm_init_dpm()
1451 rdev->pm.dpm_enabled = true; in radeon_pm_init_dpm()
1460 rdev->pm.dpm_enabled = false; in radeon_pm_init_dpm()
1461 if ((rdev->family >= CHIP_BARTS) && in radeon_pm_init_dpm()
1462 (rdev->family <= CHIP_CAYMAN) && in radeon_pm_init_dpm()
1463 rdev->mc_fw) { in radeon_pm_init_dpm()
1464 if (rdev->pm.default_vddc) in radeon_pm_init_dpm()
1465 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, in radeon_pm_init_dpm()
1467 if (rdev->pm.default_vddci) in radeon_pm_init_dpm()
1468 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, in radeon_pm_init_dpm()
1470 if (rdev->pm.default_sclk) in radeon_pm_init_dpm()
1471 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); in radeon_pm_init_dpm()
1472 if (rdev->pm.default_mclk) in radeon_pm_init_dpm()
1473 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); in radeon_pm_init_dpm()
1488 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */
1490 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */
1501 while (p && p->chip_device != 0) { in radeon_pm_init()
1502 if (rdev->pdev->vendor == p->chip_vendor && in radeon_pm_init()
1503 rdev->pdev->device == p->chip_device && in radeon_pm_init()
1504 rdev->pdev->subsystem_vendor == p->subsys_vendor && in radeon_pm_init()
1505 rdev->pdev->subsystem_device == p->subsys_device) { in radeon_pm_init()
1513 switch (rdev->family) { in radeon_pm_init()
1523 if (!rdev->rlc_fw) in radeon_pm_init()
1524 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_pm_init()
1525 else if ((rdev->family >= CHIP_RV770) && in radeon_pm_init()
1526 (!(rdev->flags & RADEON_IS_IGP)) && in radeon_pm_init()
1527 (!rdev->smc_fw)) in radeon_pm_init()
1528 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_pm_init()
1530 rdev->pm.pm_method = PM_METHOD_DPM; in radeon_pm_init()
1532 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_pm_init()
1561 if (!rdev->rlc_fw) in radeon_pm_init()
1562 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_pm_init()
1563 else if ((rdev->family >= CHIP_RV770) && in radeon_pm_init()
1564 (!(rdev->flags & RADEON_IS_IGP)) && in radeon_pm_init()
1565 (!rdev->smc_fw)) in radeon_pm_init()
1566 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_pm_init()
1567 else if (disable_dpm && (radeon_dpm == -1)) in radeon_pm_init()
1568 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_pm_init()
1570 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_pm_init()
1572 rdev->pm.pm_method = PM_METHOD_DPM; in radeon_pm_init()
1575 /* default to profile method */ in radeon_pm_init()
1576 rdev->pm.pm_method = PM_METHOD_PROFILE; in radeon_pm_init()
1580 if (rdev->pm.pm_method == PM_METHOD_DPM) in radeon_pm_init()
1590 if (rdev->pm.pm_method == PM_METHOD_DPM) { in radeon_pm_late_init()
1591 if (rdev->pm.dpm_enabled) { in radeon_pm_late_init()
1592 if (!rdev->pm.sysfs_initialized) { in radeon_pm_late_init()
1593 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state); in radeon_pm_late_init()
1596 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); in radeon_pm_late_init()
1600 ret = device_create_file(rdev->dev, &dev_attr_power_profile); in radeon_pm_late_init()
1602 DRM_ERROR("failed to create device file for power profile\n"); in radeon_pm_late_init()
1603 ret = device_create_file(rdev->dev, &dev_attr_power_method); in radeon_pm_late_init()
1606 rdev->pm.sysfs_initialized = true; in radeon_pm_late_init()
1609 mutex_lock(&rdev->pm.mutex); in radeon_pm_late_init()
1611 mutex_unlock(&rdev->pm.mutex); in radeon_pm_late_init()
1613 rdev->pm.dpm_enabled = false; in radeon_pm_late_init()
1623 if ((rdev->pm.num_power_states > 1) && in radeon_pm_late_init()
1624 (!rdev->pm.sysfs_initialized)) { in radeon_pm_late_init()
1626 ret = device_create_file(rdev->dev, &dev_attr_power_profile); in radeon_pm_late_init()
1628 DRM_ERROR("failed to create device file for power profile\n"); in radeon_pm_late_init()
1629 ret = device_create_file(rdev->dev, &dev_attr_power_method); in radeon_pm_late_init()
1633 rdev->pm.sysfs_initialized = true; in radeon_pm_late_init()
1641 if (rdev->pm.num_power_states > 1) { in radeon_pm_fini_old()
1642 mutex_lock(&rdev->pm.mutex); in radeon_pm_fini_old()
1643 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { in radeon_pm_fini_old()
1644 rdev->pm.profile = PM_PROFILE_DEFAULT; in radeon_pm_fini_old()
1647 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { in radeon_pm_fini_old()
1649 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; in radeon_pm_fini_old()
1650 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; in radeon_pm_fini_old()
1653 mutex_unlock(&rdev->pm.mutex); in radeon_pm_fini_old()
1655 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); in radeon_pm_fini_old()
1657 device_remove_file(rdev->dev, &dev_attr_power_profile); in radeon_pm_fini_old()
1658 device_remove_file(rdev->dev, &dev_attr_power_method); in radeon_pm_fini_old()
1662 kfree(rdev->pm.power_state); in radeon_pm_fini_old()
1667 if (rdev->pm.num_power_states > 1) { in radeon_pm_fini_dpm()
1668 mutex_lock(&rdev->pm.mutex); in radeon_pm_fini_dpm()
1670 mutex_unlock(&rdev->pm.mutex); in radeon_pm_fini_dpm()
1672 device_remove_file(rdev->dev, &dev_attr_power_dpm_state); in radeon_pm_fini_dpm()
1673 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); in radeon_pm_fini_dpm()
1675 device_remove_file(rdev->dev, &dev_attr_power_profile); in radeon_pm_fini_dpm()
1676 device_remove_file(rdev->dev, &dev_attr_power_method); in radeon_pm_fini_dpm()
1681 kfree(rdev->pm.power_state); in radeon_pm_fini_dpm()
1686 if (rdev->pm.pm_method == PM_METHOD_DPM) in radeon_pm_fini()
1694 struct drm_device *ddev = rdev->ddev; in radeon_pm_compute_clocks_old()
1698 if (rdev->pm.num_power_states < 2) in radeon_pm_compute_clocks_old()
1701 mutex_lock(&rdev->pm.mutex); in radeon_pm_compute_clocks_old()
1703 rdev->pm.active_crtcs = 0; in radeon_pm_compute_clocks_old()
1704 rdev->pm.active_crtc_count = 0; in radeon_pm_compute_clocks_old()
1705 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { in radeon_pm_compute_clocks_old()
1707 &ddev->mode_config.crtc_list, head) { in radeon_pm_compute_clocks_old()
1709 if (radeon_crtc->enabled) { in radeon_pm_compute_clocks_old()
1710 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); in radeon_pm_compute_clocks_old()
1711 rdev->pm.active_crtc_count++; in radeon_pm_compute_clocks_old()
1716 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { in radeon_pm_compute_clocks_old()
1719 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { in radeon_pm_compute_clocks_old()
1720 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { in radeon_pm_compute_clocks_old()
1721 if (rdev->pm.active_crtc_count > 1) { in radeon_pm_compute_clocks_old()
1722 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { in radeon_pm_compute_clocks_old()
1723 cancel_delayed_work(&rdev->pm.dynpm_idle_work); in radeon_pm_compute_clocks_old()
1725 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; in radeon_pm_compute_clocks_old()
1726 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; in radeon_pm_compute_clocks_old()
1732 } else if (rdev->pm.active_crtc_count == 1) { in radeon_pm_compute_clocks_old()
1735 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { in radeon_pm_compute_clocks_old()
1736 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; in radeon_pm_compute_clocks_old()
1737 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; in radeon_pm_compute_clocks_old()
1741 schedule_delayed_work(&rdev->pm.dynpm_idle_work, in radeon_pm_compute_clocks_old()
1743 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { in radeon_pm_compute_clocks_old()
1744 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; in radeon_pm_compute_clocks_old()
1745 schedule_delayed_work(&rdev->pm.dynpm_idle_work, in radeon_pm_compute_clocks_old()
1750 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { in radeon_pm_compute_clocks_old()
1751 cancel_delayed_work(&rdev->pm.dynpm_idle_work); in radeon_pm_compute_clocks_old()
1753 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; in radeon_pm_compute_clocks_old()
1754 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; in radeon_pm_compute_clocks_old()
1762 mutex_unlock(&rdev->pm.mutex); in radeon_pm_compute_clocks_old()
1767 struct drm_device *ddev = rdev->ddev; in radeon_pm_compute_clocks_dpm()
1772 if (!rdev->pm.dpm_enabled) in radeon_pm_compute_clocks_dpm()
1775 mutex_lock(&rdev->pm.mutex); in radeon_pm_compute_clocks_dpm()
1778 rdev->pm.dpm.new_active_crtcs = 0; in radeon_pm_compute_clocks_dpm()
1779 rdev->pm.dpm.new_active_crtc_count = 0; in radeon_pm_compute_clocks_dpm()
1780 rdev->pm.dpm.high_pixelclock_count = 0; in radeon_pm_compute_clocks_dpm()
1781 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { in radeon_pm_compute_clocks_dpm()
1783 &ddev->mode_config.crtc_list, head) { in radeon_pm_compute_clocks_dpm()
1785 if (crtc->enabled) { in radeon_pm_compute_clocks_dpm()
1786 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); in radeon_pm_compute_clocks_dpm()
1787 rdev->pm.dpm.new_active_crtc_count++; in radeon_pm_compute_clocks_dpm()
1788 if (!radeon_crtc->connector) in radeon_pm_compute_clocks_dpm()
1791 radeon_connector = to_radeon_connector(radeon_crtc->connector); in radeon_pm_compute_clocks_dpm()
1792 if (radeon_connector->pixelclock_for_modeset > 297000) in radeon_pm_compute_clocks_dpm()
1793 rdev->pm.dpm.high_pixelclock_count++; in radeon_pm_compute_clocks_dpm()
1798 /* update battery/ac status */ in radeon_pm_compute_clocks_dpm()
1800 rdev->pm.dpm.ac_power = true; in radeon_pm_compute_clocks_dpm()
1802 rdev->pm.dpm.ac_power = false; in radeon_pm_compute_clocks_dpm()
1806 mutex_unlock(&rdev->pm.mutex); in radeon_pm_compute_clocks_dpm()
1812 if (rdev->pm.pm_method == PM_METHOD_DPM) in radeon_pm_compute_clocks()
1826 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { in radeon_pm_in_vbl()
1827 if (rdev->pm.active_crtcs & (1 << crtc)) { in radeon_pm_in_vbl()
1828 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, in radeon_pm_in_vbl()
1832 &rdev->mode_info.crtcs[crtc]->base.hwmode); in radeon_pm_in_vbl()
1860 mutex_lock(&rdev->pm.mutex); in radeon_dynpm_idle_work_handler()
1861 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { in radeon_dynpm_idle_work_handler()
1866 struct radeon_ring *ring = &rdev->ring[i]; in radeon_dynpm_idle_work_handler()
1868 if (ring->ready) { in radeon_dynpm_idle_work_handler()
1876 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { in radeon_dynpm_idle_work_handler()
1877 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; in radeon_dynpm_idle_work_handler()
1878 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && in radeon_dynpm_idle_work_handler()
1879 rdev->pm.dynpm_can_upclock) { in radeon_dynpm_idle_work_handler()
1880 rdev->pm.dynpm_planned_action = in radeon_dynpm_idle_work_handler()
1882 rdev->pm.dynpm_action_timeout = jiffies + in radeon_dynpm_idle_work_handler()
1886 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { in radeon_dynpm_idle_work_handler()
1887 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; in radeon_dynpm_idle_work_handler()
1888 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && in radeon_dynpm_idle_work_handler()
1889 rdev->pm.dynpm_can_downclock) { in radeon_dynpm_idle_work_handler()
1890 rdev->pm.dynpm_planned_action = in radeon_dynpm_idle_work_handler()
1892 rdev->pm.dynpm_action_timeout = jiffies + in radeon_dynpm_idle_work_handler()
1900 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && in radeon_dynpm_idle_work_handler()
1901 time_after(jiffies, rdev->pm.dynpm_action_timeout)) { in radeon_dynpm_idle_work_handler()
1906 schedule_delayed_work(&rdev->pm.dynpm_idle_work, in radeon_dynpm_idle_work_handler()
1909 mutex_unlock(&rdev->pm.mutex); in radeon_dynpm_idle_work_handler()
1919 struct radeon_device *rdev = m->private; in radeon_debugfs_pm_info_show()
1920 struct drm_device *ddev = rdev->ddev; in radeon_debugfs_pm_info_show()
1922 if ((rdev->flags & RADEON_IS_PX) && in radeon_debugfs_pm_info_show()
1923 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { in radeon_debugfs_pm_info_show()
1925 } else if (rdev->pm.dpm_enabled) { in radeon_debugfs_pm_info_show()
1926 mutex_lock(&rdev->pm.mutex); in radeon_debugfs_pm_info_show()
1927 if (rdev->asic->dpm.debugfs_print_current_performance_level) in radeon_debugfs_pm_info_show()
1931 mutex_unlock(&rdev->pm.mutex); in radeon_debugfs_pm_info_show()
1933 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); in radeon_debugfs_pm_info_show()
1935 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP)) in radeon_debugfs_pm_info_show()
1936 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); in radeon_debugfs_pm_info_show()
1939 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); in radeon_debugfs_pm_info_show()
1940 if (rdev->asic->pm.get_memory_clock) in radeon_debugfs_pm_info_show()
1942 if (rdev->pm.current_vddc) in radeon_debugfs_pm_info_show()
1943 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); in radeon_debugfs_pm_info_show()
1944 if (rdev->asic->pm.get_pcie_lanes) in radeon_debugfs_pm_info_show()
1957 struct dentry *root = rdev->ddev->primary->debugfs_root; in radeon_debugfs_pm_init()