2799 	struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc;  in evergreen_dma_cs_parse()  local
2854 			r = r600_dma_cs_next_reloc(p, &src_reloc);  in evergreen_dma_cs_parse()
2872 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2874 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2883 				ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
2885 				ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2895 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
2905 					ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
2906 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2912 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2914 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2931 				if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2933 							src_offset + count, radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2942 				ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff);  in evergreen_dma_cs_parse()
2944 				ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2954 				ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff);  in evergreen_dma_cs_parse()
2955 				ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2975 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2977 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2992 				ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
2995 				ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3015 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3017 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3032 				ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3033 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3046 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3052 					ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3053 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3077 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3079 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3094 				ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3095 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3106 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3116 					ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3117 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3123 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3125 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3142 				ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3164 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3166 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3181 				ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3182 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()