33 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);  in visionox_vtdr6130_reset()
37 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);  in visionox_vtdr6130_reset()
53 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20);  in visionox_vtdr6130_on()
54 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, 0x00, 0x00);  in visionox_vtdr6130_on()
55 	mipi_dsi_dcs_write_seq(dsi, 0x59, 0x09);  in visionox_vtdr6130_on()
56 	mipi_dsi_dcs_write_seq(dsi, 0x6c, 0x01);  in visionox_vtdr6130_on()
57 	mipi_dsi_dcs_write_seq(dsi, 0x6d, 0x00);  in visionox_vtdr6130_on()
58 	mipi_dsi_dcs_write_seq(dsi, 0x6f, 0x01);  in visionox_vtdr6130_on()
59 	mipi_dsi_dcs_write_seq(dsi, 0x70,  in visionox_vtdr6130_on()
60 			       0x12, 0x00, 0x00, 0xab, 0x30, 0x80, 0x09, 0x60, 0x04,  in visionox_vtdr6130_on()
61 			       0x38, 0x00, 0x28, 0x02, 0x1c, 0x02, 0x1c, 0x02, 0x00,  in visionox_vtdr6130_on()
62 			       0x02, 0x0e, 0x00, 0x20, 0x03, 0xdd, 0x00, 0x07, 0x00,  in visionox_vtdr6130_on()
63 			       0x0c, 0x02, 0x77, 0x02, 0x8b, 0x18, 0x00, 0x10, 0xf0,  in visionox_vtdr6130_on()
64 			       0x07, 0x10, 0x20, 0x00, 0x06, 0x0f, 0x0f, 0x33, 0x0e,  in visionox_vtdr6130_on()
65 			       0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,  in visionox_vtdr6130_on()
66 			       0x79, 0x7b, 0x7d, 0x7e, 0x02, 0x02, 0x22, 0x00, 0x2a,  in visionox_vtdr6130_on()
67 			       0x40, 0x2a, 0xbe, 0x3a, 0xfc, 0x3a, 0xfa, 0x3a, 0xf8,  in visionox_vtdr6130_on()
68 			       0x3b, 0x38, 0x3b, 0x78, 0x3b, 0xb6, 0x4b, 0xb6, 0x4b,  in visionox_vtdr6130_on()
69 			       0xf4, 0x4b, 0xf4, 0x6c, 0x34, 0x84, 0x74, 0x00, 0x00,  in visionox_vtdr6130_on()
70 			       0x00, 0x00, 0x00, 0x00);  in visionox_vtdr6130_on()
71 	mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xaa, 0x10);  in visionox_vtdr6130_on()
72 	mipi_dsi_dcs_write_seq(dsi, 0xb1,  in visionox_vtdr6130_on()
73 			       0x01, 0x38, 0x00, 0x14, 0x00, 0x1c, 0x00, 0x01, 0x66,  in visionox_vtdr6130_on()
74 			       0x00, 0x14, 0x00, 0x14, 0x00, 0x01, 0x66, 0x00, 0x14,  in visionox_vtdr6130_on()
75 			       0x05, 0xcc, 0x00);  in visionox_vtdr6130_on()
76 	mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xaa, 0x13);  in visionox_vtdr6130_on()
77 	mipi_dsi_dcs_write_seq(dsi, 0xce,  in visionox_vtdr6130_on()
78 			       0x09, 0x11, 0x09, 0x11, 0x08, 0xc1, 0x07, 0xfa, 0x05,  in visionox_vtdr6130_on()
79 			       0xa4, 0x00, 0x3c, 0x00, 0x34, 0x00, 0x24, 0x00, 0x0c,  in visionox_vtdr6130_on()
80 			       0x00, 0x0c, 0x04, 0x00, 0x35);  in visionox_vtdr6130_on()
81 	mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xaa, 0x14);  in visionox_vtdr6130_on()
82 	mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x03, 0x33);  in visionox_vtdr6130_on()
83 	mipi_dsi_dcs_write_seq(dsi, 0xb4,  in visionox_vtdr6130_on()
84 			       0x00, 0x33, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00,  in visionox_vtdr6130_on()
85 			       0x3e, 0x00, 0x00);  in visionox_vtdr6130_on()
86 	mipi_dsi_dcs_write_seq(dsi, 0xb5,  in visionox_vtdr6130_on()
87 			       0x00, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x06, 0x01);  in visionox_vtdr6130_on()
88 	mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x00, 0x00, 0x08, 0x09, 0x09, 0x09);  in visionox_vtdr6130_on()
89 	mipi_dsi_dcs_write_seq(dsi, 0xbc,  in visionox_vtdr6130_on()
90 			       0x10, 0x00, 0x00, 0x06, 0x11, 0x09, 0x3b, 0x09, 0x47,  in visionox_vtdr6130_on()
91 			       0x09, 0x47, 0x00);  in visionox_vtdr6130_on()
92 	mipi_dsi_dcs_write_seq(dsi, 0xbe,  in visionox_vtdr6130_on()
93 			       0x10, 0x10, 0x00, 0x08, 0x22, 0x09, 0x19, 0x09, 0x25,  in visionox_vtdr6130_on()
94 			       0x09, 0x25, 0x00);  in visionox_vtdr6130_on()
95 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x80);  in visionox_vtdr6130_on()
96 	mipi_dsi_dcs_write_seq(dsi, 0x65, 0x14);  in visionox_vtdr6130_on()
97 	mipi_dsi_dcs_write_seq(dsi, 0xfa, 0x08, 0x08, 0x08);  in visionox_vtdr6130_on()
98 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x81);  in visionox_vtdr6130_on()
99 	mipi_dsi_dcs_write_seq(dsi, 0x65, 0x05);  in visionox_vtdr6130_on()
100 	mipi_dsi_dcs_write_seq(dsi, 0xf3, 0x0f);  in visionox_vtdr6130_on()
101 	mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xaa, 0x00);  in visionox_vtdr6130_on()
102 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x82);  in visionox_vtdr6130_on()
103 	mipi_dsi_dcs_write_seq(dsi, 0xf9, 0x00);  in visionox_vtdr6130_on()
104 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x51, 0x83);  in visionox_vtdr6130_on()
105 	mipi_dsi_dcs_write_seq(dsi, 0x65, 0x04);  in visionox_vtdr6130_on()
106 	mipi_dsi_dcs_write_seq(dsi, 0xf8, 0x00);  in visionox_vtdr6130_on()
107 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x00);  in visionox_vtdr6130_on()
108 	mipi_dsi_dcs_write_seq(dsi, 0x65, 0x01);  in visionox_vtdr6130_on()
109 	mipi_dsi_dcs_write_seq(dsi, 0xf4, 0x9a);  in visionox_vtdr6130_on()
110 	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x00);  in visionox_vtdr6130_on()
113 	if (ret < 0) {  in visionox_vtdr6130_on()
120 	if (ret < 0) {  in visionox_vtdr6130_on()
126 	return 0;  in visionox_vtdr6130_on()
138 	if (ret < 0) {  in visionox_vtdr6130_off()
145 	if (ret < 0) {  in visionox_vtdr6130_off()
151 	return 0;  in visionox_vtdr6130_off()
161 		return 0;  in visionox_vtdr6130_prepare()
165 	if (ret < 0)  in visionox_vtdr6130_prepare()
171 	if (ret < 0) {  in visionox_vtdr6130_prepare()
179 	return 0;  in visionox_vtdr6130_prepare()
189 		return 0;  in visionox_vtdr6130_unprepare()
192 	if (ret < 0)  in visionox_vtdr6130_unprepare()
200 	return 0;  in visionox_vtdr6130_unprepare()
278 	ctx->supplies[0].supply = "vddio";  in visionox_vtdr6130_probe()
284 	if (ret < 0)  in visionox_vtdr6130_probe()
311 	if (ret < 0) {  in visionox_vtdr6130_probe()
317 	return 0;  in visionox_vtdr6130_probe()
326 	if (ret < 0)  in visionox_vtdr6130_remove()