Lines Matching +full:0 +full:x7d

22 #define MCS_CMD_MODE_SW		0xFE /* CMD Mode Switch */
23 #define MCS_CMD1_UCS 0x00 /* User Command Set (UCS = CMD1) */
24 #define MCS_CMD2_P0 0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
25 #define MCS_CMD2_P1 0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
26 #define MCS_CMD2_P2 0x03 /* Manufacture Command Set Page2 (CMD2 P2) */
27 #define MCS_CMD2_P3 0x04 /* Manufacture Command Set Page3 (CMD2 P3) */
30 #define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */
31 #define MCS_SGOPCTR 0x16 /* Source Bias Current */
32 #define MCS_SDCTR 0x1A /* Source Output Delay Time */
33 #define MCS_INVCTR 0x1B /* Inversion Type */
34 #define MCS_EXT_PWR_IC 0x24 /* External PWR IC Control */
35 #define MCS_SETAVDD 0x27 /* PFM Control for AVDD Output */
36 #define MCS_SETAVEE 0x29 /* PFM Control for AVEE Output */
37 #define MCS_BT2CTR 0x2B /* DDVDL Charge Pump Control */
38 #define MCS_BT3CTR 0x2F /* VGH Charge Pump Control */
39 #define MCS_BT4CTR 0x34 /* VGL Charge Pump Control */
40 #define MCS_VCMCTR 0x46 /* VCOM Output Level Control */
41 #define MCS_SETVGN 0x52 /* VG M/S N Control */
42 #define MCS_SETVGP 0x54 /* VG M/S P Control */
43 #define MCS_SW_CTRL 0x5F /* Interface Control for PFM and MIPI */
46 #define GOA_VSTV1 0x00
47 #define GOA_VSTV2 0x07
48 #define GOA_VCLK1 0x0E
49 #define GOA_VCLK2 0x17
50 #define GOA_VCLK_OPT1 0x20
51 #define GOA_BICLK1 0x2A
52 #define GOA_BICLK2 0x37
53 #define GOA_BICLK3 0x44
54 #define GOA_BICLK4 0x4F
55 #define GOA_BICLK_OPT1 0x5B
56 #define GOA_BICLK_OPT2 0x60
57 #define MCS_GOA_GPO1 0x6D
58 #define MCS_GOA_GPO2 0x71
59 #define MCS_GOA_EQ 0x74
60 #define MCS_GOA_CLK_GALLON 0x7C
61 #define MCS_GOA_FS_SEL0 0x7E
62 #define MCS_GOA_FS_SEL1 0x87
63 #define MCS_GOA_FS_SEL2 0x91
64 #define MCS_GOA_FS_SEL3 0x9B
65 #define MCS_GOA_BS_SEL0 0xAC
66 #define MCS_GOA_BS_SEL1 0xB5
67 #define MCS_GOA_BS_SEL2 0xBF
68 #define MCS_GOA_BS_SEL3 0xC9
69 #define MCS_GOA_BS_SEL4 0xD3
72 #define MCS_GAMMA_VP 0x60 /* Gamma VP1~VP16 */
73 #define MCS_GAMMA_VN 0x70 /* Gamma VN1~VN16 */
94 .flags = 0,
111 if (err < 0) in rm68200_dcs_write_buf()
121 if (err < 0) in rm68200_dcs_write_cmd()
141 for (i = 0; i < ARRAY_SIZE(d) ; i++) \
147 /* Enter CMD2 with page 0 */ in rm68200_init_sequence()
149 dcs_write_cmd_seq(ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00); in rm68200_init_sequence()
150 dcs_write_seq(ctx, MCS_BT2CTR, 0xE5); in rm68200_init_sequence()
151 dcs_write_seq(ctx, MCS_SETAVDD, 0x0A); in rm68200_init_sequence()
152 dcs_write_seq(ctx, MCS_SETAVEE, 0x0A); in rm68200_init_sequence()
153 dcs_write_seq(ctx, MCS_SGOPCTR, 0x52); in rm68200_init_sequence()
154 dcs_write_seq(ctx, MCS_BT3CTR, 0x53); in rm68200_init_sequence()
155 dcs_write_seq(ctx, MCS_BT4CTR, 0x5A); in rm68200_init_sequence()
156 dcs_write_seq(ctx, MCS_INVCTR, 0x00); in rm68200_init_sequence()
157 dcs_write_seq(ctx, MCS_STBCTR, 0x0A); in rm68200_init_sequence()
158 dcs_write_seq(ctx, MCS_SDCTR, 0x06); in rm68200_init_sequence()
159 dcs_write_seq(ctx, MCS_VCMCTR, 0x56); in rm68200_init_sequence()
160 dcs_write_seq(ctx, MCS_SETVGN, 0xA0, 0x00); in rm68200_init_sequence()
161 dcs_write_seq(ctx, MCS_SETVGP, 0xA0, 0x00); in rm68200_init_sequence()
162 dcs_write_seq(ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */ in rm68200_init_sequence()
165 dcs_write_seq(ctx, GOA_VSTV1, 0x05); in rm68200_init_sequence()
166 dcs_write_seq(ctx, 0x02, 0x0B); in rm68200_init_sequence()
167 dcs_write_seq(ctx, 0x03, 0x0F); in rm68200_init_sequence()
168 dcs_write_seq(ctx, 0x04, 0x7D, 0x00, 0x50); in rm68200_init_sequence()
169 dcs_write_cmd_seq(ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00, in rm68200_init_sequence()
170 0x50); in rm68200_init_sequence()
171 dcs_write_cmd_seq(ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D, in rm68200_init_sequence()
172 0x00, 0x85, 0x08); in rm68200_init_sequence()
173 dcs_write_cmd_seq(ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D, in rm68200_init_sequence()
174 0x00, 0x85, 0x08); in rm68200_init_sequence()
175 dcs_write_seq(ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, in rm68200_init_sequence()
176 0x00, 0x00, 0x00, 0x00); in rm68200_init_sequence()
177 dcs_write_cmd_seq(ctx, GOA_BICLK1, 0x07, 0x08); in rm68200_init_sequence()
178 dcs_write_seq(ctx, 0x2D, 0x01); in rm68200_init_sequence()
179 dcs_write_seq(ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D, in rm68200_init_sequence()
180 0x00); in rm68200_init_sequence()
181 dcs_write_cmd_seq(ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00); in rm68200_init_sequence()
182 dcs_write_seq(ctx, 0x3D, 0x40); in rm68200_init_sequence()
183 dcs_write_seq(ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00); in rm68200_init_sequence()
184 dcs_write_seq(ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, in rm68200_init_sequence()
185 0x00, 0x00, 0x00, 0x00, 0x00); in rm68200_init_sequence()
186 dcs_write_seq(ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, in rm68200_init_sequence()
187 0x00, 0x00); in rm68200_init_sequence()
188 dcs_write_seq(ctx, 0x58, 0x00, 0x00, 0x00); in rm68200_init_sequence()
189 dcs_write_seq(ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00); in rm68200_init_sequence()
190 dcs_write_seq(ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, in rm68200_init_sequence()
191 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); in rm68200_init_sequence()
192 dcs_write_seq(ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00); in rm68200_init_sequence()
193 dcs_write_seq(ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00); in rm68200_init_sequence()
194 dcs_write_seq(ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, in rm68200_init_sequence()
195 0x00, 0x00); in rm68200_init_sequence()
196 dcs_write_seq(ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00); in rm68200_init_sequence()
197 dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10, in rm68200_init_sequence()
198 0x16, 0x12, 0x08, 0x3F); in rm68200_init_sequence()
199 dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C, in rm68200_init_sequence()
200 0x0A, 0x0E, 0x3F, 0x3F, 0x00); in rm68200_init_sequence()
201 dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F, in rm68200_init_sequence()
202 0x05, 0x01, 0x3F, 0x3F, 0x0F); in rm68200_init_sequence()
203 dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F, in rm68200_init_sequence()
204 0x3F); in rm68200_init_sequence()
205 dcs_write_cmd_seq(ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15); in rm68200_init_sequence()
206 dcs_write_cmd_seq(ctx, 0xA9, 0x07, 0x03, 0x3F); in rm68200_init_sequence()
207 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13, in rm68200_init_sequence()
208 0x15, 0x11, 0x0F, 0x3F); in rm68200_init_sequence()
209 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B, in rm68200_init_sequence()
210 0x0D, 0x09, 0x3F, 0x3F, 0x07); in rm68200_init_sequence()
211 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F, in rm68200_init_sequence()
212 0x02, 0x06, 0x3F, 0x3F, 0x08); in rm68200_init_sequence()
213 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F, in rm68200_init_sequence()
214 0x3F, 0x3F, 0x0E, 0x10, 0x14); in rm68200_init_sequence()
215 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F); in rm68200_init_sequence()
216 dcs_write_seq(ctx, 0xDC, 0x02); in rm68200_init_sequence()
217 dcs_write_seq(ctx, 0xDE, 0x12); in rm68200_init_sequence()
219 dcs_write_seq(ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */ in rm68200_init_sequence()
220 dcs_write_seq(ctx, 0x01, 0x75); in rm68200_init_sequence()
223 dcs_write_cmd_seq(ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06, in rm68200_init_sequence()
224 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F, in rm68200_init_sequence()
225 0x12, 0x0C, 0x00); in rm68200_init_sequence()
226 dcs_write_cmd_seq(ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06, in rm68200_init_sequence()
227 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F, in rm68200_init_sequence()
228 0x12, 0x0C, 0x00); in rm68200_init_sequence()
239 return 0; in rm68200_disable()
243 return 0; in rm68200_disable()
253 return 0; in rm68200_unprepare()
274 return 0; in rm68200_unprepare()
284 return 0; in rm68200_prepare()
287 if (ret < 0) { in rm68200_prepare()
295 gpiod_set_value_cansleep(ctx->reset_gpio, 0); in rm68200_prepare()
315 return 0; in rm68200_prepare()
323 return 0; in rm68200_enable()
327 return 0; in rm68200_enable()
406 if (ret < 0) { in rm68200_probe()
412 return 0; in rm68200_probe()