27 enum nv40_sensor_style { INVALID_STYLE = -1, OLD_STYLE = 0, NEW_STYLE = 1 };
33 	case 0x43:  in nv40_sensor_style()
34 	case 0x44:  in nv40_sensor_style()
35 	case 0x4a:  in nv40_sensor_style()
36 	case 0x47:  in nv40_sensor_style()
38 	case 0x46:  in nv40_sensor_style()
39 	case 0x49:  in nv40_sensor_style()
40 	case 0x4b:  in nv40_sensor_style()
41 	case 0x4e:  in nv40_sensor_style()
42 	case 0x4c:  in nv40_sensor_style()
43 	case 0x67:  in nv40_sensor_style()
44 	case 0x68:  in nv40_sensor_style()
45 	case 0x63:  in nv40_sensor_style()
60 		nvkm_mask(device, 0x15b8, 0x80000000, 0);  in nv40_sensor_setup()
61 		nvkm_wr32(device, 0x15b0, 0x80003fff);  in nv40_sensor_setup()
63 		return nvkm_rd32(device, 0x15b4) & 0x3fff;  in nv40_sensor_setup()
65 		nvkm_wr32(device, 0x15b0, 0xff);  in nv40_sensor_setup()
67 		return nvkm_rd32(device, 0x15b4) & 0xff;  in nv40_sensor_setup()
81 		nvkm_wr32(device, 0x15b0, 0x80003fff);  in nv40_temp_get()
82 		core_temp = nvkm_rd32(device, 0x15b4) & 0x3fff;  in nv40_temp_get()
84 		nvkm_wr32(device, 0x15b0, 0xff);  in nv40_temp_get()
85 		core_temp = nvkm_rd32(device, 0x15b4) & 0xff;  in nv40_temp_get()
99 	if (core_temp < 0)  in nv40_temp_get()
100 		core_temp = 0;  in nv40_temp_get()
110 	u32 mask = enable ? 0x80000000 : 0x00000000;  in nv40_fan_pwm_ctrl()
111 	if      (line == 2) nvkm_mask(device, 0x0010f0, 0x80000000, mask);  in nv40_fan_pwm_ctrl()
112 	else if (line == 9) nvkm_mask(device, 0x0015f4, 0x80000000, mask);  in nv40_fan_pwm_ctrl()
117 	return 0;  in nv40_fan_pwm_ctrl()
126 		u32 reg = nvkm_rd32(device, 0x0010f0);  in nv40_fan_pwm_get()
127 		if (reg & 0x80000000) {  in nv40_fan_pwm_get()
128 			*duty = (reg & 0x7fff0000) >> 16;  in nv40_fan_pwm_get()
129 			*divs = (reg & 0x00007fff);  in nv40_fan_pwm_get()
130 			return 0;  in nv40_fan_pwm_get()
134 		u32 reg = nvkm_rd32(device, 0x0015f4);  in nv40_fan_pwm_get()
135 		if (reg & 0x80000000) {  in nv40_fan_pwm_get()
136 			*divs = nvkm_rd32(device, 0x0015f8);  in nv40_fan_pwm_get()
137 			*duty = (reg & 0x7fffffff);  in nv40_fan_pwm_get()
138 			return 0;  in nv40_fan_pwm_get()
154 		nvkm_mask(device, 0x0010f0, 0x7fff7fff, (duty << 16) | divs);  in nv40_fan_pwm_set()
157 		nvkm_wr32(device, 0x0015f8, divs);  in nv40_fan_pwm_set()
158 		nvkm_mask(device, 0x0015f4, 0x7fffffff, duty);  in nv40_fan_pwm_set()
164 	return 0;  in nv40_fan_pwm_set()
172 	uint32_t stat = nvkm_rd32(device, 0x1100);  in nv40_therm_intr()
177 	nvkm_wr32(device, 0x1100, 0x70000);  in nv40_therm_intr()