1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
14 #include <linux/soc/qcom/llcc-qcom.h>
23 	/* Check that the GMU is idle */  in _a6xx_check_idle()
24 	if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu))  in _a6xx_check_idle()
44 			gpu->name, __builtin_return_address(0),  in a6xx_idle()
61 	if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) {  in update_shadow_rptr()
75 	spin_lock_irqsave(&ring->preempt_lock, flags);  in a6xx_flush()
78 	ring->cur = ring->next;  in a6xx_flush()
83 	spin_unlock_irqrestore(&ring->preempt_lock, flags);  in a6xx_flush()
105 	bool sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1;  in a6xx_set_pagetable()
110 	if (ctx->seqno == a6xx_gpu->base.base.cur_ctx_seqno)  in a6xx_set_pagetable()
113 	if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))  in a6xx_set_pagetable()
166 		/* Re-enable protected mode: */  in a6xx_set_pagetable()
174 	unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;  in a6xx_submit()
177 	struct msm_ringbuffer *ring = submit->ring;  in a6xx_submit()
180 	a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);  in a6xx_submit()
186 	 * For PM4 the GMU register offsets are calculated from the base of the  in a6xx_submit()
201 	for (i = 0; i < submit->nr_cmds; i++) {  in a6xx_submit()
202 		switch (submit->cmd[i].type) {  in a6xx_submit()
206 			if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno)  in a6xx_submit()
211 			OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));  in a6xx_submit()
212 			OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));  in a6xx_submit()
213 			OUT_RING(ring, submit->cmd[i].size);  in a6xx_submit()
219 		 * Periodically update shadow-wptr if needed, so that we  in a6xx_submit()
236 	OUT_RING(ring, submit->seqno);  in a6xx_submit()
247 	OUT_RING(ring, submit->seqno);  in a6xx_submit()
702 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;  in a6xx_set_hwcg()  local
707 	if (!adreno_gpu->info->hwcg)  in a6xx_set_hwcg()
719 	/* Don't re-program the registers if they are already correct */  in a6xx_set_hwcg()
725 		gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);  in a6xx_set_hwcg()
727 	for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++)  in a6xx_set_hwcg()
728 		gpu_write(gpu, reg->offset, state ? reg->value : 0);  in a6xx_set_hwcg()
732 		gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);  in a6xx_set_hwcg()
938 	for (i = 0; i < count - 1; i++) {  in a6xx_set_cp_protect()
944 	gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]);  in a6xx_set_cp_protect()
956 	/* Entirely magic, per-GPU-gen value */  in a6xx_set_ubwc_config()
1025 	struct msm_ringbuffer *ring = gpu->rb[0];  in a6xx_cp_init()
1049 	return a6xx_idle(gpu, ring) ? 0 : -EINVAL;  in a6xx_cp_init()
1059 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;  in a6xx_ucode_check_version()
1060 	struct msm_gpu *gpu = &adreno_gpu->base;  in a6xx_ucode_check_version()
1061 	const char *sqe_name = adreno_gpu->info->fw[ADRENO_FW_SQE];  in a6xx_ucode_check_version()
1091 			a6xx_gpu->has_whereami = true;  in a6xx_ucode_check_version()
1096 		DRM_DEV_ERROR(&gpu->pdev->dev,  in a6xx_ucode_check_version()
1105 		DRM_DEV_ERROR(&gpu->pdev->dev,  in a6xx_ucode_check_version()
1111 		DRM_DEV_ERROR(&gpu->pdev->dev,  in a6xx_ucode_check_version()
1124 	if (!a6xx_gpu->sqe_bo) {  in a6xx_ucode_load()
1125 		a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu,  in a6xx_ucode_load()
1126 			adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova);  in a6xx_ucode_load()
1128 		if (IS_ERR(a6xx_gpu->sqe_bo)) {  in a6xx_ucode_load()
1129 			int ret = PTR_ERR(a6xx_gpu->sqe_bo);  in a6xx_ucode_load()
1131 			a6xx_gpu->sqe_bo = NULL;  in a6xx_ucode_load()
1132 			DRM_DEV_ERROR(&gpu->pdev->dev,  in a6xx_ucode_load()
1138 		msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw");  in a6xx_ucode_load()
1139 		if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) {  in a6xx_ucode_load()
1140 			msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);  in a6xx_ucode_load()
1141 			drm_gem_object_put(a6xx_gpu->sqe_bo);  in a6xx_ucode_load()
1143 			a6xx_gpu->sqe_bo = NULL;  in a6xx_ucode_load()
1144 			return -EPERM;  in a6xx_ucode_load()
1152 	if ((adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) &&  in a6xx_ucode_load()
1153 	    !a6xx_gpu->shadow_bo) {  in a6xx_ucode_load()
1154 		a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev,  in a6xx_ucode_load()
1155 						      sizeof(u32) * gpu->nr_rings,  in a6xx_ucode_load()
1157 						      gpu->aspace, &a6xx_gpu->shadow_bo,  in a6xx_ucode_load()
1158 						      &a6xx_gpu->shadow_iova);  in a6xx_ucode_load()
1160 		if (IS_ERR(a6xx_gpu->shadow))  in a6xx_ucode_load()
1161 			return PTR_ERR(a6xx_gpu->shadow);  in a6xx_ucode_load()
1163 		msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow");  in a6xx_ucode_load()
1199 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;  in hw_init()  local
1203 		/* Make sure the GMU keeps the GPU on while we set it up */  in hw_init()
1204 		ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);  in hw_init()
1225 		a6xx_sptprac_enable(gmu);  in hw_init()
1228 	 * Disable the trusted memory range - we don't actually supported secure  in hw_init()
1277 		/* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */  in hw_init()
1281 			0x00100000 + adreno_gpu->info->gmem - 1);  in hw_init()
1358 	/* Set up the CX GMU counter 0 to count busy ticks */  in hw_init()
1359 	gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);  in hw_init()
1362 	gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5));  in hw_init()
1363 	gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);  in hw_init()
1378 	if (gpu->hw_apriv) {  in hw_init()
1390 	gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova);  in hw_init()
1393 	gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova);  in hw_init()
1399 	if (adreno_gpu->base.hw_apriv)  in hw_init()
1406 	if (a6xx_gpu->shadow_bo) {  in hw_init()
1408 			shadowptr(a6xx_gpu, gpu->rb[0]));  in hw_init()
1412 	a6xx_gpu->cur_ring = gpu->rb[0];  in hw_init()
1414 	gpu->cur_ctx_seqno = 0;  in hw_init()
1432 		OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1);  in hw_init()
1433 		OUT_RING(gpu->rb[0], 0x00000000);  in hw_init()
1435 		a6xx_flush(gpu, gpu->rb[0]);  in hw_init()
1436 		if (!a6xx_idle(gpu, gpu->rb[0]))  in hw_init()
1437 			return -EINVAL;  in hw_init()
1438 	} else if (ret == -ENODEV) {  in hw_init()
1445 		dev_warn_once(gpu->dev->dev,  in hw_init()
1446 			"Zap shader not enabled - using SECVID_TRUST_CNTL instead\n");  in hw_init()
1457 	 * Tell the GMU that we are done touching the GPU and it can start power  in hw_init()
1460 	a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);  in hw_init()
1462 	if (a6xx_gpu->gmu.legacy) {  in hw_init()
1463 		/* Take the GMU out of its special boot mode */  in hw_init()
1464 		a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);  in hw_init()
1476 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_hw_init()
1478 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_hw_init()
1485 	DRM_DEV_INFO(&gpu->pdev->dev, "status:   %08x\n",  in a6xx_dump()
1494 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;  in a6xx_recover()  local
1500 		DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i,  in a6xx_recover()
1510 	a6xx_gpu->hung = true;  in a6xx_recover()
1515 	pm_runtime_dont_use_autosuspend(&gpu->pdev->dev);  in a6xx_recover()
1518 	mutex_lock(&gpu->active_lock);  in a6xx_recover()
1519 	active_submits = gpu->active_submits;  in a6xx_recover()
1525 	gpu->active_submits = 0;  in a6xx_recover()
1536 	reinit_completion(&gmu->pd_gate);  in a6xx_recover()
1537 	dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb);  in a6xx_recover()
1538 	dev_pm_genpd_synced_poweroff(gmu->cxpd);  in a6xx_recover()
1542 		pm_runtime_put(&gpu->pdev->dev);  in a6xx_recover()
1545 	pm_runtime_put_sync(&gpu->pdev->dev);  in a6xx_recover()
1547 	if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000)))  in a6xx_recover()
1548 		DRM_DEV_ERROR(&gpu->pdev->dev, "cx gdsc didn't collapse\n");  in a6xx_recover()
1550 	dev_pm_genpd_remove_notifier(gmu->cxpd);  in a6xx_recover()
1552 	pm_runtime_use_autosuspend(&gpu->pdev->dev);  in a6xx_recover()
1555 		pm_runtime_get(&gpu->pdev->dev);  in a6xx_recover()
1557 	pm_runtime_get_sync(&gpu->pdev->dev);  in a6xx_recover()
1559 	gpu->active_submits = active_submits;  in a6xx_recover()
1560 	mutex_unlock(&gpu->active_lock);  in a6xx_recover()
1563 	a6xx_gpu->hung = false;  in a6xx_recover()
1620 		block = a6xx_fault_block(gpu, info->fsynr1 & 0xff);  in a6xx_fault_handler()
1634 		dev_err_ratelimited(&gpu->pdev->dev,  in a6xx_cp_hw_err_irq()
1640 		dev_err_ratelimited(&gpu->pdev->dev,  in a6xx_cp_hw_err_irq()
1644 		dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n",  in a6xx_cp_hw_err_irq()
1650 		dev_err_ratelimited(&gpu->pdev->dev,  in a6xx_cp_hw_err_irq()
1657 		dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n");  in a6xx_cp_hw_err_irq()
1660 		dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n");  in a6xx_cp_hw_err_irq()
1663 		dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n");  in a6xx_cp_hw_err_irq()
1671 	struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);  in a6xx_fault_detect_irq()
1687 		gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);  in a6xx_fault_detect_irq()
1689 	DRM_DEV_ERROR(&gpu->pdev->dev,  in a6xx_fault_detect_irq()
1691 		ring ? ring->id : -1, ring ? ring->fctx->last_fence : 0,  in a6xx_fault_detect_irq()
1701 	del_timer(&gpu->hangcheck_timer);  in a6xx_fault_detect_irq()
1703 	kthread_queue_work(gpu->worker, &gpu->recover_work);  in a6xx_fault_detect_irq()
1708 	struct msm_drm_private *priv = gpu->dev->dev_private;  in a6xx_irq()
1713 	if (priv->disable_err_irq)  in a6xx_irq()
1720 		dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n");  in a6xx_irq()
1726 		dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n");  in a6xx_irq()
1729 		dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n");  in a6xx_irq()
1732 		dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");  in a6xx_irq()
1742 	llcc_slice_deactivate(a6xx_gpu->llc_slice);  in a6xx_llc_deactivate()
1743 	llcc_slice_deactivate(a6xx_gpu->htw_llc_slice);  in a6xx_llc_deactivate()
1748 	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;  in a6xx_llc_activate()
1749 	struct msm_gpu *gpu = &adreno_gpu->base;  in a6xx_llc_activate()
1752 	if (IS_ERR(a6xx_gpu->llc_mmio))  in a6xx_llc_activate()
1755 	if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {  in a6xx_llc_activate()
1756 		u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);  in a6xx_llc_activate()
1774 	if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) {  in a6xx_llc_activate()
1775 		if (!a6xx_gpu->have_mmu500) {  in a6xx_llc_activate()
1776 			u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice);  in a6xx_llc_activate()
1790 	if (!a6xx_gpu->have_mmu500) {  in a6xx_llc_activate()
1808 	/* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */  in a6xx_llc_slices_destroy()
1809 	if (adreno_has_gmu_wrapper(&a6xx_gpu->base))  in a6xx_llc_slices_destroy()
1812 	llcc_slice_putd(a6xx_gpu->llc_slice);  in a6xx_llc_slices_destroy()
1813 	llcc_slice_putd(a6xx_gpu->htw_llc_slice);  in a6xx_llc_slices_destroy()
1821 	/* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */  in a6xx_llc_slices_init()
1822 	if (adreno_has_gmu_wrapper(&a6xx_gpu->base))  in a6xx_llc_slices_init()
1829 	phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0);  in a6xx_llc_slices_init()
1830 	a6xx_gpu->have_mmu500 = (phandle &&  in a6xx_llc_slices_init()
1831 		of_device_is_compatible(phandle, "arm,mmu-500"));  in a6xx_llc_slices_init()
1834 	if (a6xx_gpu->have_mmu500)  in a6xx_llc_slices_init()
1835 		a6xx_gpu->llc_mmio = NULL;  in a6xx_llc_slices_init()
1837 		a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem");  in a6xx_llc_slices_init()
1839 	a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);  in a6xx_llc_slices_init()
1840 	a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);  in a6xx_llc_slices_init()
1842 	if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))  in a6xx_llc_slices_init()
1843 		a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);  in a6xx_llc_slices_init()
1854 	struct msm_gpu *gpu = &adreno_gpu->base;  in a6xx_bus_clear_pending_transactions()
1911 	gpu->needs_hw_init = true;  in a6xx_gmu_pm_resume()
1915 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_pm_resume()
1917 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_pm_resume()
1932 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;  in a6xx_pm_resume()  local
1933 	unsigned long freq = gpu->fast_rate;  in a6xx_pm_resume()
1937 	gpu->needs_hw_init = true;  in a6xx_pm_resume()
1941 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_pm_resume()
1943 	opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq);  in a6xx_pm_resume()
1951 	dev_pm_opp_set_opp(&gpu->pdev->dev, opp);  in a6xx_pm_resume()
1953 	pm_runtime_resume_and_get(gmu->dev);  in a6xx_pm_resume()
1954 	pm_runtime_resume_and_get(gmu->gxpd);  in a6xx_pm_resume()
1956 	ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);  in a6xx_pm_resume()
1961 		a6xx_sptprac_enable(gmu);  in a6xx_pm_resume()
1966 		pm_runtime_put(gmu->gxpd);  in a6xx_pm_resume()
1967 		pm_runtime_put(gmu->dev);  in a6xx_pm_resume()
1968 		dev_pm_opp_set_opp(&gpu->pdev->dev, NULL);  in a6xx_pm_resume()
1971 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_pm_resume()
1991 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_pm_suspend()
1993 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_pm_suspend()
1997 	if (a6xx_gpu->shadow_bo)  in a6xx_gmu_pm_suspend()
1998 		for (i = 0; i < gpu->nr_rings; i++)  in a6xx_gmu_pm_suspend()
1999 			a6xx_gpu->shadow[i] = 0;  in a6xx_gmu_pm_suspend()
2001 	gpu->suspend_count++;  in a6xx_gmu_pm_suspend()
2010 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;  in a6xx_pm_suspend()  local
2017 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_pm_suspend()
2023 		a6xx_sptprac_disable(gmu);  in a6xx_pm_suspend()
2025 	clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);  in a6xx_pm_suspend()
2027 	pm_runtime_put_sync(gmu->gxpd);  in a6xx_pm_suspend()
2028 	dev_pm_opp_set_opp(&gpu->pdev->dev, NULL);  in a6xx_pm_suspend()
2029 	pm_runtime_put_sync(gmu->dev);  in a6xx_pm_suspend()
2031 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_pm_suspend()
2033 	if (a6xx_gpu->shadow_bo)  in a6xx_pm_suspend()
2034 		for (i = 0; i < gpu->nr_rings; i++)  in a6xx_pm_suspend()
2035 			a6xx_gpu->shadow[i] = 0;  in a6xx_pm_suspend()
2037 	gpu->suspend_count++;  in a6xx_pm_suspend()
2047 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_get_timestamp()
2050 	a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);  in a6xx_gmu_get_timestamp()
2054 	a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);  in a6xx_gmu_get_timestamp()
2056 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_get_timestamp()
2072 	return a6xx_gpu->cur_ring;  in a6xx_active_ring()
2080 	if (a6xx_gpu->sqe_bo) {  in a6xx_destroy()
2081 		msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);  in a6xx_destroy()
2082 		drm_gem_object_put(a6xx_gpu->sqe_bo);  in a6xx_destroy()
2085 	if (a6xx_gpu->shadow_bo) {  in a6xx_destroy()
2086 		msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace);  in a6xx_destroy()
2087 		drm_gem_object_put(a6xx_gpu->shadow_bo);  in a6xx_destroy()
2108 	busy_cycles = gmu_read64(&a6xx_gpu->gmu,  in a6xx_gpu_busy()
2121 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_gpu_set_freq()
2123 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_gpu_set_freq()
2137 	if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice) &&  in a6xx_create_address_space()
2138 	    !device_iommu_capable(&pdev->dev, IOMMU_CAP_CACHE_COHERENCY))  in a6xx_create_address_space()
2149 	mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);  in a6xx_create_private_address_space()
2164 	if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami)  in a6xx_get_rptr()
2165 		return a6xx_gpu->shadow[ring->id];  in a6xx_get_rptr()
2167 	return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR);  in a6xx_get_rptr()
2196 	progress = !!memcmp(&cp_state, &ring->last_cp_state, sizeof(cp_state));  in a6xx_progress()
2198 	ring->last_cp_state = cp_state;  in a6xx_progress()
2205 	if (!info->speedbins)  in fuse_to_supp_hw()
2208 	for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++)  in fuse_to_supp_hw()
2209 		if (info->speedbins[i].fuse == fuse)  in fuse_to_supp_hw()
2210 			return BIT(info->speedbins[i].speedbin);  in fuse_to_supp_hw()
2223 	 * -ENOENT means that the platform doesn't support speedbin which is  in a6xx_set_supported_hw()
2226 	if (ret == -ENOENT) {  in a6xx_set_supported_hw()
2230 			      "failed to read speed-bin. Some OPPs may not be supported by hardware\n");  in a6xx_set_supported_hw()
2238 			"missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",  in a6xx_set_supported_hw()
2312 	struct msm_drm_private *priv = dev->dev_private;  in a6xx_gpu_init()
2313 	struct platform_device *pdev = priv->gpu_pdev;  in a6xx_gpu_init()
2314 	struct adreno_platform_config *config = pdev->dev.platform_data;  in a6xx_gpu_init()
2323 		return ERR_PTR(-ENOMEM);  in a6xx_gpu_init()
2325 	adreno_gpu = &a6xx_gpu->base;  in a6xx_gpu_init()
2326 	gpu = &adreno_gpu->base;  in a6xx_gpu_init()
2328 	mutex_init(&a6xx_gpu->gmu.lock);  in a6xx_gpu_init()
2330 	adreno_gpu->registers = NULL;  in a6xx_gpu_init()
2332 	/* Check if there is a GMU phandle and set it up */  in a6xx_gpu_init()
2333 	node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);  in a6xx_gpu_init()
2337 	adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper");  in a6xx_gpu_init()
2339 	adreno_gpu->base.hw_apriv =  in a6xx_gpu_init()
2340 		!!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);  in a6xx_gpu_init()
2344 	ret = a6xx_set_supported_hw(&pdev->dev, config->info);  in a6xx_gpu_init()
2346 		a6xx_destroy(&(a6xx_gpu->base.base));  in a6xx_gpu_init()
2355 		a6xx_destroy(&(a6xx_gpu->base.base));  in a6xx_gpu_init()
2364 		priv->gpu_clamp_to_idle = true;  in a6xx_gpu_init()
2372 		a6xx_destroy(&(a6xx_gpu->base.base));  in a6xx_gpu_init()
2376 	if (gpu->aspace)  in a6xx_gpu_init()
2377 		msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,  in a6xx_gpu_init()