52 	TILE6_LINEAR = 0,
194 	DEPTH6_NONE = 0,
309 	PERF_CP_ALWAYS_COUNT = 0,
362 	PERF_RBBM_ALWAYS_COUNT = 0,
379 	PERF_PC_BUSY_CYCLES = 0,
424 	PERF_VFD_BUSY_CYCLES = 0,
450 	PERF_HLSQ_BUSY_CYCLES = 0,
474 	PERF_VPC_BUSY_CYCLES = 0,
505 	PERF_TSE_BUSY_CYCLES = 0,
528 	PERF_RAS_BUSY_CYCLES = 0,
544 	PERF_UCHE_BUSY_CYCLES = 0,
587 	PERF_TP_BUSY_CYCLES = 0,
647 	PERF_SP_BUSY_CYCLES = 0,
735 	PERF_RB_BUSY_CYCLES = 0,
786 	PERF_VSC_BUSY_CYCLES = 0,
794 	PERF_CCU_BUSY_CYCLES = 0,
826 	PERF_LRZ_BUSY_CYCLES = 0,
857 	PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
907 	R2D_RAW = 0,
911 	A6XX_EARLY_Z = 0,
918 	DIST_SCREEN_COORD = 0,
923 	NO_FLUSH = 0,
929 	TYPE_TILED = 0,
934 	LR_TB = 0,
941 	RENDERING_PASS = 0,
946 	BUFFERS_IN_GMEM = 0,
957 	FRAGCOORD_CENTER = 0,
962 	ROTATE_0 = 0,
971 	TESS_EQUAL = 0,
977 	TESS_POINTS = 0,
984 	THREAD64 = 0,
998 	A6XX_TEX_NEAREST = 0,
1005 	A6XX_TEX_REPEAT = 0,
1013 	A6XX_TEX_ANISO_1 = 0,
1021 	A6XX_REDUCTION_MODE_AVERAGE = 0,
1027 	A6XX_TEX_X = 0,
1036 	A6XX_TEX_1D = 0,
1043 #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE			0x00000001
1044 #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR			0x00000002
1045 #define A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0			0x00000010
1046 #define A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1			0x00000020
1047 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW	0x00000040
1048 #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR			0x00000080
1049 #define A6XX_RBBM_INT_0_MASK_CP_SW				0x00000100
1050 #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR			0x00000200
1051 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS		0x00000400
1052 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS		0x00000800
1053 #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS			0x00001000
1054 #define A6XX_RBBM_INT_0_MASK_CP_IB2				0x00002000
1055 #define A6XX_RBBM_INT_0_MASK_CP_IB1				0x00004000
1056 #define A6XX_RBBM_INT_0_MASK_CP_RB				0x00008000
1057 #define A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT			0x00008000
1058 #define A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC			0x00010000
1059 #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS			0x00020000
1060 #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS			0x00040000
1061 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS			0x00100000
1062 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC		0x00200000
1063 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW		0x00400000
1064 #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT			0x00800000
1065 #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS			0x01000000
1066 #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR			0x02000000
1067 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0			0x04000000
1068 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1			0x08000000
1069 #define A6XX_RBBM_INT_0_MASK_TSBWRITEERROR			0x10000000
1070 #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ			0x40000000
1071 #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG			0x80000000
1072 #define A6XX_CP_INT_CP_OPCODE_ERROR				0x00000001
1073 #define A6XX_CP_INT_CP_UCODE_ERROR				0x00000002
1074 #define A6XX_CP_INT_CP_HW_FAULT_ERROR				0x00000004
1075 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR		0x00000010
1076 #define A6XX_CP_INT_CP_AHB_ERROR				0x00000020
1077 #define A6XX_CP_INT_CP_VSD_PARITY_ERROR				0x00000040
1078 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR			0x00000080
1079 #define A6XX_CP_INT_CP_OPCODE_ERROR_LPAC			0x00000100
1080 #define A6XX_CP_INT_CP_UCODE_ERROR_LPAC				0x00000200
1081 #define A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC			0x00000400
1082 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC		0x00000800
1083 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC			0x00001000
1084 #define A6XX_CP_INT_CP_OPCODE_ERROR_BV				0x00002000
1085 #define A6XX_CP_INT_CP_UCODE_ERROR_BV				0x00004000
1086 #define A6XX_CP_INT_CP_HW_FAULT_ERROR_BV			0x00008000
1087 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV		0x00010000
1088 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV			0x00020000
1089 #define REG_A6XX_CP_RB_BASE					0x00000800
1091 #define REG_A6XX_CP_RB_CNTL					0x00000802
1093 #define REG_A6XX_CP_RB_RPTR_ADDR				0x00000804
1095 #define REG_A6XX_CP_RB_RPTR					0x00000806
1097 #define REG_A6XX_CP_RB_WPTR					0x00000807
1099 #define REG_A6XX_CP_SQE_CNTL					0x00000808
1101 #define REG_A6XX_CP_CP2GMU_STATUS				0x00000812
1102 #define A6XX_CP_CP2GMU_STATUS_IFPC				0x00000001
1104 #define REG_A6XX_CP_HW_FAULT					0x00000821
1106 #define REG_A6XX_CP_INTERRUPT_STATUS				0x00000823
1108 #define REG_A6XX_CP_PROTECT_STATUS				0x00000824
1110 #define REG_A6XX_CP_STATUS_1					0x00000825
1112 #define REG_A6XX_CP_SQE_INSTR_BASE				0x00000830
1114 #define REG_A6XX_CP_MISC_CNTL					0x00000840
1116 #define REG_A6XX_CP_APRIV_CNTL					0x00000844
1118 #define REG_A6XX_CP_PREEMPT_THRESHOLD				0x000008c0
1120 #define REG_A6XX_CP_ROQ_THRESHOLDS_1				0x000008c1
1121 #define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK		0x000000ff
1122 #define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT		0
1127 #define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK		0x0000ff00
1133 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK		0x00ff0000
1139 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK		0xff000000
1146 #define REG_A6XX_CP_ROQ_THRESHOLDS_2				0x000008c2
1147 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK		0x000001ff
1148 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT		0
1153 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK			0xffff0000
1160 #define REG_A6XX_CP_MEM_POOL_SIZE				0x000008c3
1162 #define REG_A6XX_CP_CHICKEN_DBG					0x00000841
1164 #define REG_A6XX_CP_ADDR_MODE_CNTL				0x00000842
1166 #define REG_A6XX_CP_DBG_ECO_CNTL				0x00000843
1168 #define REG_A6XX_CP_PROTECT_CNTL				0x0000084f
1169 #define A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE		0x00000008
1170 #define A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN		0x00000002
1171 #define A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN			0x00000001
1173 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }  in REG_A6XX_CP_SCRATCH()
1175 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }  in REG_A6XX_CP_SCRATCH_REG()
1177 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }  in REG_A6XX_CP_PROTECT()
1179 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }  in REG_A6XX_CP_PROTECT_REG()
1180 #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK			0x0003ffff
1181 #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT			0
1186 #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK			0x7ffc0000
1192 #define A6XX_CP_PROTECT_REG_READ				0x80000000
1194 #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL				0x000008a0
1196 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO			0x000008a1
1198 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR	0x000008a3
1200 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR	0x000008a5
1202 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR	0x000008a7
1204 #define REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS			0x000008ab
1206 static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; }  in REG_A6XX_CP_PERFCTR_CP_SEL()
1208 static inline uint32_t REG_A7XX_CP_BV_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008e0 + 0x1*i0; }  in REG_A7XX_CP_BV_PERFCTR_CP_SEL()
1210 #define REG_A6XX_CP_CRASH_SCRIPT_BASE				0x00000900
1212 #define REG_A6XX_CP_CRASH_DUMP_CNTL				0x00000902
1214 #define REG_A6XX_CP_CRASH_DUMP_STATUS				0x00000903
1216 #define REG_A6XX_CP_SQE_STAT_ADDR				0x00000908
1218 #define REG_A6XX_CP_SQE_STAT_DATA				0x00000909
1220 #define REG_A6XX_CP_DRAW_STATE_ADDR				0x0000090a
1222 #define REG_A6XX_CP_DRAW_STATE_DATA				0x0000090b
1224 #define REG_A6XX_CP_ROQ_DBG_ADDR				0x0000090c
1226 #define REG_A6XX_CP_ROQ_DBG_DATA				0x0000090d
1228 #define REG_A6XX_CP_MEM_POOL_DBG_ADDR				0x0000090e
1230 #define REG_A6XX_CP_MEM_POOL_DBG_DATA				0x0000090f
1232 #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR				0x00000910
1234 #define REG_A6XX_CP_SQE_UCODE_DBG_DATA				0x00000911
1236 #define REG_A6XX_CP_IB1_BASE					0x00000928
1238 #define REG_A6XX_CP_IB1_REM_SIZE				0x0000092a
1240 #define REG_A6XX_CP_IB2_BASE					0x0000092b
1242 #define REG_A6XX_CP_IB2_REM_SIZE				0x0000092d
1244 #define REG_A6XX_CP_SDS_BASE					0x0000092e
1246 #define REG_A6XX_CP_SDS_REM_SIZE				0x00000930
1248 #define REG_A6XX_CP_MRB_BASE					0x00000931
1250 #define REG_A6XX_CP_MRB_REM_SIZE				0x00000933
1252 #define REG_A6XX_CP_VSD_BASE					0x00000934
1254 #define REG_A6XX_CP_ROQ_RB_STAT					0x00000939
1255 #define A6XX_CP_ROQ_RB_STAT_RPTR__MASK				0x000003ff
1256 #define A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT				0
1261 #define A6XX_CP_ROQ_RB_STAT_WPTR__MASK				0x03ff0000
1268 #define REG_A6XX_CP_ROQ_IB1_STAT				0x0000093a
1269 #define A6XX_CP_ROQ_IB1_STAT_RPTR__MASK				0x000003ff
1270 #define A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT			0
1275 #define A6XX_CP_ROQ_IB1_STAT_WPTR__MASK				0x03ff0000
1282 #define REG_A6XX_CP_ROQ_IB2_STAT				0x0000093b
1283 #define A6XX_CP_ROQ_IB2_STAT_RPTR__MASK				0x000003ff
1284 #define A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT			0
1289 #define A6XX_CP_ROQ_IB2_STAT_WPTR__MASK				0x03ff0000
1296 #define REG_A6XX_CP_ROQ_SDS_STAT				0x0000093c
1297 #define A6XX_CP_ROQ_SDS_STAT_RPTR__MASK				0x000003ff
1298 #define A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT			0
1303 #define A6XX_CP_ROQ_SDS_STAT_WPTR__MASK				0x03ff0000
1310 #define REG_A6XX_CP_ROQ_MRB_STAT				0x0000093d
1311 #define A6XX_CP_ROQ_MRB_STAT_RPTR__MASK				0x000003ff
1312 #define A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT			0
1317 #define A6XX_CP_ROQ_MRB_STAT_WPTR__MASK				0x03ff0000
1324 #define REG_A6XX_CP_ROQ_VSD_STAT				0x0000093e
1325 #define A6XX_CP_ROQ_VSD_STAT_RPTR__MASK				0x000003ff
1326 #define A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT			0
1331 #define A6XX_CP_ROQ_VSD_STAT_WPTR__MASK				0x03ff0000
1338 #define REG_A6XX_CP_IB1_DWORDS					0x00000943
1340 #define REG_A6XX_CP_IB2_DWORDS					0x00000944
1342 #define REG_A6XX_CP_SDS_DWORDS					0x00000945
1344 #define REG_A6XX_CP_MRB_DWORDS					0x00000946
1346 #define REG_A6XX_CP_VSD_DWORDS					0x00000947
1348 #define REG_A6XX_CP_ROQ_AVAIL_RB				0x00000948
1349 #define A6XX_CP_ROQ_AVAIL_RB_REM__MASK				0xffff0000
1356 #define REG_A6XX_CP_ROQ_AVAIL_IB1				0x00000949
1357 #define A6XX_CP_ROQ_AVAIL_IB1_REM__MASK				0xffff0000
1364 #define REG_A6XX_CP_ROQ_AVAIL_IB2				0x0000094a
1365 #define A6XX_CP_ROQ_AVAIL_IB2_REM__MASK				0xffff0000
1372 #define REG_A6XX_CP_ROQ_AVAIL_SDS				0x0000094b
1373 #define A6XX_CP_ROQ_AVAIL_SDS_REM__MASK				0xffff0000
1380 #define REG_A6XX_CP_ROQ_AVAIL_MRB				0x0000094c
1381 #define A6XX_CP_ROQ_AVAIL_MRB_REM__MASK				0xffff0000
1388 #define REG_A6XX_CP_ROQ_AVAIL_VSD				0x0000094d
1389 #define A6XX_CP_ROQ_AVAIL_VSD_REM__MASK				0xffff0000
1396 #define REG_A6XX_CP_ALWAYS_ON_COUNTER				0x00000980
1398 #define REG_A6XX_CP_AHB_CNTL					0x0000098d
1400 #define REG_A6XX_CP_APERTURE_CNTL_HOST				0x00000a00
1402 #define REG_A6XX_CP_APERTURE_CNTL_CD				0x00000a03
1404 #define REG_A7XX_CP_BV_PROTECT_STATUS				0x00000a61
1406 #define REG_A7XX_CP_BV_HW_FAULT					0x00000a64
1408 #define REG_A7XX_CP_BV_DRAW_STATE_ADDR				0x00000a81
1410 #define REG_A7XX_CP_BV_DRAW_STATE_DATA				0x00000a82
1412 #define REG_A7XX_CP_BV_ROQ_DBG_ADDR				0x00000a83
1414 #define REG_A7XX_CP_BV_ROQ_DBG_DATA				0x00000a84
1416 #define REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR			0x00000a85
1418 #define REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA			0x00000a86
1420 #define REG_A7XX_CP_BV_SQE_STAT_ADDR				0x00000a87
1422 #define REG_A7XX_CP_BV_SQE_STAT_DATA				0x00000a88
1424 #define REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR			0x00000a96
1426 #define REG_A7XX_CP_BV_MEM_POOL_DBG_DATA			0x00000a97
1428 #define REG_A7XX_CP_BV_RB_RPTR_ADDR				0x00000a98
1430 #define REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR			0x00000a9a
1432 #define REG_A7XX_CP_RESOURCE_TBL_DBG_DATA			0x00000a9b
1434 #define REG_A7XX_CP_BV_APRIV_CNTL				0x00000ad0
1436 #define REG_A7XX_CP_BV_CHICKEN_DBG				0x00000ada
1438 #define REG_A7XX_CP_LPAC_DRAW_STATE_ADDR			0x00000b0a
1440 #define REG_A7XX_CP_LPAC_DRAW_STATE_DATA			0x00000b0b
1442 #define REG_A7XX_CP_LPAC_ROQ_DBG_ADDR				0x00000b0c
1444 #define REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR			0x00000b27
1446 #define REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA			0x00000b28
1448 #define REG_A7XX_CP_SQE_AC_STAT_ADDR				0x00000b29
1450 #define REG_A7XX_CP_SQE_AC_STAT_DATA				0x00000b2a
1452 #define REG_A7XX_CP_LPAC_APRIV_CNTL				0x00000b31
1454 #define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE				0x00000b34
1456 #define REG_A7XX_CP_LPAC_ROQ_DBG_DATA				0x00000b35
1458 #define REG_A7XX_CP_LPAC_FIFO_DBG_DATA				0x00000b36
1460 #define REG_A7XX_CP_LPAC_FIFO_DBG_ADDR				0x00000b40
1462 #define REG_A6XX_CP_LPAC_SQE_INSTR_BASE				0x00000b82
1464 #define REG_A6XX_VSC_ADDR_MODE_CNTL				0x00000c01
1466 #define REG_A6XX_RBBM_GPR0_CNTL					0x00000018
1468 #define REG_A6XX_RBBM_INT_0_STATUS				0x00000201
1470 #define REG_A6XX_RBBM_STATUS					0x00000210
1471 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB			0x00800000
1472 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP			0x00400000
1473 #define A6XX_RBBM_STATUS_HLSQ_BUSY				0x00200000
1474 #define A6XX_RBBM_STATUS_VSC_BUSY				0x00100000
1475 #define A6XX_RBBM_STATUS_TPL1_BUSY				0x00080000
1476 #define A6XX_RBBM_STATUS_SP_BUSY				0x00040000
1477 #define A6XX_RBBM_STATUS_UCHE_BUSY				0x00020000
1478 #define A6XX_RBBM_STATUS_VPC_BUSY				0x00010000
1479 #define A6XX_RBBM_STATUS_VFD_BUSY				0x00008000
1480 #define A6XX_RBBM_STATUS_TESS_BUSY				0x00004000
1481 #define A6XX_RBBM_STATUS_PC_VSD_BUSY				0x00002000
1482 #define A6XX_RBBM_STATUS_PC_DCALL_BUSY				0x00001000
1483 #define A6XX_RBBM_STATUS_COM_DCOM_BUSY				0x00000800
1484 #define A6XX_RBBM_STATUS_LRZ_BUSY				0x00000400
1485 #define A6XX_RBBM_STATUS_A2D_BUSY				0x00000200
1486 #define A6XX_RBBM_STATUS_CCU_BUSY				0x00000100
1487 #define A6XX_RBBM_STATUS_RB_BUSY				0x00000080
1488 #define A6XX_RBBM_STATUS_RAS_BUSY				0x00000040
1489 #define A6XX_RBBM_STATUS_TSE_BUSY				0x00000020
1490 #define A6XX_RBBM_STATUS_VBIF_BUSY				0x00000010
1491 #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY				0x00000008
1492 #define A6XX_RBBM_STATUS_CP_BUSY				0x00000004
1493 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER			0x00000002
1494 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER			0x00000001
1496 #define REG_A6XX_RBBM_STATUS1					0x00000211
1498 #define REG_A6XX_RBBM_STATUS2					0x00000212
1500 #define REG_A6XX_RBBM_STATUS3					0x00000213
1501 #define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT			0x01000000
1503 #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS			0x00000215
1505 #define REG_A7XX_RBBM_CLOCK_MODE_CP				0x00000260
1507 #define REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ				0x00000284
1509 #define REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS			0x00000285
1511 #define REG_A7XX_RBBM_CLOCK_MODE2_GRAS				0x00000286
1513 #define REG_A7XX_RBBM_CLOCK_MODE_BV_VFD				0x00000287
1515 #define REG_A7XX_RBBM_CLOCK_MODE_BV_GPC				0x00000288
1517 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_CP()
1519 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_RBBM()
1521 static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_PC()
1523 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_VFD()
1525 static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_HLSQ()
1527 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_VPC()
1529 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_CCU()
1531 static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_TSE()
1533 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_RAS()
1535 static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_UCHE()
1537 static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_TP()
1539 static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_SP()
1541 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_RB()
1543 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_VSC()
1545 static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_LRZ()
1547 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_CMP()
1549 static inline uint32_t REG_A7XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000300 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_CP()
1551 static inline uint32_t REG_A7XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000031c + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_RBBM()
1553 static inline uint32_t REG_A7XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000324 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_PC()
1555 static inline uint32_t REG_A7XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000334 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_VFD()
1557 static inline uint32_t REG_A7XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000344 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_HLSQ()
1559 static inline uint32_t REG_A7XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000350 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_VPC()
1561 static inline uint32_t REG_A7XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000035c + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_CCU()
1563 static inline uint32_t REG_A7XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000366 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_TSE()
1565 static inline uint32_t REG_A7XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000036e + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_RAS()
1567 static inline uint32_t REG_A7XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000376 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_UCHE()
1569 static inline uint32_t REG_A7XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000038e + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_TP()
1571 static inline uint32_t REG_A7XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000003a6 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_SP()
1573 static inline uint32_t REG_A7XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000003d6 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_RB()
1575 static inline uint32_t REG_A7XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000003e6 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_VSC()
1577 static inline uint32_t REG_A7XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000003ea + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_LRZ()
1579 static inline uint32_t REG_A7XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000003f2 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_CMP()
1581 static inline uint32_t REG_A7XX_RBBM_PERFCTR_UFC(uint32_t i0) { return 0x000003fa + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_UFC()
1583 static inline uint32_t REG_A7XX_RBBM_PERFCTR2_HLSQ(uint32_t i0) { return 0x00000410 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR2_HLSQ()
1585 static inline uint32_t REG_A7XX_RBBM_PERFCTR2_CP(uint32_t i0) { return 0x0000041c + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR2_CP()
1587 static inline uint32_t REG_A7XX_RBBM_PERFCTR2_SP(uint32_t i0) { return 0x0000042a + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR2_SP()
1589 static inline uint32_t REG_A7XX_RBBM_PERFCTR2_TP(uint32_t i0) { return 0x00000442 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR2_TP()
1591 static inline uint32_t REG_A7XX_RBBM_PERFCTR2_UFC(uint32_t i0) { return 0x0000044e + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR2_UFC()
1593 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_PC(uint32_t i0) { return 0x00000460 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_BV_PC()
1595 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_VFD(uint32_t i0) { return 0x00000470 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_BV_VFD()
1597 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_VPC(uint32_t i0) { return 0x00000480 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_BV_VPC()
1599 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_TSE(uint32_t i0) { return 0x0000048c + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_BV_TSE()
1601 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_RAS(uint32_t i0) { return 0x00000494 + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_BV_RAS()
1603 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_LRZ(uint32_t i0) { return 0x0000049c + 0x2*i0; }  in REG_A7XX_RBBM_PERFCTR_BV_LRZ()
1605 #define REG_A6XX_RBBM_PERFCTR_CNTL				0x00000500
1607 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0				0x00000501
1609 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1				0x00000502
1611 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2				0x00000503
1613 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3				0x00000504
1615 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO			0x00000505
1617 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI			0x00000506
1619 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; }  in REG_A6XX_RBBM_PERFCTR_RBBM_SEL()
1621 #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED			0x0000050b
1623 #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD			0x0000050e
1625 #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS			0x0000050f
1627 #define REG_A6XX_RBBM_ISDB_CNT					0x00000533
1629 #define REG_A7XX_RBBM_NC_MODE_CNTL				0x00000534
1631 #define REG_A7XX_RBBM_SNAPSHOT_STATUS				0x00000535
1633 #define REG_A6XX_RBBM_PRIMCTR_0_LO				0x00000540
1635 #define REG_A6XX_RBBM_PRIMCTR_0_HI				0x00000541
1637 #define REG_A6XX_RBBM_PRIMCTR_1_LO				0x00000542
1639 #define REG_A6XX_RBBM_PRIMCTR_1_HI				0x00000543
1641 #define REG_A6XX_RBBM_PRIMCTR_2_LO				0x00000544
1643 #define REG_A6XX_RBBM_PRIMCTR_2_HI				0x00000545
1645 #define REG_A6XX_RBBM_PRIMCTR_3_LO				0x00000546
1647 #define REG_A6XX_RBBM_PRIMCTR_3_HI				0x00000547
1649 #define REG_A6XX_RBBM_PRIMCTR_4_LO				0x00000548
1651 #define REG_A6XX_RBBM_PRIMCTR_4_HI				0x00000549
1653 #define REG_A6XX_RBBM_PRIMCTR_5_LO				0x0000054a
1655 #define REG_A6XX_RBBM_PRIMCTR_5_HI				0x0000054b
1657 #define REG_A6XX_RBBM_PRIMCTR_6_LO				0x0000054c
1659 #define REG_A6XX_RBBM_PRIMCTR_6_HI				0x0000054d
1661 #define REG_A6XX_RBBM_PRIMCTR_7_LO				0x0000054e
1663 #define REG_A6XX_RBBM_PRIMCTR_7_HI				0x0000054f
1665 #define REG_A6XX_RBBM_PRIMCTR_8_LO				0x00000550
1667 #define REG_A6XX_RBBM_PRIMCTR_8_HI				0x00000551
1669 #define REG_A6XX_RBBM_PRIMCTR_9_LO				0x00000552
1671 #define REG_A6XX_RBBM_PRIMCTR_9_HI				0x00000553
1673 #define REG_A6XX_RBBM_PRIMCTR_10_LO				0x00000554
1675 #define REG_A6XX_RBBM_PRIMCTR_10_HI				0x00000555
1677 #define REG_A6XX_RBBM_SECVID_TRUST_CNTL				0x0000f400
1679 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE			0x0000f800
1681 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE			0x0000f802
1683 #define REG_A6XX_RBBM_SECVID_TSB_CNTL				0x0000f803
1685 #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL			0x0000f810
1687 #define REG_A7XX_RBBM_SECVID_TSB_STATUS				0x0000fc00
1689 #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL			0x00000010
1691 #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL			0x00000011
1693 #define REG_A6XX_RBBM_GBIF_HALT					0x00000016
1695 #define REG_A6XX_RBBM_GBIF_HALT_ACK				0x00000017
1697 #define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD			0x0000001c
1698 #define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE		0x00000001
1700 #define REG_A7XX_RBBM_GBIF_HALT					0x00000016
1702 #define REG_A7XX_RBBM_GBIF_HALT_ACK				0x00000017
1704 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL			0x0000001f
1706 #define REG_A6XX_RBBM_INT_CLEAR_CMD				0x00000037
1708 #define REG_A6XX_RBBM_INT_0_MASK				0x00000038
1710 #define REG_A7XX_RBBM_INT_2_MASK				0x0000003a
1712 #define REG_A6XX_RBBM_SP_HYST_CNT				0x00000042
1714 #define REG_A6XX_RBBM_SW_RESET_CMD				0x00000043
1716 #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT				0x00000044
1718 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD			0x00000045
1720 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2			0x00000046
1722 #define REG_A6XX_RBBM_CLOCK_CNTL				0x000000ae
1724 #define REG_A6XX_RBBM_CLOCK_CNTL_SP0				0x000000b0
1726 #define REG_A6XX_RBBM_CLOCK_CNTL_SP1				0x000000b1
1728 #define REG_A6XX_RBBM_CLOCK_CNTL_SP2				0x000000b2
1730 #define REG_A6XX_RBBM_CLOCK_CNTL_SP3				0x000000b3
1732 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0				0x000000b4
1734 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1				0x000000b5
1736 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2				0x000000b6
1738 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3				0x000000b7
1740 #define REG_A6XX_RBBM_CLOCK_DELAY_SP0				0x000000b8
1742 #define REG_A6XX_RBBM_CLOCK_DELAY_SP1				0x000000b9
1744 #define REG_A6XX_RBBM_CLOCK_DELAY_SP2				0x000000ba
1746 #define REG_A6XX_RBBM_CLOCK_DELAY_SP3				0x000000bb
1748 #define REG_A6XX_RBBM_CLOCK_HYST_SP0				0x000000bc
1750 #define REG_A6XX_RBBM_CLOCK_HYST_SP1				0x000000bd
1752 #define REG_A6XX_RBBM_CLOCK_HYST_SP2				0x000000be
1754 #define REG_A6XX_RBBM_CLOCK_HYST_SP3				0x000000bf
1756 #define REG_A6XX_RBBM_CLOCK_CNTL_TP0				0x000000c0
1758 #define REG_A6XX_RBBM_CLOCK_CNTL_TP1				0x000000c1
1760 #define REG_A6XX_RBBM_CLOCK_CNTL_TP2				0x000000c2
1762 #define REG_A6XX_RBBM_CLOCK_CNTL_TP3				0x000000c3
1764 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0				0x000000c4
1766 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1				0x000000c5
1768 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2				0x000000c6
1770 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3				0x000000c7
1772 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0				0x000000c8
1774 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1				0x000000c9
1776 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2				0x000000ca
1778 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3				0x000000cb
1780 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0				0x000000cc
1782 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1				0x000000cd
1784 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2				0x000000ce
1786 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3				0x000000cf
1788 #define REG_A6XX_RBBM_CLOCK_DELAY_TP0				0x000000d0
1790 #define REG_A6XX_RBBM_CLOCK_DELAY_TP1				0x000000d1
1792 #define REG_A6XX_RBBM_CLOCK_DELAY_TP2				0x000000d2
1794 #define REG_A6XX_RBBM_CLOCK_DELAY_TP3				0x000000d3
1796 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0				0x000000d4
1798 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1				0x000000d5
1800 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2				0x000000d6
1802 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3				0x000000d7
1804 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0				0x000000d8
1806 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1				0x000000d9
1808 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2				0x000000da
1810 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3				0x000000db
1812 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0				0x000000dc
1814 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1				0x000000dd
1816 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2				0x000000de
1818 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3				0x000000df
1820 #define REG_A6XX_RBBM_CLOCK_HYST_TP0				0x000000e0
1822 #define REG_A6XX_RBBM_CLOCK_HYST_TP1				0x000000e1
1824 #define REG_A6XX_RBBM_CLOCK_HYST_TP2				0x000000e2
1826 #define REG_A6XX_RBBM_CLOCK_HYST_TP3				0x000000e3
1828 #define REG_A6XX_RBBM_CLOCK_HYST2_TP0				0x000000e4
1830 #define REG_A6XX_RBBM_CLOCK_HYST2_TP1				0x000000e5
1832 #define REG_A6XX_RBBM_CLOCK_HYST2_TP2				0x000000e6
1834 #define REG_A6XX_RBBM_CLOCK_HYST2_TP3				0x000000e7
1836 #define REG_A6XX_RBBM_CLOCK_HYST3_TP0				0x000000e8
1838 #define REG_A6XX_RBBM_CLOCK_HYST3_TP1				0x000000e9
1840 #define REG_A6XX_RBBM_CLOCK_HYST3_TP2				0x000000ea
1842 #define REG_A6XX_RBBM_CLOCK_HYST3_TP3				0x000000eb
1844 #define REG_A6XX_RBBM_CLOCK_HYST4_TP0				0x000000ec
1846 #define REG_A6XX_RBBM_CLOCK_HYST4_TP1				0x000000ed
1848 #define REG_A6XX_RBBM_CLOCK_HYST4_TP2				0x000000ee
1850 #define REG_A6XX_RBBM_CLOCK_HYST4_TP3				0x000000ef
1852 #define REG_A6XX_RBBM_CLOCK_CNTL_RB0				0x000000f0
1854 #define REG_A6XX_RBBM_CLOCK_CNTL_RB1				0x000000f1
1856 #define REG_A6XX_RBBM_CLOCK_CNTL_RB2				0x000000f2
1858 #define REG_A6XX_RBBM_CLOCK_CNTL_RB3				0x000000f3
1860 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0				0x000000f4
1862 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1				0x000000f5
1864 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2				0x000000f6
1866 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3				0x000000f7
1868 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0				0x000000f8
1870 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1				0x000000f9
1872 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2				0x000000fa
1874 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3				0x000000fb
1876 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0			0x00000100
1878 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1			0x00000101
1880 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2			0x00000102
1882 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3			0x00000103
1884 #define REG_A6XX_RBBM_CLOCK_CNTL_RAC				0x00000104
1886 #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC				0x00000105
1888 #define REG_A6XX_RBBM_CLOCK_DELAY_RAC				0x00000106
1890 #define REG_A6XX_RBBM_CLOCK_HYST_RAC				0x00000107
1892 #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM			0x00000108
1894 #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM			0x00000109
1896 #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM			0x0000010a
1898 #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE				0x0000010b
1900 #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE				0x0000010c
1902 #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE				0x0000010d
1904 #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE				0x0000010e
1906 #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE				0x0000010f
1908 #define REG_A6XX_RBBM_CLOCK_HYST_UCHE				0x00000110
1910 #define REG_A6XX_RBBM_CLOCK_MODE_VFD				0x00000111
1912 #define REG_A6XX_RBBM_CLOCK_DELAY_VFD				0x00000112
1914 #define REG_A6XX_RBBM_CLOCK_HYST_VFD				0x00000113
1916 #define REG_A6XX_RBBM_CLOCK_MODE_GPC				0x00000114
1918 #define REG_A6XX_RBBM_CLOCK_DELAY_GPC				0x00000115
1920 #define REG_A6XX_RBBM_CLOCK_HYST_GPC				0x00000116
1922 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2			0x00000117
1924 #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX				0x00000118
1926 #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX			0x00000119
1928 #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX				0x0000011a
1930 #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ				0x0000011b
1932 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ				0x0000011c
1934 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ				0x0000011d
1936 #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE			0x00000120
1938 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE			0x00000121
1940 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE			0x00000122
1942 #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL			0x000005ff
1944 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A				0x00000600
1946 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B				0x00000601
1948 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C				0x00000602
1950 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D				0x00000603
1951 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK		0x000000ff
1952 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT		0
1957 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK		0x0000ff00
1964 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT				0x00000604
1965 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK		0x0000003f
1966 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT		0
1971 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK			0x00007000
1977 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK			0xf0000000
1984 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM				0x00000605
1985 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK			0x0f000000
1992 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0				0x00000608
1994 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1				0x00000609
1996 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2				0x0000060a
1998 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3				0x0000060b
2000 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0			0x0000060c
2002 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1			0x0000060d
2004 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2			0x0000060e
2006 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3			0x0000060f
2008 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0			0x00000610
2009 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK		0x0000000f
2010 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT		0
2015 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK		0x000000f0
2021 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK		0x00000f00
2027 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK		0x0000f000
2033 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK		0x000f0000
2039 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK		0x00f00000
2045 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK		0x0f000000
2051 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK		0xf0000000
2058 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1			0x00000611
2059 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK		0x0000000f
2060 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT		0
2065 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK		0x000000f0
2071 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK		0x00000f00
2077 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK		0x0000f000
2083 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK		0x000f0000
2089 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK		0x00f00000
2095 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK		0x0f000000
2101 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK		0xf0000000
2108 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1			0x0000062f
2110 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2			0x00000630
2112 static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; }  in REG_A6XX_VSC_PERFCTR_VSC_SEL()
2114 #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE			0x0000c800
2116 #define REG_A6XX_HLSQ_DBG_READ_SEL				0x0000d000
2118 #define REG_A6XX_UCHE_ADDR_MODE_CNTL				0x00000e00
2120 #define REG_A6XX_UCHE_MODE_CNTL					0x00000e01
2122 #define REG_A6XX_UCHE_WRITE_RANGE_MAX				0x00000e05
2124 #define REG_A6XX_UCHE_WRITE_THRU_BASE				0x00000e07
2126 #define REG_A6XX_UCHE_TRAP_BASE					0x00000e09
2128 #define REG_A6XX_UCHE_GMEM_RANGE_MIN				0x00000e0b
2130 #define REG_A6XX_UCHE_GMEM_RANGE_MAX				0x00000e0d
2132 #define REG_A6XX_UCHE_CACHE_WAYS				0x00000e17
2134 #define REG_A6XX_UCHE_FILTER_CNTL				0x00000e18
2136 #define REG_A6XX_UCHE_CLIENT_PF					0x00000e19
2137 #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK			0x000000ff
2138 #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT			0
2144 static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; }  in REG_A6XX_UCHE_PERFCTR_UCHE_SEL()
2146 #define REG_A6XX_UCHE_GBIF_GX_CONFIG				0x00000e3a
2148 #define REG_A6XX_UCHE_CMDQ_CONFIG				0x00000e3c
2150 #define REG_A6XX_VBIF_VERSION					0x00003000
2152 #define REG_A6XX_VBIF_CLKON					0x00003001
2153 #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS			0x00000002
2155 #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN				0x0000302a
2157 #define REG_A6XX_VBIF_XIN_HALT_CTRL0				0x00003080
2159 #define REG_A6XX_VBIF_XIN_HALT_CTRL1				0x00003081
2161 #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL				0x00003084
2163 #define REG_A6XX_VBIF_TEST_BUS1_CTRL0				0x00003085
2165 #define REG_A6XX_VBIF_TEST_BUS1_CTRL1				0x00003086
2166 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK		0x0000000f
2167 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT		0
2173 #define REG_A6XX_VBIF_TEST_BUS2_CTRL0				0x00003087
2175 #define REG_A6XX_VBIF_TEST_BUS2_CTRL1				0x00003088
2176 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK		0x000001ff
2177 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT		0
2183 #define REG_A6XX_VBIF_TEST_BUS_OUT				0x0000308c
2185 #define REG_A6XX_VBIF_PERF_CNT_SEL0				0x000030d0
2187 #define REG_A6XX_VBIF_PERF_CNT_SEL1				0x000030d1
2189 #define REG_A6XX_VBIF_PERF_CNT_SEL2				0x000030d2
2191 #define REG_A6XX_VBIF_PERF_CNT_SEL3				0x000030d3
2193 #define REG_A6XX_VBIF_PERF_CNT_LOW0				0x000030d8
2195 #define REG_A6XX_VBIF_PERF_CNT_LOW1				0x000030d9
2197 #define REG_A6XX_VBIF_PERF_CNT_LOW2				0x000030da
2199 #define REG_A6XX_VBIF_PERF_CNT_LOW3				0x000030db
2201 #define REG_A6XX_VBIF_PERF_CNT_HIGH0				0x000030e0
2203 #define REG_A6XX_VBIF_PERF_CNT_HIGH1				0x000030e1
2205 #define REG_A6XX_VBIF_PERF_CNT_HIGH2				0x000030e2
2207 #define REG_A6XX_VBIF_PERF_CNT_HIGH3				0x000030e3
2209 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0				0x00003100
2211 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1				0x00003101
2213 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2				0x00003102
2215 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0				0x00003110
2217 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1				0x00003111
2219 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2				0x00003112
2221 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0			0x00003118
2223 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1			0x00003119
2225 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2			0x0000311a
2227 #define REG_A6XX_GBIF_SCACHE_CNTL0				0x00003c01
2229 #define REG_A6XX_GBIF_SCACHE_CNTL1				0x00003c02
2231 #define REG_A6XX_GBIF_QSB_SIDE0					0x00003c03
2233 #define REG_A6XX_GBIF_QSB_SIDE1					0x00003c04
2235 #define REG_A6XX_GBIF_QSB_SIDE2					0x00003c05
2237 #define REG_A6XX_GBIF_QSB_SIDE3					0x00003c06
2239 #define REG_A6XX_GBIF_HALT					0x00003c45
2241 #define REG_A6XX_GBIF_HALT_ACK					0x00003c46
2243 #define REG_A6XX_GBIF_PERF_PWR_CNT_EN				0x00003cc0
2245 #define REG_A6XX_GBIF_PERF_PWR_CNT_CLR				0x00003cc1
2247 #define REG_A6XX_GBIF_PERF_CNT_SEL				0x00003cc2
2249 #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL				0x00003cc3
2251 #define REG_A6XX_GBIF_PERF_CNT_LOW0				0x00003cc4
2253 #define REG_A6XX_GBIF_PERF_CNT_LOW1				0x00003cc5
2255 #define REG_A6XX_GBIF_PERF_CNT_LOW2				0x00003cc6
2257 #define REG_A6XX_GBIF_PERF_CNT_LOW3				0x00003cc7
2259 #define REG_A6XX_GBIF_PERF_CNT_HIGH0				0x00003cc8
2261 #define REG_A6XX_GBIF_PERF_CNT_HIGH1				0x00003cc9
2263 #define REG_A6XX_GBIF_PERF_CNT_HIGH2				0x00003cca
2265 #define REG_A6XX_GBIF_PERF_CNT_HIGH3				0x00003ccb
2267 #define REG_A6XX_GBIF_PWR_CNT_LOW0				0x00003ccc
2269 #define REG_A6XX_GBIF_PWR_CNT_LOW1				0x00003ccd
2271 #define REG_A6XX_GBIF_PWR_CNT_LOW2				0x00003cce
2273 #define REG_A6XX_GBIF_PWR_CNT_HIGH0				0x00003ccf
2275 #define REG_A6XX_GBIF_PWR_CNT_HIGH1				0x00003cd0
2277 #define REG_A6XX_GBIF_PWR_CNT_HIGH2				0x00003cd1
2279 #define REG_A6XX_VSC_DBG_ECO_CNTL				0x00000c00
2281 #define REG_A6XX_VSC_BIN_SIZE					0x00000c02
2282 #define A6XX_VSC_BIN_SIZE_WIDTH__MASK				0x000000ff
2283 #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT				0
2288 #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK				0x0001ff00
2295 #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS			0x00000c03
2297 #define REG_A6XX_VSC_BIN_COUNT					0x00000c06
2298 #define A6XX_VSC_BIN_COUNT_NX__MASK				0x000007fe
2304 #define A6XX_VSC_BIN_COUNT_NY__MASK				0x001ff800
2311 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }  in REG_A6XX_VSC_PIPE_CONFIG()
2313 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }  in REG_A6XX_VSC_PIPE_CONFIG_REG()
2314 #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK			0x000003ff
2315 #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT			0
2320 #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK			0x000ffc00
2326 #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK			0x03f00000
2332 #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK			0xfc000000
2339 #define REG_A6XX_VSC_PRIM_STRM_ADDRESS				0x00000c30
2341 #define REG_A6XX_VSC_PRIM_STRM_PITCH				0x00000c32
2343 #define REG_A6XX_VSC_PRIM_STRM_LIMIT				0x00000c33
2345 #define REG_A6XX_VSC_DRAW_STRM_ADDRESS				0x00000c34
2347 #define REG_A6XX_VSC_DRAW_STRM_PITCH				0x00000c36
2349 #define REG_A6XX_VSC_DRAW_STRM_LIMIT				0x00000c37
2351 static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; }  in REG_A6XX_VSC_STATE()
2353 static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; }  in REG_A6XX_VSC_STATE_REG()
2355 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; }  in REG_A6XX_VSC_PRIM_STRM_SIZE()
2357 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; }  in REG_A6XX_VSC_PRIM_STRM_SIZE_REG()
2359 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }  in REG_A6XX_VSC_DRAW_STRM_SIZE()
2361 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }  in REG_A6XX_VSC_DRAW_STRM_SIZE_REG()
2363 #define REG_A6XX_UCHE_UNKNOWN_0E12				0x00000e12
2365 #define REG_A6XX_GRAS_CL_CNTL					0x00008000
2366 #define A6XX_GRAS_CL_CNTL_CLIP_DISABLE				0x00000001
2367 #define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE			0x00000002
2368 #define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE			0x00000004
2369 #define A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE			0x00000020
2370 #define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z			0x00000040
2371 #define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE			0x00000080
2372 #define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE			0x00000100
2373 #define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE		0x00000200
2375 #define REG_A6XX_GRAS_VS_CL_CNTL				0x00008001
2376 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
2377 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT			0
2382 #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
2389 #define REG_A6XX_GRAS_DS_CL_CNTL				0x00008002
2390 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
2391 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT			0
2396 #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
2403 #define REG_A6XX_GRAS_GS_CL_CNTL				0x00008003
2404 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
2405 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT			0
2410 #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
2417 #define REG_A6XX_GRAS_MAX_LAYER_INDEX				0x00008004
2419 #define REG_A6XX_GRAS_CNTL					0x00008005
2420 #define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL				0x00000001
2421 #define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID			0x00000002
2422 #define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE				0x00000004
2423 #define A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL				0x00000008
2424 #define A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID			0x00000010
2425 #define A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE				0x00000020
2426 #define A6XX_GRAS_CNTL_COORD_MASK__MASK				0x000003c0
2433 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ			0x00008006
2434 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK		0x000001ff
2435 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT		0
2440 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK		0x0007fc00
2447 static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT()
2449 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_XOFFSET()
2450 #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK			0xffffffff
2451 #define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT			0
2457 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_XSCALE()
2458 #define A6XX_GRAS_CL_VPORT_XSCALE__MASK				0xffffffff
2459 #define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT			0
2465 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_YOFFSET()
2466 #define A6XX_GRAS_CL_VPORT_YOFFSET__MASK			0xffffffff
2467 #define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT			0
2473 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_YSCALE()
2474 #define A6XX_GRAS_CL_VPORT_YSCALE__MASK				0xffffffff
2475 #define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT			0
2481 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_ZOFFSET()
2482 #define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK			0xffffffff
2483 #define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT			0
2489 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_ZSCALE()
2490 #define A6XX_GRAS_CL_VPORT_ZSCALE__MASK				0xffffffff
2491 #define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT			0
2497 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; }  in REG_A6XX_GRAS_CL_Z_CLAMP()
2499 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; }  in REG_A6XX_GRAS_CL_Z_CLAMP_MIN()
2500 #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK				0xffffffff
2501 #define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT				0
2507 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; }  in REG_A6XX_GRAS_CL_Z_CLAMP_MAX()
2508 #define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK				0xffffffff
2509 #define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT				0
2515 #define REG_A6XX_GRAS_SU_CNTL					0x00008090
2516 #define A6XX_GRAS_SU_CNTL_CULL_FRONT				0x00000001
2517 #define A6XX_GRAS_SU_CNTL_CULL_BACK				0x00000002
2518 #define A6XX_GRAS_SU_CNTL_FRONT_CW				0x00000004
2519 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK			0x000007f8
2525 #define A6XX_GRAS_SU_CNTL_POLY_OFFSET				0x00000800
2526 #define A6XX_GRAS_SU_CNTL_UNK12__MASK				0x00001000
2532 #define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK			0x00002000
2538 #define A6XX_GRAS_SU_CNTL_UNK15__MASK				0x00018000
2544 #define A6XX_GRAS_SU_CNTL_UNK17					0x00020000
2545 #define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE			0x00040000
2546 #define A6XX_GRAS_SU_CNTL_UNK19__MASK				0x00780000
2553 #define REG_A6XX_GRAS_SU_POINT_MINMAX				0x00008091
2554 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK			0x0000ffff
2555 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT			0
2560 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK			0xffff0000
2567 #define REG_A6XX_GRAS_SU_POINT_SIZE				0x00008092
2568 #define A6XX_GRAS_SU_POINT_SIZE__MASK				0x0000ffff
2569 #define A6XX_GRAS_SU_POINT_SIZE__SHIFT				0
2575 #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL			0x00008094
2576 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK		0x00000003
2577 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT		0
2583 #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE			0x00008095
2584 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK			0xffffffff
2585 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT			0
2591 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET			0x00008096
2592 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK			0xffffffff
2593 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT			0
2599 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP		0x00008097
2600 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK		0xffffffff
2601 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT		0
2607 #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO			0x00008098
2608 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK	0x00000007
2609 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT	0
2614 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK		0x00000008
2621 #define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL			0x00008099
2622 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN	0x00000001
2623 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK	0x00000006
2629 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN	0x00000008
2630 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK		0x00000030
2637 #define REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL			0x0000809a
2638 #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0			0x00000001
2639 #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN		0x00000002
2641 #define REG_A6XX_GRAS_VS_LAYER_CNTL				0x0000809b
2642 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER			0x00000001
2643 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW			0x00000002
2645 #define REG_A6XX_GRAS_GS_LAYER_CNTL				0x0000809c
2646 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER			0x00000001
2647 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW			0x00000002
2649 #define REG_A6XX_GRAS_DS_LAYER_CNTL				0x0000809d
2650 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER			0x00000001
2651 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW			0x00000002
2653 #define REG_A6XX_GRAS_SC_CNTL					0x000080a0
2654 #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK		0x00000007
2655 #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT		0
2660 #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK		0x00000018
2666 #define A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK			0x00000020
2672 #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK		0x000000c0
2678 #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK	0x00000100
2684 #define A6XX_GRAS_SC_CNTL_UNK9					0x00000200
2685 #define A6XX_GRAS_SC_CNTL_ROTATION__MASK			0x00000c00
2691 #define A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN				0x00001000
2693 #define REG_A6XX_GRAS_BIN_CONTROL				0x000080a1
2694 #define A6XX_GRAS_BIN_CONTROL_BINW__MASK			0x0000003f
2695 #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT			0
2700 #define A6XX_GRAS_BIN_CONTROL_BINH__MASK			0x00007f00
2706 #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK			0x001c0000
2712 #define A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS		0x00200000
2713 #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK		0x00c00000
2719 #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK	0x07000000
2725 #define A6XX_GRAS_BIN_CONTROL_UNK27__MASK			0x08000000
2732 #define REG_A6XX_GRAS_RAS_MSAA_CNTL				0x000080a2
2733 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
2734 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT			0
2739 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK			0x00000004
2745 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK			0x00000008
2752 #define REG_A6XX_GRAS_DEST_MSAA_CNTL				0x000080a3
2753 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK			0x00000003
2754 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT			0
2759 #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004
2761 #define REG_A6XX_GRAS_SAMPLE_CONFIG				0x000080a4
2762 #define A6XX_GRAS_SAMPLE_CONFIG_UNK0				0x00000001
2763 #define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE			0x00000002
2765 #define REG_A6XX_GRAS_SAMPLE_LOCATION_0				0x000080a5
2766 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK		0x0000000f
2767 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT		0
2772 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK		0x000000f0
2778 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK		0x00000f00
2784 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK		0x0000f000
2790 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK		0x000f0000
2796 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK		0x00f00000
2802 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK		0x0f000000
2808 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK		0xf0000000
2815 #define REG_A6XX_GRAS_SAMPLE_LOCATION_1				0x000080a6
2816 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK		0x0000000f
2817 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT		0
2822 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK		0x000000f0
2828 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK		0x00000f00
2834 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK		0x0000f000
2840 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK		0x000f0000
2846 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK		0x00f00000
2852 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK		0x0f000000
2858 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK		0xf0000000
2865 #define REG_A6XX_GRAS_UNKNOWN_80AF				0x000080af
2867 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; }  in REG_A6XX_GRAS_SC_SCREEN_SCISSOR()
2869 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0…  in REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL()
2870 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK			0x0000ffff
2871 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT			0
2876 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK			0xffff0000
2883 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0…  in REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR()
2884 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK			0x0000ffff
2885 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT			0
2890 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK			0xffff0000
2897 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0;…  in REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR()
2899 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*…  in REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL()
2900 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK		0x0000ffff
2901 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT		0
2906 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK		0xffff0000
2913 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*…  in REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR()
2914 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK		0x0000ffff
2915 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT		0
2920 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK		0xffff0000
2927 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL			0x000080f0
2928 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK			0x00003fff
2929 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT			0
2934 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK			0x3fff0000
2941 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR			0x000080f1
2942 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK			0x00003fff
2943 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT			0
2948 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK			0x3fff0000
2955 #define REG_A6XX_GRAS_LRZ_CNTL					0x00008100
2956 #define A6XX_GRAS_LRZ_CNTL_ENABLE				0x00000001
2957 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE				0x00000002
2958 #define A6XX_GRAS_LRZ_CNTL_GREATER				0x00000004
2959 #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE				0x00000008
2960 #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE			0x00000010
2961 #define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE			0x00000020
2962 #define A6XX_GRAS_LRZ_CNTL_DIR__MASK				0x000000c0
2968 #define A6XX_GRAS_LRZ_CNTL_DIR_WRITE				0x00000100
2969 #define A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR			0x00000200
2971 #define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL				0x00008101
2972 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID			0x00000001
2973 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK	0x00000006
2980 #define REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0			0x00008102
2981 #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK		0x000000ff
2982 #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT	0
2988 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE				0x00008103
2989 #define A6XX_GRAS_LRZ_BUFFER_BASE__MASK				0xffffffff
2990 #define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT			0
2996 #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH				0x00008105
2997 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK			0x000000ff
2998 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT			0
3003 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK		0x1ffffc00
3010 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE		0x00008106
3011 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK		0xffffffff
3012 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT		0
3018 #define REG_A6XX_GRAS_SAMPLE_CNTL				0x00008109
3019 #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE			0x00000001
3021 #define REG_A6XX_GRAS_LRZ_DEPTH_VIEW				0x0000810a
3022 #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK		0x000007ff
3023 #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT		0
3028 #define A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK		0x07ff0000
3034 #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK		0xf0000000
3041 #define REG_A6XX_GRAS_UNKNOWN_8110				0x00008110
3043 #define REG_A6XX_GRAS_2D_BLIT_CNTL				0x00008400
3044 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK			0x00000007
3045 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT			0
3050 #define A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN			0x00000008
3051 #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK			0x00000070
3057 #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR			0x00000080
3058 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK		0x0000ff00
3064 #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR				0x00010000
3065 #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK			0x00060000
3071 #define A6XX_GRAS_2D_BLIT_CNTL_D24S8				0x00080000
3072 #define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK			0x00f00000
3078 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK			0x1f000000
3084 #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK		0x20000000
3091 #define REG_A6XX_GRAS_2D_SRC_TL_X				0x00008401
3093 #define REG_A6XX_GRAS_2D_SRC_BR_X				0x00008402
3095 #define REG_A6XX_GRAS_2D_SRC_TL_Y				0x00008403
3097 #define REG_A6XX_GRAS_2D_SRC_BR_Y				0x00008404
3099 #define REG_A6XX_GRAS_2D_DST_TL					0x00008405
3100 #define A6XX_GRAS_2D_DST_TL_X__MASK				0x00003fff
3101 #define A6XX_GRAS_2D_DST_TL_X__SHIFT				0
3106 #define A6XX_GRAS_2D_DST_TL_Y__MASK				0x3fff0000
3113 #define REG_A6XX_GRAS_2D_DST_BR					0x00008406
3114 #define A6XX_GRAS_2D_DST_BR_X__MASK				0x00003fff
3115 #define A6XX_GRAS_2D_DST_BR_X__SHIFT				0
3120 #define A6XX_GRAS_2D_DST_BR_Y__MASK				0x3fff0000
3127 #define REG_A6XX_GRAS_2D_UNKNOWN_8407				0x00008407
3129 #define REG_A6XX_GRAS_2D_UNKNOWN_8408				0x00008408
3131 #define REG_A6XX_GRAS_2D_UNKNOWN_8409				0x00008409
3133 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1				0x0000840a
3134 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK			0x00003fff
3135 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT			0
3140 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK			0x3fff0000
3147 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2				0x0000840b
3148 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK			0x00003fff
3149 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT			0
3154 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK			0x3fff0000
3161 #define REG_A6XX_GRAS_DBG_ECO_CNTL				0x00008600
3162 #define A6XX_GRAS_DBG_ECO_CNTL_UNK7				0x00000080
3163 #define A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS			0x00000800
3165 #define REG_A6XX_GRAS_ADDR_MODE_CNTL				0x00008601
3167 #define REG_A7XX_GRAS_NC_MODE_CNTL				0x00008602
3169 static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; }  in REG_A6XX_GRAS_PERFCTR_TSE_SEL()
3171 static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; }  in REG_A6XX_GRAS_PERFCTR_RAS_SEL()
3173 static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; }  in REG_A6XX_GRAS_PERFCTR_LRZ_SEL()
3175 #define REG_A6XX_RB_BIN_CONTROL					0x00008800
3176 #define A6XX_RB_BIN_CONTROL_BINW__MASK				0x0000003f
3177 #define A6XX_RB_BIN_CONTROL_BINW__SHIFT				0
3182 #define A6XX_RB_BIN_CONTROL_BINH__MASK				0x00007f00
3188 #define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK			0x001c0000
3194 #define A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS			0x00200000
3195 #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK		0x00c00000
3201 #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK	0x07000000
3208 #define REG_A6XX_RB_RENDER_CNTL					0x00008801
3209 #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK	0x00000038
3215 #define A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN			0x00000040
3216 #define A6XX_RB_RENDER_CNTL_BINNING				0x00000080
3217 #define A6XX_RB_RENDER_CNTL_UNK8__MASK				0x00000700
3223 #define A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK			0x00000100
3229 #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK		0x00000600
3235 #define A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN			0x00000800
3236 #define A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN		0x00001000
3237 #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH				0x00004000
3238 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK			0x00ff0000
3245 #define REG_A6XX_RB_RAS_MSAA_CNTL				0x00008802
3246 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
3247 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT			0
3252 #define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK			0x00000004
3258 #define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK			0x00000008
3265 #define REG_A6XX_RB_DEST_MSAA_CNTL				0x00008803
3266 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK			0x00000003
3267 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT			0
3272 #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004
3274 #define REG_A6XX_RB_SAMPLE_CONFIG				0x00008804
3275 #define A6XX_RB_SAMPLE_CONFIG_UNK0				0x00000001
3276 #define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE			0x00000002
3278 #define REG_A6XX_RB_SAMPLE_LOCATION_0				0x00008805
3279 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK		0x0000000f
3280 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT		0
3285 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK		0x000000f0
3291 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK		0x00000f00
3297 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK		0x0000f000
3303 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK		0x000f0000
3309 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK		0x00f00000
3315 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK		0x0f000000
3321 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK		0xf0000000
3328 #define REG_A6XX_RB_SAMPLE_LOCATION_1				0x00008806
3329 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK		0x0000000f
3330 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT		0
3335 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK		0x000000f0
3341 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK		0x00000f00
3347 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK		0x0000f000
3353 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK		0x000f0000
3359 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK		0x00f00000
3365 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK		0x0f000000
3371 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK		0xf0000000
3378 #define REG_A6XX_RB_RENDER_CONTROL0				0x00008809
3379 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL			0x00000001
3380 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID		0x00000002
3381 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE			0x00000004
3382 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL			0x00000008
3383 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID		0x00000010
3384 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE		0x00000020
3385 #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK		0x000003c0
3391 #define A6XX_RB_RENDER_CONTROL0_UNK10				0x00000400
3393 #define REG_A6XX_RB_RENDER_CONTROL1				0x0000880a
3394 #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK			0x00000001
3395 #define A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE		0x00000002
3396 #define A6XX_RB_RENDER_CONTROL1_FACENESS			0x00000004
3397 #define A6XX_RB_RENDER_CONTROL1_SAMPLEID			0x00000008
3398 #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK	0x00000030
3404 #define A6XX_RB_RENDER_CONTROL1_CENTERRHW			0x00000040
3405 #define A6XX_RB_RENDER_CONTROL1_LINELENGTHEN			0x00000080
3406 #define A6XX_RB_RENDER_CONTROL1_FOVEATION			0x00000100
3408 #define REG_A6XX_RB_FS_OUTPUT_CNTL0				0x0000880b
3409 #define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE		0x00000001
3410 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z			0x00000002
3411 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK		0x00000004
3412 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF		0x00000008
3414 #define REG_A6XX_RB_FS_OUTPUT_CNTL1				0x0000880c
3415 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK			0x0000000f
3416 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT			0
3422 #define REG_A6XX_RB_RENDER_COMPONENTS				0x0000880d
3423 #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK			0x0000000f
3424 #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT			0
3429 #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK			0x000000f0
3435 #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK			0x00000f00
3441 #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK			0x0000f000
3447 #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK			0x000f0000
3453 #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK			0x00f00000
3459 #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK			0x0f000000
3465 #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK			0xf0000000
3472 #define REG_A6XX_RB_DITHER_CNTL					0x0000880e
3473 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK		0x00000003
3474 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT		0
3479 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK		0x0000000c
3485 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK		0x00000030
3491 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK		0x000000c0
3497 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK		0x00000300
3503 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK		0x00000c00
3509 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK		0x00001000
3515 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK		0x0000c000
3522 #define REG_A6XX_RB_SRGB_CNTL					0x0000880f
3523 #define A6XX_RB_SRGB_CNTL_SRGB_MRT0				0x00000001
3524 #define A6XX_RB_SRGB_CNTL_SRGB_MRT1				0x00000002
3525 #define A6XX_RB_SRGB_CNTL_SRGB_MRT2				0x00000004
3526 #define A6XX_RB_SRGB_CNTL_SRGB_MRT3				0x00000008
3527 #define A6XX_RB_SRGB_CNTL_SRGB_MRT4				0x00000010
3528 #define A6XX_RB_SRGB_CNTL_SRGB_MRT5				0x00000020
3529 #define A6XX_RB_SRGB_CNTL_SRGB_MRT6				0x00000040
3530 #define A6XX_RB_SRGB_CNTL_SRGB_MRT7				0x00000080
3532 #define REG_A6XX_RB_SAMPLE_CNTL					0x00008810
3533 #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE			0x00000001
3535 #define REG_A6XX_RB_UNKNOWN_8811				0x00008811
3537 #define REG_A6XX_RB_UNKNOWN_8818				0x00008818
3539 #define REG_A6XX_RB_UNKNOWN_8819				0x00008819
3541 #define REG_A6XX_RB_UNKNOWN_881A				0x0000881a
3543 #define REG_A6XX_RB_UNKNOWN_881B				0x0000881b
3545 #define REG_A6XX_RB_UNKNOWN_881C				0x0000881c
3547 #define REG_A6XX_RB_UNKNOWN_881D				0x0000881d
3549 #define REG_A6XX_RB_UNKNOWN_881E				0x0000881e
3551 static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }  in REG_A6XX_RB_MRT()
3553 static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }  in REG_A6XX_RB_MRT_CONTROL()
3554 #define A6XX_RB_MRT_CONTROL_BLEND				0x00000001
3555 #define A6XX_RB_MRT_CONTROL_BLEND2				0x00000002
3556 #define A6XX_RB_MRT_CONTROL_ROP_ENABLE				0x00000004
3557 #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK			0x00000078
3563 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK		0x00000780
3570 static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }  in REG_A6XX_RB_MRT_BLEND_CONTROL()
3571 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK		0x0000001f
3572 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT		0
3577 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK	0x000000e0
3583 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK		0x00001f00
3589 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK	0x001f0000
3595 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK	0x00e00000
3601 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK	0x1f000000
3608 static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }  in REG_A6XX_RB_MRT_BUF_INFO()
3609 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK			0x000000ff
3610 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT		0
3615 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK		0x00000300
3621 #define A6XX_RB_MRT_BUF_INFO_UNK10__MASK			0x00000400
3627 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK			0x00006000
3634 static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }  in REG_A6XX_RB_MRT_PITCH()
3635 #define A6XX_RB_MRT_PITCH__MASK					0x0000ffff
3636 #define A6XX_RB_MRT_PITCH__SHIFT				0
3642 static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }  in REG_A6XX_RB_MRT_ARRAY_PITCH()
3643 #define A6XX_RB_MRT_ARRAY_PITCH__MASK				0x1fffffff
3644 #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT				0
3650 static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }  in REG_A6XX_RB_MRT_BASE()
3651 #define A6XX_RB_MRT_BASE__MASK					0xffffffff
3652 #define A6XX_RB_MRT_BASE__SHIFT					0
3658 static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }  in REG_A6XX_RB_MRT_BASE_GMEM()
3659 #define A6XX_RB_MRT_BASE_GMEM__MASK				0xfffff000
3666 #define REG_A6XX_RB_BLEND_RED_F32				0x00008860
3667 #define A6XX_RB_BLEND_RED_F32__MASK				0xffffffff
3668 #define A6XX_RB_BLEND_RED_F32__SHIFT				0
3674 #define REG_A6XX_RB_BLEND_GREEN_F32				0x00008861
3675 #define A6XX_RB_BLEND_GREEN_F32__MASK				0xffffffff
3676 #define A6XX_RB_BLEND_GREEN_F32__SHIFT				0
3682 #define REG_A6XX_RB_BLEND_BLUE_F32				0x00008862
3683 #define A6XX_RB_BLEND_BLUE_F32__MASK				0xffffffff
3684 #define A6XX_RB_BLEND_BLUE_F32__SHIFT				0
3690 #define REG_A6XX_RB_BLEND_ALPHA_F32				0x00008863
3691 #define A6XX_RB_BLEND_ALPHA_F32__MASK				0xffffffff
3692 #define A6XX_RB_BLEND_ALPHA_F32__SHIFT				0
3698 #define REG_A6XX_RB_ALPHA_CONTROL				0x00008864
3699 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK			0x000000ff
3700 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT			0
3705 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST			0x00000100
3706 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK		0x00000e00
3713 #define REG_A6XX_RB_BLEND_CNTL					0x00008865
3714 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK			0x000000ff
3715 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT			0
3720 #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND			0x00000100
3721 #define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE			0x00000200
3722 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE			0x00000400
3723 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE				0x00000800
3724 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK			0xffff0000
3731 #define REG_A6XX_RB_DEPTH_PLANE_CNTL				0x00008870
3732 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK			0x00000003
3733 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT			0
3739 #define REG_A6XX_RB_DEPTH_CNTL					0x00008871
3740 #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE			0x00000001
3741 #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE			0x00000002
3742 #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK				0x0000001c
3748 #define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE			0x00000020
3749 #define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE			0x00000040
3750 #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE			0x00000080
3752 #define REG_A6XX_RB_DEPTH_BUFFER_INFO				0x00008872
3753 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK		0x00000007
3754 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT		0
3759 #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK			0x00000018
3766 #define REG_A6XX_RB_DEPTH_BUFFER_PITCH				0x00008873
3767 #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK			0x00003fff
3768 #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT			0
3774 #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH			0x00008874
3775 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK			0x0fffffff
3776 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT			0
3782 #define REG_A6XX_RB_DEPTH_BUFFER_BASE				0x00008875
3783 #define A6XX_RB_DEPTH_BUFFER_BASE__MASK				0xffffffff
3784 #define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT			0
3790 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM			0x00008877
3791 #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK			0xfffff000
3798 #define REG_A6XX_RB_Z_BOUNDS_MIN				0x00008878
3799 #define A6XX_RB_Z_BOUNDS_MIN__MASK				0xffffffff
3800 #define A6XX_RB_Z_BOUNDS_MIN__SHIFT				0
3806 #define REG_A6XX_RB_Z_BOUNDS_MAX				0x00008879
3807 #define A6XX_RB_Z_BOUNDS_MAX__MASK				0xffffffff
3808 #define A6XX_RB_Z_BOUNDS_MAX__SHIFT				0
3814 #define REG_A6XX_RB_STENCIL_CONTROL				0x00008880
3815 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE			0x00000001
3816 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF		0x00000002
3817 #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ			0x00000004
3818 #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK			0x00000700
3824 #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK			0x00003800
3830 #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK			0x0001c000
3836 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK			0x000e0000
3842 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK			0x00700000
3848 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK			0x03800000
3854 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK			0x1c000000
3860 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK			0xe0000000
3867 #define REG_A6XX_RB_STENCIL_INFO				0x00008881
3868 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL			0x00000001
3869 #define A6XX_RB_STENCIL_INFO_UNK1				0x00000002
3871 #define REG_A6XX_RB_STENCIL_BUFFER_PITCH			0x00008882
3872 #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK			0x00000fff
3873 #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT			0
3879 #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH			0x00008883
3880 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK		0x00ffffff
3881 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT		0
3887 #define REG_A6XX_RB_STENCIL_BUFFER_BASE				0x00008884
3888 #define A6XX_RB_STENCIL_BUFFER_BASE__MASK			0xffffffff
3889 #define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT			0
3895 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM			0x00008886
3896 #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK			0xfffff000
3903 #define REG_A6XX_RB_STENCILREF					0x00008887
3904 #define A6XX_RB_STENCILREF_REF__MASK				0x000000ff
3905 #define A6XX_RB_STENCILREF_REF__SHIFT				0
3910 #define A6XX_RB_STENCILREF_BFREF__MASK				0x0000ff00
3917 #define REG_A6XX_RB_STENCILMASK					0x00008888
3918 #define A6XX_RB_STENCILMASK_MASK__MASK				0x000000ff
3919 #define A6XX_RB_STENCILMASK_MASK__SHIFT				0
3924 #define A6XX_RB_STENCILMASK_BFMASK__MASK			0x0000ff00
3931 #define REG_A6XX_RB_STENCILWRMASK				0x00008889
3932 #define A6XX_RB_STENCILWRMASK_WRMASK__MASK			0x000000ff
3933 #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT			0
3938 #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK			0x0000ff00
3945 #define REG_A6XX_RB_WINDOW_OFFSET				0x00008890
3946 #define A6XX_RB_WINDOW_OFFSET_X__MASK				0x00003fff
3947 #define A6XX_RB_WINDOW_OFFSET_X__SHIFT				0
3952 #define A6XX_RB_WINDOW_OFFSET_Y__MASK				0x3fff0000
3959 #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL			0x00008891
3960 #define A6XX_RB_SAMPLE_COUNT_CONTROL_DISABLE			0x00000001
3961 #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY			0x00000002
3963 #define REG_A6XX_RB_LRZ_CNTL					0x00008898
3964 #define A6XX_RB_LRZ_CNTL_ENABLE					0x00000001
3966 #define REG_A6XX_RB_Z_CLAMP_MIN					0x000088c0
3967 #define A6XX_RB_Z_CLAMP_MIN__MASK				0xffffffff
3968 #define A6XX_RB_Z_CLAMP_MIN__SHIFT				0
3974 #define REG_A6XX_RB_Z_CLAMP_MAX					0x000088c1
3975 #define A6XX_RB_Z_CLAMP_MAX__MASK				0xffffffff
3976 #define A6XX_RB_Z_CLAMP_MAX__SHIFT				0
3982 #define REG_A6XX_RB_UNKNOWN_88D0				0x000088d0
3983 #define A6XX_RB_UNKNOWN_88D0_UNK0__MASK				0x00001fff
3984 #define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT			0
3989 #define A6XX_RB_UNKNOWN_88D0_UNK16__MASK			0x07ff0000
3996 #define REG_A6XX_RB_BLIT_SCISSOR_TL				0x000088d1
3997 #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK				0x00003fff
3998 #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT			0
4003 #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK				0x3fff0000
4010 #define REG_A6XX_RB_BLIT_SCISSOR_BR				0x000088d2
4011 #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK				0x00003fff
4012 #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT			0
4017 #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK				0x3fff0000
4024 #define REG_A6XX_RB_BIN_CONTROL2				0x000088d3
4025 #define A6XX_RB_BIN_CONTROL2_BINW__MASK				0x0000003f
4026 #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT			0
4031 #define A6XX_RB_BIN_CONTROL2_BINH__MASK				0x00007f00
4038 #define REG_A6XX_RB_WINDOW_OFFSET2				0x000088d4
4039 #define A6XX_RB_WINDOW_OFFSET2_X__MASK				0x00003fff
4040 #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT				0
4045 #define A6XX_RB_WINDOW_OFFSET2_Y__MASK				0x3fff0000
4052 #define REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL				0x000088d5
4053 #define A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK		0x00000018
4060 #define REG_A6XX_RB_BLIT_BASE_GMEM				0x000088d6
4061 #define A6XX_RB_BLIT_BASE_GMEM__MASK				0xfffff000
4068 #define REG_A6XX_RB_BLIT_DST_INFO				0x000088d7
4069 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK			0x00000003
4070 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT			0
4075 #define A6XX_RB_BLIT_DST_INFO_FLAGS				0x00000004
4076 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK			0x00000018
4082 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK			0x00000060
4088 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK		0x00007f80
4094 #define A6XX_RB_BLIT_DST_INFO_UNK15				0x00008000
4096 #define REG_A6XX_RB_BLIT_DST					0x000088d8
4097 #define A6XX_RB_BLIT_DST__MASK					0xffffffff
4098 #define A6XX_RB_BLIT_DST__SHIFT					0
4104 #define REG_A6XX_RB_BLIT_DST_PITCH				0x000088da
4105 #define A6XX_RB_BLIT_DST_PITCH__MASK				0x0000ffff
4106 #define A6XX_RB_BLIT_DST_PITCH__SHIFT				0
4112 #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH			0x000088db
4113 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK			0x1fffffff
4114 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT			0
4120 #define REG_A6XX_RB_BLIT_FLAG_DST				0x000088dc
4121 #define A6XX_RB_BLIT_FLAG_DST__MASK				0xffffffff
4122 #define A6XX_RB_BLIT_FLAG_DST__SHIFT				0
4128 #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH				0x000088de
4129 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK			0x000007ff
4130 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT		0
4135 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK		0x0ffff800
4142 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0			0x000088df
4144 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1			0x000088e0
4146 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2			0x000088e1
4148 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3			0x000088e2
4150 #define REG_A6XX_RB_BLIT_INFO					0x000088e3
4151 #define A6XX_RB_BLIT_INFO_UNK0					0x00000001
4152 #define A6XX_RB_BLIT_INFO_GMEM					0x00000002
4153 #define A6XX_RB_BLIT_INFO_SAMPLE_0				0x00000004
4154 #define A6XX_RB_BLIT_INFO_DEPTH					0x00000008
4155 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK			0x000000f0
4161 #define A6XX_RB_BLIT_INFO_LAST__MASK				0x00000300
4167 #define A6XX_RB_BLIT_INFO_BUFFER_ID__MASK			0x0000f000
4174 #define REG_A6XX_RB_UNKNOWN_88F0				0x000088f0
4176 #define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE			0x000088f1
4177 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK			0xffffffff
4178 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT			0
4184 #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH			0x000088f3
4185 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK		0x000007ff
4186 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT		0
4191 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK		0x00fff800
4198 #define REG_A6XX_RB_UNKNOWN_88F4				0x000088f4
4200 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE			0x00008900
4201 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK			0xffffffff
4202 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT			0
4208 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH			0x00008902
4209 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK		0x0000007f
4210 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT		0
4215 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK		0x00000700
4221 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK	0x0ffff800
4228 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }  in REG_A6XX_RB_MRT_FLAG_BUFFER()
4230 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }  in REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR()
4231 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK			0xffffffff
4232 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT			0
4238 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0;…  in REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH()
4239 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK		0x000007ff
4240 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT		0
4245 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK		0x1ffff800
4252 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR				0x00008927
4253 #define A6XX_RB_SAMPLE_COUNT_ADDR__MASK				0xffffffff
4254 #define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT			0
4260 #define REG_A6XX_RB_UNKNOWN_8A00				0x00008a00
4262 #define REG_A6XX_RB_UNKNOWN_8A10				0x00008a10
4264 #define REG_A6XX_RB_UNKNOWN_8A20				0x00008a20
4266 #define REG_A6XX_RB_UNKNOWN_8A30				0x00008a30
4268 #define REG_A6XX_RB_2D_BLIT_CNTL				0x00008c00
4269 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK			0x00000007
4270 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT			0
4275 #define A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN			0x00000008
4276 #define A6XX_RB_2D_BLIT_CNTL_UNK4__MASK				0x00000070
4282 #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR			0x00000080
4283 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK			0x0000ff00
4289 #define A6XX_RB_2D_BLIT_CNTL_SCISSOR				0x00010000
4290 #define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK			0x00060000
4296 #define A6XX_RB_2D_BLIT_CNTL_D24S8				0x00080000
4297 #define A6XX_RB_2D_BLIT_CNTL_MASK__MASK				0x00f00000
4303 #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK				0x1f000000
4309 #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK			0x20000000
4316 #define REG_A6XX_RB_2D_UNKNOWN_8C01				0x00008c01
4318 #define REG_A6XX_RB_2D_DST_INFO					0x00008c17
4319 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK			0x000000ff
4320 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT			0
4325 #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK			0x00000300
4331 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK			0x00000c00
4337 #define A6XX_RB_2D_DST_INFO_FLAGS				0x00001000
4338 #define A6XX_RB_2D_DST_INFO_SRGB				0x00002000
4339 #define A6XX_RB_2D_DST_INFO_SAMPLES__MASK			0x0000c000
4345 #define A6XX_RB_2D_DST_INFO_FILTER				0x00010000
4346 #define A6XX_RB_2D_DST_INFO_UNK17				0x00020000
4347 #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE			0x00040000
4348 #define A6XX_RB_2D_DST_INFO_UNK19				0x00080000
4349 #define A6XX_RB_2D_DST_INFO_UNK20				0x00100000
4350 #define A6XX_RB_2D_DST_INFO_UNK21				0x00200000
4351 #define A6XX_RB_2D_DST_INFO_UNK22				0x00400000
4352 #define A6XX_RB_2D_DST_INFO_UNK23__MASK				0x07800000
4358 #define A6XX_RB_2D_DST_INFO_UNK28				0x10000000
4360 #define REG_A6XX_RB_2D_DST					0x00008c18
4361 #define A6XX_RB_2D_DST__MASK					0xffffffff
4362 #define A6XX_RB_2D_DST__SHIFT					0
4368 #define REG_A6XX_RB_2D_DST_PITCH				0x00008c1a
4369 #define A6XX_RB_2D_DST_PITCH__MASK				0x0000ffff
4370 #define A6XX_RB_2D_DST_PITCH__SHIFT				0
4376 #define REG_A6XX_RB_2D_DST_PLANE1				0x00008c1b
4377 #define A6XX_RB_2D_DST_PLANE1__MASK				0xffffffff
4378 #define A6XX_RB_2D_DST_PLANE1__SHIFT				0
4384 #define REG_A6XX_RB_2D_DST_PLANE_PITCH				0x00008c1d
4385 #define A6XX_RB_2D_DST_PLANE_PITCH__MASK			0x0000ffff
4386 #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT			0
4392 #define REG_A6XX_RB_2D_DST_PLANE2				0x00008c1e
4393 #define A6XX_RB_2D_DST_PLANE2__MASK				0xffffffff
4394 #define A6XX_RB_2D_DST_PLANE2__SHIFT				0
4400 #define REG_A6XX_RB_2D_DST_FLAGS				0x00008c20
4401 #define A6XX_RB_2D_DST_FLAGS__MASK				0xffffffff
4402 #define A6XX_RB_2D_DST_FLAGS__SHIFT				0
4408 #define REG_A6XX_RB_2D_DST_FLAGS_PITCH				0x00008c22
4409 #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK			0x000000ff
4410 #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT			0
4416 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE				0x00008c23
4417 #define A6XX_RB_2D_DST_FLAGS_PLANE__MASK			0xffffffff
4418 #define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT			0
4424 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH			0x00008c25
4425 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK			0x000000ff
4426 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT			0
4432 #define REG_A6XX_RB_2D_SRC_SOLID_C0				0x00008c2c
4434 #define REG_A6XX_RB_2D_SRC_SOLID_C1				0x00008c2d
4436 #define REG_A6XX_RB_2D_SRC_SOLID_C2				0x00008c2e
4438 #define REG_A6XX_RB_2D_SRC_SOLID_C3				0x00008c2f
4440 #define REG_A6XX_RB_UNKNOWN_8E01				0x00008e01
4442 #define REG_A6XX_RB_DBG_ECO_CNTL				0x00008e04
4444 #define REG_A6XX_RB_ADDR_MODE_CNTL				0x00008e05
4446 #define REG_A6XX_RB_CCU_CNTL					0x00008e07
4447 #define A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE			0x00000004
4448 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK			0x00000080
4454 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK			0x00000200
4460 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK			0x001ff000
4466 #define A6XX_RB_CCU_CNTL_GMEM					0x00400000
4467 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK			0xff800000
4474 #define REG_A6XX_RB_NC_MODE_CNTL				0x00008e08
4475 #define A6XX_RB_NC_MODE_CNTL_MODE				0x00000001
4476 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK			0x00000006
4482 #define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH			0x00000008
4483 #define A6XX_RB_NC_MODE_CNTL_AMSBC				0x00000010
4484 #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK			0x00000400
4490 #define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR			0x00000800
4491 #define A6XX_RB_NC_MODE_CNTL_UNK12__MASK			0x00003000
4498 static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; }  in REG_A6XX_RB_PERFCTR_RB_SEL()
4500 static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; }  in REG_A6XX_RB_PERFCTR_CCU_SEL()
4502 #define REG_A6XX_RB_UNKNOWN_8E28				0x00008e28
4504 static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; }  in REG_A6XX_RB_PERFCTR_CMP_SEL()
4506 static inline uint32_t REG_A7XX_RB_PERFCTR_UFC_SEL(uint32_t i0) { return 0x00008e30 + 0x1*i0; }  in REG_A7XX_RB_PERFCTR_UFC_SEL()
4508 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST			0x00008e3b
4510 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD			0x00008e3d
4512 #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE		0x00008e50
4514 #define REG_A6XX_RB_UNKNOWN_8E51				0x00008e51
4515 #define A6XX_RB_UNKNOWN_8E51__MASK				0xffffffff
4516 #define A6XX_RB_UNKNOWN_8E51__SHIFT				0
4522 #define REG_A6XX_VPC_GS_PARAM					0x00009100
4523 #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK			0x000000ff
4524 #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT			0
4530 #define REG_A6XX_VPC_VS_CLIP_CNTL				0x00009101
4531 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
4532 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT			0
4537 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
4543 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
4550 #define REG_A6XX_VPC_GS_CLIP_CNTL				0x00009102
4551 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
4552 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT			0
4557 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
4563 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
4570 #define REG_A6XX_VPC_DS_CLIP_CNTL				0x00009103
4571 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
4572 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT			0
4577 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
4583 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
4590 #define REG_A6XX_VPC_VS_LAYER_CNTL				0x00009104
4591 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK			0x000000ff
4592 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT			0
4597 #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK			0x0000ff00
4604 #define REG_A6XX_VPC_GS_LAYER_CNTL				0x00009105
4605 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK			0x000000ff
4606 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT			0
4611 #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK			0x0000ff00
4618 #define REG_A6XX_VPC_DS_LAYER_CNTL				0x00009106
4619 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK			0x000000ff
4620 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT			0
4625 #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK			0x0000ff00
4632 #define REG_A6XX_VPC_UNKNOWN_9107				0x00009107
4633 #define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD			0x00000001
4634 #define A6XX_VPC_UNKNOWN_9107_UNK2				0x00000004
4636 #define REG_A6XX_VPC_POLYGON_MODE				0x00009108
4637 #define A6XX_VPC_POLYGON_MODE_MODE__MASK			0x00000003
4638 #define A6XX_VPC_POLYGON_MODE_MODE__SHIFT			0
4644 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }  in REG_A6XX_VPC_VARYING_INTERP()
4646 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }  in REG_A6XX_VPC_VARYING_INTERP_MODE()
4648 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; }  in REG_A6XX_VPC_VARYING_PS_REPL()
4650 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0;…  in REG_A6XX_VPC_VARYING_PS_REPL_MODE()
4652 #define REG_A6XX_VPC_UNKNOWN_9210				0x00009210
4654 #define REG_A6XX_VPC_UNKNOWN_9211				0x00009211
4656 static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }  in REG_A6XX_VPC_VAR()
4658 static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }  in REG_A6XX_VPC_VAR_DISABLE()
4660 #define REG_A6XX_VPC_SO_CNTL					0x00009216
4661 #define A6XX_VPC_SO_CNTL_ADDR__MASK				0x000000ff
4662 #define A6XX_VPC_SO_CNTL_ADDR__SHIFT				0
4667 #define A6XX_VPC_SO_CNTL_RESET					0x00010000
4669 #define REG_A6XX_VPC_SO_PROG					0x00009217
4670 #define A6XX_VPC_SO_PROG_A_BUF__MASK				0x00000003
4671 #define A6XX_VPC_SO_PROG_A_BUF__SHIFT				0
4676 #define A6XX_VPC_SO_PROG_A_OFF__MASK				0x000007fc
4682 #define A6XX_VPC_SO_PROG_A_EN					0x00000800
4683 #define A6XX_VPC_SO_PROG_B_BUF__MASK				0x00003000
4689 #define A6XX_VPC_SO_PROG_B_OFF__MASK				0x007fc000
4695 #define A6XX_VPC_SO_PROG_B_EN					0x00800000
4697 #define REG_A6XX_VPC_SO_STREAM_COUNTS				0x00009218
4698 #define A6XX_VPC_SO_STREAM_COUNTS__MASK				0xffffffff
4699 #define A6XX_VPC_SO_STREAM_COUNTS__SHIFT			0
4705 static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }  in REG_A6XX_VPC_SO()
4707 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; }  in REG_A6XX_VPC_SO_BUFFER_BASE()
4708 #define A6XX_VPC_SO_BUFFER_BASE__MASK				0xffffffff
4709 #define A6XX_VPC_SO_BUFFER_BASE__SHIFT				0
4715 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }  in REG_A6XX_VPC_SO_BUFFER_SIZE()
4716 #define A6XX_VPC_SO_BUFFER_SIZE__MASK				0xfffffffc
4723 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_STRIDE(uint32_t i0) { return 0x0000921d + 0x7*i0; }  in REG_A6XX_VPC_SO_BUFFER_STRIDE()
4724 #define A6XX_VPC_SO_BUFFER_STRIDE__MASK				0x000003ff
4725 #define A6XX_VPC_SO_BUFFER_STRIDE__SHIFT			0
4731 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }  in REG_A6XX_VPC_SO_BUFFER_OFFSET()
4732 #define A6XX_VPC_SO_BUFFER_OFFSET__MASK				0xfffffffc
4739 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; }  in REG_A6XX_VPC_SO_FLUSH_BASE()
4740 #define A6XX_VPC_SO_FLUSH_BASE__MASK				0xffffffff
4741 #define A6XX_VPC_SO_FLUSH_BASE__SHIFT				0
4747 #define REG_A6XX_VPC_POINT_COORD_INVERT				0x00009236
4748 #define A6XX_VPC_POINT_COORD_INVERT_INVERT			0x00000001
4750 #define REG_A6XX_VPC_UNKNOWN_9300				0x00009300
4752 #define REG_A6XX_VPC_VS_PACK					0x00009301
4753 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK			0x000000ff
4754 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT			0
4759 #define A6XX_VPC_VS_PACK_POSITIONLOC__MASK			0x0000ff00
4765 #define A6XX_VPC_VS_PACK_PSIZELOC__MASK				0x00ff0000
4771 #define A6XX_VPC_VS_PACK_EXTRAPOS__MASK				0x0f000000
4778 #define REG_A6XX_VPC_GS_PACK					0x00009302
4779 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK			0x000000ff
4780 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT			0
4785 #define A6XX_VPC_GS_PACK_POSITIONLOC__MASK			0x0000ff00
4791 #define A6XX_VPC_GS_PACK_PSIZELOC__MASK				0x00ff0000
4797 #define A6XX_VPC_GS_PACK_EXTRAPOS__MASK				0x0f000000
4804 #define REG_A6XX_VPC_DS_PACK					0x00009303
4805 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK			0x000000ff
4806 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT			0
4811 #define A6XX_VPC_DS_PACK_POSITIONLOC__MASK			0x0000ff00
4817 #define A6XX_VPC_DS_PACK_PSIZELOC__MASK				0x00ff0000
4823 #define A6XX_VPC_DS_PACK_EXTRAPOS__MASK				0x0f000000
4830 #define REG_A6XX_VPC_CNTL_0					0x00009304
4831 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK			0x000000ff
4832 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT			0
4837 #define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK				0x0000ff00
4843 #define A6XX_VPC_CNTL_0_VARYING					0x00010000
4844 #define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK				0xff000000
4851 #define REG_A6XX_VPC_SO_STREAM_CNTL				0x00009305
4852 #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK		0x00000007
4853 #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT		0
4858 #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK		0x00000038
4864 #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK		0x000001c0
4870 #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK		0x00000e00
4876 #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK		0x00078000
4883 #define REG_A6XX_VPC_SO_DISABLE					0x00009306
4884 #define A6XX_VPC_SO_DISABLE_DISABLE				0x00000001
4886 #define REG_A6XX_VPC_DBG_ECO_CNTL				0x00009600
4888 #define REG_A6XX_VPC_ADDR_MODE_CNTL				0x00009601
4890 #define REG_A6XX_VPC_UNKNOWN_9602				0x00009602
4892 #define REG_A6XX_VPC_UNKNOWN_9603				0x00009603
4894 static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; }  in REG_A6XX_VPC_PERFCTR_VPC_SEL()
4896 static inline uint32_t REG_A7XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x0000960b + 0x1*i0; }  in REG_A7XX_VPC_PERFCTR_VPC_SEL()
4898 #define REG_A6XX_PC_TESS_NUM_VERTEX				0x00009800
4900 #define REG_A6XX_PC_HS_INPUT_SIZE				0x00009801
4901 #define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK			0x000007ff
4902 #define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT			0
4907 #define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK			0x00002000
4914 #define REG_A6XX_PC_TESS_CNTL					0x00009802
4915 #define A6XX_PC_TESS_CNTL_SPACING__MASK				0x00000003
4916 #define A6XX_PC_TESS_CNTL_SPACING__SHIFT			0
4921 #define A6XX_PC_TESS_CNTL_OUTPUT__MASK				0x0000000c
4928 #define REG_A6XX_PC_RESTART_INDEX				0x00009803
4930 #define REG_A6XX_PC_MODE_CNTL					0x00009804
4932 #define REG_A6XX_PC_POWER_CNTL					0x00009805
4934 #define REG_A6XX_PC_PRIMID_PASSTHRU				0x00009806
4936 #define REG_A6XX_PC_SO_STREAM_CNTL				0x00009808
4937 #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK		0x00078000
4944 #define REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL		0x0000980a
4945 #define A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN	0x00000001
4947 #define REG_A6XX_PC_DRAW_CMD					0x00009840
4948 #define A6XX_PC_DRAW_CMD_STATE_ID__MASK				0x000000ff
4949 #define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT			0
4955 #define REG_A6XX_PC_DISPATCH_CMD				0x00009841
4956 #define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK			0x000000ff
4957 #define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT			0
4963 #define REG_A6XX_PC_EVENT_CMD					0x00009842
4964 #define A6XX_PC_EVENT_CMD_STATE_ID__MASK			0x00ff0000
4970 #define A6XX_PC_EVENT_CMD_EVENT__MASK				0x0000007f
4971 #define A6XX_PC_EVENT_CMD_EVENT__SHIFT				0
4977 #define REG_A6XX_PC_MARKER					0x00009880
4979 #define REG_A6XX_PC_POLYGON_MODE				0x00009981
4980 #define A6XX_PC_POLYGON_MODE_MODE__MASK				0x00000003
4981 #define A6XX_PC_POLYGON_MODE_MODE__SHIFT			0
4987 #define REG_A6XX_PC_RASTER_CNTL					0x00009980
4988 #define A6XX_PC_RASTER_CNTL_STREAM__MASK			0x00000003
4989 #define A6XX_PC_RASTER_CNTL_STREAM__SHIFT			0
4994 #define A6XX_PC_RASTER_CNTL_DISCARD				0x00000004
4996 #define REG_A6XX_PC_PRIMITIVE_CNTL_0				0x00009b00
4997 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART		0x00000001
4998 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST		0x00000002
4999 #define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN	0x00000004
5000 #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3				0x00000008
5002 #define REG_A6XX_PC_VS_OUT_CNTL					0x00009b01
5003 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
5004 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
5009 #define A6XX_PC_VS_OUT_CNTL_PSIZE				0x00000100
5010 #define A6XX_PC_VS_OUT_CNTL_LAYER				0x00000200
5011 #define A6XX_PC_VS_OUT_CNTL_VIEW				0x00000400
5012 #define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID			0x00000800
5013 #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
5020 #define REG_A6XX_PC_GS_OUT_CNTL					0x00009b02
5021 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
5022 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
5027 #define A6XX_PC_GS_OUT_CNTL_PSIZE				0x00000100
5028 #define A6XX_PC_GS_OUT_CNTL_LAYER				0x00000200
5029 #define A6XX_PC_GS_OUT_CNTL_VIEW				0x00000400
5030 #define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID			0x00000800
5031 #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
5038 #define REG_A6XX_PC_HS_OUT_CNTL					0x00009b03
5039 #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
5040 #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
5045 #define A6XX_PC_HS_OUT_CNTL_PSIZE				0x00000100
5046 #define A6XX_PC_HS_OUT_CNTL_LAYER				0x00000200
5047 #define A6XX_PC_HS_OUT_CNTL_VIEW				0x00000400
5048 #define A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID			0x00000800
5049 #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
5056 #define REG_A6XX_PC_DS_OUT_CNTL					0x00009b04
5057 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
5058 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
5063 #define A6XX_PC_DS_OUT_CNTL_PSIZE				0x00000100
5064 #define A6XX_PC_DS_OUT_CNTL_LAYER				0x00000200
5065 #define A6XX_PC_DS_OUT_CNTL_VIEW				0x00000400
5066 #define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID			0x00000800
5067 #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
5074 #define REG_A6XX_PC_PRIMITIVE_CNTL_5				0x00009b05
5075 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK		0x000000ff
5076 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT		0
5081 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK		0x00007c00
5087 #define A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN			0x00008000
5088 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK		0x00030000
5094 #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK			0x00040000
5101 #define REG_A6XX_PC_PRIMITIVE_CNTL_6				0x00009b06
5102 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK		0x000007ff
5103 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT		0
5109 #define REG_A6XX_PC_MULTIVIEW_CNTL				0x00009b07
5110 #define A6XX_PC_MULTIVIEW_CNTL_ENABLE				0x00000001
5111 #define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS			0x00000002
5112 #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK			0x0000007c
5119 #define REG_A6XX_PC_MULTIVIEW_MASK				0x00009b08
5121 #define REG_A6XX_PC_2D_EVENT_CMD				0x00009c00
5122 #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK			0x0000007f
5123 #define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT			0
5128 #define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK			0x0000ff00
5135 #define REG_A6XX_PC_DBG_ECO_CNTL				0x00009e00
5137 #define REG_A6XX_PC_ADDR_MODE_CNTL				0x00009e01
5139 #define REG_A6XX_PC_DRAW_INDX_BASE				0x00009e04
5141 #define REG_A6XX_PC_DRAW_FIRST_INDX				0x00009e06
5143 #define REG_A6XX_PC_DRAW_MAX_INDICES				0x00009e07
5145 #define REG_A6XX_PC_TESSFACTOR_ADDR				0x00009e08
5146 #define A6XX_PC_TESSFACTOR_ADDR__MASK				0xffffffff
5147 #define A6XX_PC_TESSFACTOR_ADDR__SHIFT				0
5153 #define REG_A6XX_PC_DRAW_INITIATOR				0x00009e0b
5154 #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK			0x0000003f
5155 #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT			0
5160 #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK		0x000000c0
5166 #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK			0x00000300
5172 #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK			0x00000c00
5178 #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK			0x00003000
5184 #define A6XX_PC_DRAW_INITIATOR_GS_ENABLE			0x00010000
5185 #define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE			0x00020000
5187 #define REG_A6XX_PC_DRAW_NUM_INSTANCES				0x00009e0c
5189 #define REG_A6XX_PC_DRAW_NUM_INDICES				0x00009e0d
5191 #define REG_A6XX_PC_VSTREAM_CONTROL				0x00009e11
5192 #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK			0x0000ffff
5193 #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT			0
5198 #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK			0x003f0000
5204 #define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK			0x07c00000
5211 #define REG_A6XX_PC_BIN_PRIM_STRM				0x00009e12
5212 #define A6XX_PC_BIN_PRIM_STRM__MASK				0xffffffff
5213 #define A6XX_PC_BIN_PRIM_STRM__SHIFT				0
5219 #define REG_A6XX_PC_BIN_DRAW_STRM				0x00009e14
5220 #define A6XX_PC_BIN_DRAW_STRM__MASK				0xffffffff
5221 #define A6XX_PC_BIN_DRAW_STRM__SHIFT				0
5227 #define REG_A6XX_PC_VISIBILITY_OVERRIDE				0x00009e1c
5228 #define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE			0x00000001
5230 static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; }  in REG_A6XX_PC_PERFCTR_PC_SEL()
5232 static inline uint32_t REG_A7XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e42 + 0x1*i0; }  in REG_A7XX_PC_PERFCTR_PC_SEL()
5234 #define REG_A6XX_PC_UNKNOWN_9E72				0x00009e72
5236 #define REG_A6XX_VFD_CONTROL_0					0x0000a000
5237 #define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK			0x0000003f
5238 #define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT			0
5243 #define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK			0x00003f00
5250 #define REG_A6XX_VFD_CONTROL_1					0x0000a001
5251 #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK			0x000000ff
5252 #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT			0
5257 #define A6XX_VFD_CONTROL_1_REGID4INST__MASK			0x0000ff00
5263 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK			0x00ff0000
5269 #define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK			0xff000000
5276 #define REG_A6XX_VFD_CONTROL_2					0x0000a002
5277 #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK		0x000000ff
5278 #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT		0
5283 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK		0x0000ff00
5290 #define REG_A6XX_VFD_CONTROL_3					0x0000a003
5291 #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK			0x000000ff
5292 #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT		0
5297 #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK		0x0000ff00
5303 #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK			0x00ff0000
5309 #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK			0xff000000
5316 #define REG_A6XX_VFD_CONTROL_4					0x0000a004
5317 #define A6XX_VFD_CONTROL_4_UNK0__MASK				0x000000ff
5318 #define A6XX_VFD_CONTROL_4_UNK0__SHIFT				0
5324 #define REG_A6XX_VFD_CONTROL_5					0x0000a005
5325 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK			0x000000ff
5326 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT		0
5331 #define A6XX_VFD_CONTROL_5_UNK8__MASK				0x0000ff00
5338 #define REG_A6XX_VFD_CONTROL_6					0x0000a006
5339 #define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU			0x00000001
5341 #define REG_A6XX_VFD_MODE_CNTL					0x0000a007
5342 #define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK			0x00000007
5343 #define A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT			0
5349 #define REG_A6XX_VFD_MULTIVIEW_CNTL				0x0000a008
5350 #define A6XX_VFD_MULTIVIEW_CNTL_ENABLE				0x00000001
5351 #define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS			0x00000002
5352 #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK			0x0000007c
5359 #define REG_A6XX_VFD_ADD_OFFSET					0x0000a009
5360 #define A6XX_VFD_ADD_OFFSET_VERTEX				0x00000001
5361 #define A6XX_VFD_ADD_OFFSET_INSTANCE				0x00000002
5363 #define REG_A6XX_VFD_INDEX_OFFSET				0x0000a00e
5365 #define REG_A6XX_VFD_INSTANCE_START_OFFSET			0x0000a00f
5367 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }  in REG_A6XX_VFD_FETCH()
5369 static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }  in REG_A6XX_VFD_FETCH_BASE()
5370 #define A6XX_VFD_FETCH_BASE__MASK				0xffffffff
5371 #define A6XX_VFD_FETCH_BASE__SHIFT				0
5377 static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }  in REG_A6XX_VFD_FETCH_SIZE()
5379 static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }  in REG_A6XX_VFD_FETCH_STRIDE()
5381 static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }  in REG_A6XX_VFD_DECODE()
5383 static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }  in REG_A6XX_VFD_DECODE_INSTR()
5384 #define A6XX_VFD_DECODE_INSTR_IDX__MASK				0x0000001f
5385 #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT			0
5390 #define A6XX_VFD_DECODE_INSTR_OFFSET__MASK			0x0001ffe0
5396 #define A6XX_VFD_DECODE_INSTR_INSTANCED				0x00020000
5397 #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK			0x0ff00000
5403 #define A6XX_VFD_DECODE_INSTR_SWAP__MASK			0x30000000
5409 #define A6XX_VFD_DECODE_INSTR_UNK30				0x40000000
5410 #define A6XX_VFD_DECODE_INSTR_FLOAT				0x80000000
5412 static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }  in REG_A6XX_VFD_DECODE_STEP_RATE()
5414 static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }  in REG_A6XX_VFD_DEST_CNTL()
5416 static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }  in REG_A6XX_VFD_DEST_CNTL_INSTR()
5417 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK		0x0000000f
5418 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT		0
5423 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK			0x00000ff0
5430 #define REG_A6XX_VFD_POWER_CNTL					0x0000a0f8
5432 #define REG_A6XX_VFD_ADDR_MODE_CNTL				0x0000a601
5434 static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; }  in REG_A6XX_VFD_PERFCTR_VFD_SEL()
5436 static inline uint32_t REG_A7XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; }  in REG_A7XX_VFD_PERFCTR_VFD_SEL()
5438 #define REG_A6XX_SP_VS_CTRL_REG0				0x0000a800
5439 #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS				0x00100000
5440 #define A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE			0x00200000
5441 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK			0x00000001
5442 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT			0
5447 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
5453 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
5459 #define A6XX_SP_VS_CTRL_REG0_UNK13				0x00002000
5460 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
5467 #define REG_A6XX_SP_VS_BRANCH_COND				0x0000a801
5469 #define REG_A6XX_SP_VS_PRIMITIVE_CNTL				0x0000a802
5470 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK			0x0000003f
5471 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT			0
5476 #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK		0x00003fc0
5483 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }  in REG_A6XX_SP_VS_OUT()
5485 static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }  in REG_A6XX_SP_VS_OUT_REG()
5486 #define A6XX_SP_VS_OUT_REG_A_REGID__MASK			0x000000ff
5487 #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT			0
5492 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK			0x00000f00
5498 #define A6XX_SP_VS_OUT_REG_B_REGID__MASK			0x00ff0000
5504 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK			0x0f000000
5511 static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; }  in REG_A6XX_SP_VS_VPC_DST()
5513 static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }  in REG_A6XX_SP_VS_VPC_DST_REG()
5514 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
5515 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT			0
5520 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
5526 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
5532 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
5539 #define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET			0x0000a81b
5541 #define REG_A6XX_SP_VS_OBJ_START				0x0000a81c
5542 #define A6XX_SP_VS_OBJ_START__MASK				0xffffffff
5543 #define A6XX_SP_VS_OBJ_START__SHIFT				0
5549 #define REG_A6XX_SP_VS_PVT_MEM_PARAM				0x0000a81e
5550 #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK		0x000000ff
5551 #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT		0
5556 #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK	0xff000000
5563 #define REG_A6XX_SP_VS_PVT_MEM_ADDR				0x0000a81f
5564 #define A6XX_SP_VS_PVT_MEM_ADDR__MASK				0xffffffff
5565 #define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT				0
5571 #define REG_A6XX_SP_VS_PVT_MEM_SIZE				0x0000a821
5572 #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK		0x0003ffff
5573 #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT		0
5578 #define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT		0x80000000
5580 #define REG_A6XX_SP_VS_TEX_COUNT				0x0000a822
5582 #define REG_A6XX_SP_VS_CONFIG					0x0000a823
5583 #define A6XX_SP_VS_CONFIG_BINDLESS_TEX				0x00000001
5584 #define A6XX_SP_VS_CONFIG_BINDLESS_SAMP				0x00000002
5585 #define A6XX_SP_VS_CONFIG_BINDLESS_IBO				0x00000004
5586 #define A6XX_SP_VS_CONFIG_BINDLESS_UBO				0x00000008
5587 #define A6XX_SP_VS_CONFIG_ENABLED				0x00000100
5588 #define A6XX_SP_VS_CONFIG_NTEX__MASK				0x0001fe00
5594 #define A6XX_SP_VS_CONFIG_NSAMP__MASK				0x003e0000
5600 #define A6XX_SP_VS_CONFIG_NIBO__MASK				0x1fc00000
5607 #define REG_A6XX_SP_VS_INSTRLEN					0x0000a824
5609 #define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET			0x0000a825
5610 #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK		0x0007ffff
5611 #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT	0
5617 #define REG_A6XX_SP_HS_CTRL_REG0				0x0000a830
5618 #define A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE			0x00100000
5619 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK			0x00000001
5620 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT			0
5625 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
5631 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
5637 #define A6XX_SP_HS_CTRL_REG0_UNK13				0x00002000
5638 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
5645 #define REG_A6XX_SP_HS_WAVE_INPUT_SIZE				0x0000a831
5647 #define REG_A6XX_SP_HS_BRANCH_COND				0x0000a832
5649 #define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET			0x0000a833
5651 #define REG_A6XX_SP_HS_OBJ_START				0x0000a834
5652 #define A6XX_SP_HS_OBJ_START__MASK				0xffffffff
5653 #define A6XX_SP_HS_OBJ_START__SHIFT				0
5659 #define REG_A6XX_SP_HS_PVT_MEM_PARAM				0x0000a836
5660 #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK		0x000000ff
5661 #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT		0
5666 #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK	0xff000000
5673 #define REG_A6XX_SP_HS_PVT_MEM_ADDR				0x0000a837
5674 #define A6XX_SP_HS_PVT_MEM_ADDR__MASK				0xffffffff
5675 #define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT				0
5681 #define REG_A6XX_SP_HS_PVT_MEM_SIZE				0x0000a839
5682 #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK		0x0003ffff
5683 #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT		0
5688 #define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT		0x80000000
5690 #define REG_A6XX_SP_HS_TEX_COUNT				0x0000a83a
5692 #define REG_A6XX_SP_HS_CONFIG					0x0000a83b
5693 #define A6XX_SP_HS_CONFIG_BINDLESS_TEX				0x00000001
5694 #define A6XX_SP_HS_CONFIG_BINDLESS_SAMP				0x00000002
5695 #define A6XX_SP_HS_CONFIG_BINDLESS_IBO				0x00000004
5696 #define A6XX_SP_HS_CONFIG_BINDLESS_UBO				0x00000008
5697 #define A6XX_SP_HS_CONFIG_ENABLED				0x00000100
5698 #define A6XX_SP_HS_CONFIG_NTEX__MASK				0x0001fe00
5704 #define A6XX_SP_HS_CONFIG_NSAMP__MASK				0x003e0000
5710 #define A6XX_SP_HS_CONFIG_NIBO__MASK				0x1fc00000
5717 #define REG_A6XX_SP_HS_INSTRLEN					0x0000a83c
5719 #define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET			0x0000a83d
5720 #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK		0x0007ffff
5721 #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT	0
5727 #define REG_A6XX_SP_DS_CTRL_REG0				0x0000a840
5728 #define A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE			0x00100000
5729 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK			0x00000001
5730 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT			0
5735 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
5741 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
5747 #define A6XX_SP_DS_CTRL_REG0_UNK13				0x00002000
5748 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
5755 #define REG_A6XX_SP_DS_BRANCH_COND				0x0000a841
5757 #define REG_A6XX_SP_DS_PRIMITIVE_CNTL				0x0000a842
5758 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK			0x0000003f
5759 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT			0
5764 #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK		0x00003fc0
5771 static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }  in REG_A6XX_SP_DS_OUT()
5773 static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }  in REG_A6XX_SP_DS_OUT_REG()
5774 #define A6XX_SP_DS_OUT_REG_A_REGID__MASK			0x000000ff
5775 #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT			0
5780 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK			0x00000f00
5786 #define A6XX_SP_DS_OUT_REG_B_REGID__MASK			0x00ff0000
5792 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK			0x0f000000
5799 static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; }  in REG_A6XX_SP_DS_VPC_DST()
5801 static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; }  in REG_A6XX_SP_DS_VPC_DST_REG()
5802 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
5803 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT			0
5808 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
5814 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
5820 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
5827 #define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET			0x0000a85b
5829 #define REG_A6XX_SP_DS_OBJ_START				0x0000a85c
5830 #define A6XX_SP_DS_OBJ_START__MASK				0xffffffff
5831 #define A6XX_SP_DS_OBJ_START__SHIFT				0
5837 #define REG_A6XX_SP_DS_PVT_MEM_PARAM				0x0000a85e
5838 #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK		0x000000ff
5839 #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT		0
5844 #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK	0xff000000
5851 #define REG_A6XX_SP_DS_PVT_MEM_ADDR				0x0000a85f
5852 #define A6XX_SP_DS_PVT_MEM_ADDR__MASK				0xffffffff
5853 #define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT				0
5859 #define REG_A6XX_SP_DS_PVT_MEM_SIZE				0x0000a861
5860 #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK		0x0003ffff
5861 #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT		0
5866 #define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT		0x80000000
5868 #define REG_A6XX_SP_DS_TEX_COUNT				0x0000a862
5870 #define REG_A6XX_SP_DS_CONFIG					0x0000a863
5871 #define A6XX_SP_DS_CONFIG_BINDLESS_TEX				0x00000001
5872 #define A6XX_SP_DS_CONFIG_BINDLESS_SAMP				0x00000002
5873 #define A6XX_SP_DS_CONFIG_BINDLESS_IBO				0x00000004
5874 #define A6XX_SP_DS_CONFIG_BINDLESS_UBO				0x00000008
5875 #define A6XX_SP_DS_CONFIG_ENABLED				0x00000100
5876 #define A6XX_SP_DS_CONFIG_NTEX__MASK				0x0001fe00
5882 #define A6XX_SP_DS_CONFIG_NSAMP__MASK				0x003e0000
5888 #define A6XX_SP_DS_CONFIG_NIBO__MASK				0x1fc00000
5895 #define REG_A6XX_SP_DS_INSTRLEN					0x0000a864
5897 #define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET			0x0000a865
5898 #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK		0x0007ffff
5899 #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT	0
5905 #define REG_A6XX_SP_GS_CTRL_REG0				0x0000a870
5906 #define A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE			0x00100000
5907 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK			0x00000001
5908 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT			0
5913 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
5919 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
5925 #define A6XX_SP_GS_CTRL_REG0_UNK13				0x00002000
5926 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
5933 #define REG_A6XX_SP_GS_PRIM_SIZE				0x0000a871
5935 #define REG_A6XX_SP_GS_BRANCH_COND				0x0000a872
5937 #define REG_A6XX_SP_GS_PRIMITIVE_CNTL				0x0000a873
5938 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK			0x0000003f
5939 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT			0
5944 #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK		0x00003fc0
5951 static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; }  in REG_A6XX_SP_GS_OUT()
5953 static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; }  in REG_A6XX_SP_GS_OUT_REG()
5954 #define A6XX_SP_GS_OUT_REG_A_REGID__MASK			0x000000ff
5955 #define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT			0
5960 #define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK			0x00000f00
5966 #define A6XX_SP_GS_OUT_REG_B_REGID__MASK			0x00ff0000
5972 #define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK			0x0f000000
5979 static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; }  in REG_A6XX_SP_GS_VPC_DST()
5981 static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; }  in REG_A6XX_SP_GS_VPC_DST_REG()
5982 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
5983 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT			0
5988 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
5994 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
6000 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
6007 #define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET			0x0000a88c
6009 #define REG_A6XX_SP_GS_OBJ_START				0x0000a88d
6010 #define A6XX_SP_GS_OBJ_START__MASK				0xffffffff
6011 #define A6XX_SP_GS_OBJ_START__SHIFT				0
6017 #define REG_A6XX_SP_GS_PVT_MEM_PARAM				0x0000a88f
6018 #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK		0x000000ff
6019 #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT		0
6024 #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK	0xff000000
6031 #define REG_A6XX_SP_GS_PVT_MEM_ADDR				0x0000a890
6032 #define A6XX_SP_GS_PVT_MEM_ADDR__MASK				0xffffffff
6033 #define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT				0
6039 #define REG_A6XX_SP_GS_PVT_MEM_SIZE				0x0000a892
6040 #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK		0x0003ffff
6041 #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT		0
6046 #define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT		0x80000000
6048 #define REG_A6XX_SP_GS_TEX_COUNT				0x0000a893
6050 #define REG_A6XX_SP_GS_CONFIG					0x0000a894
6051 #define A6XX_SP_GS_CONFIG_BINDLESS_TEX				0x00000001
6052 #define A6XX_SP_GS_CONFIG_BINDLESS_SAMP				0x00000002
6053 #define A6XX_SP_GS_CONFIG_BINDLESS_IBO				0x00000004
6054 #define A6XX_SP_GS_CONFIG_BINDLESS_UBO				0x00000008
6055 #define A6XX_SP_GS_CONFIG_ENABLED				0x00000100
6056 #define A6XX_SP_GS_CONFIG_NTEX__MASK				0x0001fe00
6062 #define A6XX_SP_GS_CONFIG_NSAMP__MASK				0x003e0000
6068 #define A6XX_SP_GS_CONFIG_NIBO__MASK				0x1fc00000
6075 #define REG_A6XX_SP_GS_INSTRLEN					0x0000a895
6077 #define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET			0x0000a896
6078 #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK		0x0007ffff
6079 #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT	0
6085 #define REG_A6XX_SP_VS_TEX_SAMP					0x0000a8a0
6086 #define A6XX_SP_VS_TEX_SAMP__MASK				0xffffffff
6087 #define A6XX_SP_VS_TEX_SAMP__SHIFT				0
6093 #define REG_A6XX_SP_HS_TEX_SAMP					0x0000a8a2
6094 #define A6XX_SP_HS_TEX_SAMP__MASK				0xffffffff
6095 #define A6XX_SP_HS_TEX_SAMP__SHIFT				0
6101 #define REG_A6XX_SP_DS_TEX_SAMP					0x0000a8a4
6102 #define A6XX_SP_DS_TEX_SAMP__MASK				0xffffffff
6103 #define A6XX_SP_DS_TEX_SAMP__SHIFT				0
6109 #define REG_A6XX_SP_GS_TEX_SAMP					0x0000a8a6
6110 #define A6XX_SP_GS_TEX_SAMP__MASK				0xffffffff
6111 #define A6XX_SP_GS_TEX_SAMP__SHIFT				0
6117 #define REG_A6XX_SP_VS_TEX_CONST				0x0000a8a8
6118 #define A6XX_SP_VS_TEX_CONST__MASK				0xffffffff
6119 #define A6XX_SP_VS_TEX_CONST__SHIFT				0
6125 #define REG_A6XX_SP_HS_TEX_CONST				0x0000a8aa
6126 #define A6XX_SP_HS_TEX_CONST__MASK				0xffffffff
6127 #define A6XX_SP_HS_TEX_CONST__SHIFT				0
6133 #define REG_A6XX_SP_DS_TEX_CONST				0x0000a8ac
6134 #define A6XX_SP_DS_TEX_CONST__MASK				0xffffffff
6135 #define A6XX_SP_DS_TEX_CONST__SHIFT				0
6141 #define REG_A6XX_SP_GS_TEX_CONST				0x0000a8ae
6142 #define A6XX_SP_GS_TEX_CONST__MASK				0xffffffff
6143 #define A6XX_SP_GS_TEX_CONST__SHIFT				0
6149 #define REG_A6XX_SP_FS_CTRL_REG0				0x0000a980
6150 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK			0x00100000
6156 #define A6XX_SP_FS_CTRL_REG0_UNK21				0x00200000
6157 #define A6XX_SP_FS_CTRL_REG0_VARYING				0x00400000
6158 #define A6XX_SP_FS_CTRL_REG0_DIFF_FINE				0x00800000
6159 #define A6XX_SP_FS_CTRL_REG0_UNK24				0x01000000
6160 #define A6XX_SP_FS_CTRL_REG0_UNK25				0x02000000
6161 #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE			0x04000000
6162 #define A6XX_SP_FS_CTRL_REG0_UNK27				0x08000000
6163 #define A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE			0x10000000
6164 #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS				0x80000000
6165 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK			0x00000001
6166 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT			0
6171 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
6177 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
6183 #define A6XX_SP_FS_CTRL_REG0_UNK13				0x00002000
6184 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
6191 #define REG_A6XX_SP_FS_BRANCH_COND				0x0000a981
6193 #define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET			0x0000a982
6195 #define REG_A6XX_SP_FS_OBJ_START				0x0000a983
6196 #define A6XX_SP_FS_OBJ_START__MASK				0xffffffff
6197 #define A6XX_SP_FS_OBJ_START__SHIFT				0
6203 #define REG_A6XX_SP_FS_PVT_MEM_PARAM				0x0000a985
6204 #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK		0x000000ff
6205 #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT		0
6210 #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK	0xff000000
6217 #define REG_A6XX_SP_FS_PVT_MEM_ADDR				0x0000a986
6218 #define A6XX_SP_FS_PVT_MEM_ADDR__MASK				0xffffffff
6219 #define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT				0
6225 #define REG_A6XX_SP_FS_PVT_MEM_SIZE				0x0000a988
6226 #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK		0x0003ffff
6227 #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT		0
6232 #define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT		0x80000000
6234 #define REG_A6XX_SP_BLEND_CNTL					0x0000a989
6235 #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK			0x000000ff
6236 #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT			0
6241 #define A6XX_SP_BLEND_CNTL_UNK8					0x00000100
6242 #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE			0x00000200
6243 #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE			0x00000400
6245 #define REG_A6XX_SP_SRGB_CNTL					0x0000a98a
6246 #define A6XX_SP_SRGB_CNTL_SRGB_MRT0				0x00000001
6247 #define A6XX_SP_SRGB_CNTL_SRGB_MRT1				0x00000002
6248 #define A6XX_SP_SRGB_CNTL_SRGB_MRT2				0x00000004
6249 #define A6XX_SP_SRGB_CNTL_SRGB_MRT3				0x00000008
6250 #define A6XX_SP_SRGB_CNTL_SRGB_MRT4				0x00000010
6251 #define A6XX_SP_SRGB_CNTL_SRGB_MRT5				0x00000020
6252 #define A6XX_SP_SRGB_CNTL_SRGB_MRT6				0x00000040
6253 #define A6XX_SP_SRGB_CNTL_SRGB_MRT7				0x00000080
6255 #define REG_A6XX_SP_FS_RENDER_COMPONENTS			0x0000a98b
6256 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK			0x0000000f
6257 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT			0
6262 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK			0x000000f0
6268 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK			0x00000f00
6274 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK			0x0000f000
6280 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK			0x000f0000
6286 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK			0x00f00000
6292 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK			0x0f000000
6298 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK			0xf0000000
6305 #define REG_A6XX_SP_FS_OUTPUT_CNTL0				0x0000a98c
6306 #define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE		0x00000001
6307 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK		0x0000ff00
6313 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK		0x00ff0000
6319 #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK		0xff000000
6326 #define REG_A6XX_SP_FS_OUTPUT_CNTL1				0x0000a98d
6327 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK			0x0000000f
6328 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT			0
6334 static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }  in REG_A6XX_SP_FS_OUTPUT()
6336 static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }  in REG_A6XX_SP_FS_OUTPUT_REG()
6337 #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK			0x000000ff
6338 #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT			0
6343 #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION			0x00000100
6345 static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }  in REG_A6XX_SP_FS_MRT()
6347 static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }  in REG_A6XX_SP_FS_MRT_REG()
6348 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK			0x000000ff
6349 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT			0
6354 #define A6XX_SP_FS_MRT_REG_COLOR_SINT				0x00000100
6355 #define A6XX_SP_FS_MRT_REG_COLOR_UINT				0x00000200
6356 #define A6XX_SP_FS_MRT_REG_UNK10				0x00000400
6358 #define REG_A6XX_SP_FS_PREFETCH_CNTL				0x0000a99e
6359 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK			0x00000007
6360 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT			0
6365 #define A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE		0x00000008
6366 #define A6XX_SP_FS_PREFETCH_CNTL_UNK4				0x00000010
6367 #define A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT		0x00000020
6368 #define A6XX_SP_FS_PREFETCH_CNTL_UNK6__MASK			0x00007fc0
6375 static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }  in REG_A6XX_SP_FS_PREFETCH()
6377 static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }  in REG_A6XX_SP_FS_PREFETCH_CMD()
6378 #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK			0x0000007f
6379 #define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT			0
6384 #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK			0x00000780
6390 #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK			0x0000f800
6396 #define A6XX_SP_FS_PREFETCH_CMD_DST__MASK			0x003f0000
6402 #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK			0x03c00000
6408 #define A6XX_SP_FS_PREFETCH_CMD_HALF				0x04000000
6409 #define A6XX_SP_FS_PREFETCH_CMD_UNK27				0x08000000
6410 #define A6XX_SP_FS_PREFETCH_CMD_BINDLESS			0x10000000
6411 #define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK			0xe0000000
6418 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }  in REG_A6XX_SP_FS_BINDLESS_PREFETCH()
6420 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*…  in REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD()
6421 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK		0x0000ffff
6422 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT		0
6427 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK		0xffff0000
6434 #define REG_A6XX_SP_FS_TEX_COUNT				0x0000a9a7
6436 #define REG_A6XX_SP_UNKNOWN_A9A8				0x0000a9a8
6438 #define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET			0x0000a9a9
6439 #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK		0x0007ffff
6440 #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT	0
6446 #define REG_A6XX_SP_CS_CTRL_REG0				0x0000a9b0
6447 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK			0x00100000
6453 #define A6XX_SP_CS_CTRL_REG0_UNK21				0x00200000
6454 #define A6XX_SP_CS_CTRL_REG0_UNK22				0x00400000
6455 #define A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE			0x00800000
6456 #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS				0x80000000
6457 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK			0x00000001
6458 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT			0
6463 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
6469 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
6475 #define A6XX_SP_CS_CTRL_REG0_UNK13				0x00002000
6476 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
6483 #define REG_A6XX_SP_CS_UNKNOWN_A9B1				0x0000a9b1
6484 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK		0x0000001f
6485 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT		0
6490 #define A6XX_SP_CS_UNKNOWN_A9B1_UNK5				0x00000020
6491 #define A6XX_SP_CS_UNKNOWN_A9B1_UNK6				0x00000040
6493 #define REG_A6XX_SP_CS_BRANCH_COND				0x0000a9b2
6495 #define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET			0x0000a9b3
6497 #define REG_A6XX_SP_CS_OBJ_START				0x0000a9b4
6498 #define A6XX_SP_CS_OBJ_START__MASK				0xffffffff
6499 #define A6XX_SP_CS_OBJ_START__SHIFT				0
6505 #define REG_A6XX_SP_CS_PVT_MEM_PARAM				0x0000a9b6
6506 #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK		0x000000ff
6507 #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT		0
6512 #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK	0xff000000
6519 #define REG_A6XX_SP_CS_PVT_MEM_ADDR				0x0000a9b7
6520 #define A6XX_SP_CS_PVT_MEM_ADDR__MASK				0xffffffff
6521 #define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT				0
6527 #define REG_A6XX_SP_CS_PVT_MEM_SIZE				0x0000a9b9
6528 #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK		0x0003ffff
6529 #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT		0
6534 #define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT		0x80000000
6536 #define REG_A6XX_SP_CS_TEX_COUNT				0x0000a9ba
6538 #define REG_A6XX_SP_CS_CONFIG					0x0000a9bb
6539 #define A6XX_SP_CS_CONFIG_BINDLESS_TEX				0x00000001
6540 #define A6XX_SP_CS_CONFIG_BINDLESS_SAMP				0x00000002
6541 #define A6XX_SP_CS_CONFIG_BINDLESS_IBO				0x00000004
6542 #define A6XX_SP_CS_CONFIG_BINDLESS_UBO				0x00000008
6543 #define A6XX_SP_CS_CONFIG_ENABLED				0x00000100
6544 #define A6XX_SP_CS_CONFIG_NTEX__MASK				0x0001fe00
6550 #define A6XX_SP_CS_CONFIG_NSAMP__MASK				0x003e0000
6556 #define A6XX_SP_CS_CONFIG_NIBO__MASK				0x1fc00000
6563 #define REG_A6XX_SP_CS_INSTRLEN					0x0000a9bc
6565 #define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET			0x0000a9bd
6566 #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK		0x0007ffff
6567 #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT	0
6573 #define REG_A6XX_SP_CS_CNTL_0					0x0000a9c2
6574 #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK			0x000000ff
6575 #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT			0
6580 #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK			0x0000ff00
6586 #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK			0x00ff0000
6592 #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK			0xff000000
6599 #define REG_A6XX_SP_CS_CNTL_1					0x0000a9c3
6600 #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK		0x000000ff
6601 #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT		0
6606 #define A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE			0x00000100
6607 #define A6XX_SP_CS_CNTL_1_THREADSIZE__MASK			0x00000200
6613 #define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR			0x00000400
6615 #define REG_A6XX_SP_FS_TEX_SAMP					0x0000a9e0
6616 #define A6XX_SP_FS_TEX_SAMP__MASK				0xffffffff
6617 #define A6XX_SP_FS_TEX_SAMP__SHIFT				0
6623 #define REG_A6XX_SP_CS_TEX_SAMP					0x0000a9e2
6624 #define A6XX_SP_CS_TEX_SAMP__MASK				0xffffffff
6625 #define A6XX_SP_CS_TEX_SAMP__SHIFT				0
6631 #define REG_A6XX_SP_FS_TEX_CONST				0x0000a9e4
6632 #define A6XX_SP_FS_TEX_CONST__MASK				0xffffffff
6633 #define A6XX_SP_FS_TEX_CONST__SHIFT				0
6639 #define REG_A6XX_SP_CS_TEX_CONST				0x0000a9e6
6640 #define A6XX_SP_CS_TEX_CONST__MASK				0xffffffff
6641 #define A6XX_SP_CS_TEX_CONST__SHIFT				0
6647 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }  in REG_A6XX_SP_CS_BINDLESS_BASE()
6649 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000a9e8 + 0…  in REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR()
6650 #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK	0x00000003
6651 #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT	0
6656 #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK		0xfffffffc
6663 #define REG_A6XX_SP_CS_IBO					0x0000a9f2
6664 #define A6XX_SP_CS_IBO__MASK					0xffffffff
6665 #define A6XX_SP_CS_IBO__SHIFT					0
6671 #define REG_A6XX_SP_CS_IBO_COUNT				0x0000aa00
6673 #define REG_A6XX_SP_MODE_CONTROL				0x0000ab00
6674 #define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE		0x00000001
6675 #define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK			0x00000006
6681 #define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE		0x00000008
6683 #define REG_A6XX_SP_FS_CONFIG					0x0000ab04
6684 #define A6XX_SP_FS_CONFIG_BINDLESS_TEX				0x00000001
6685 #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP				0x00000002
6686 #define A6XX_SP_FS_CONFIG_BINDLESS_IBO				0x00000004
6687 #define A6XX_SP_FS_CONFIG_BINDLESS_UBO				0x00000008
6688 #define A6XX_SP_FS_CONFIG_ENABLED				0x00000100
6689 #define A6XX_SP_FS_CONFIG_NTEX__MASK				0x0001fe00
6695 #define A6XX_SP_FS_CONFIG_NSAMP__MASK				0x003e0000
6701 #define A6XX_SP_FS_CONFIG_NIBO__MASK				0x1fc00000
6708 #define REG_A6XX_SP_FS_INSTRLEN					0x0000ab05
6710 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }  in REG_A6XX_SP_BINDLESS_BASE()
6712 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000ab10 + 0x2*…  in REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR()
6713 #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK	0x00000003
6714 #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT	0
6719 #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK		0xfffffffc
6726 #define REG_A6XX_SP_IBO						0x0000ab1a
6727 #define A6XX_SP_IBO__MASK					0xffffffff
6728 #define A6XX_SP_IBO__SHIFT					0
6734 #define REG_A6XX_SP_IBO_COUNT					0x0000ab20
6736 #define REG_A6XX_SP_2D_DST_FORMAT				0x0000acc0
6737 #define A6XX_SP_2D_DST_FORMAT_NORM				0x00000001
6738 #define A6XX_SP_2D_DST_FORMAT_SINT				0x00000002
6739 #define A6XX_SP_2D_DST_FORMAT_UINT				0x00000004
6740 #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK		0x000007f8
6746 #define A6XX_SP_2D_DST_FORMAT_SRGB				0x00000800
6747 #define A6XX_SP_2D_DST_FORMAT_MASK__MASK			0x0000f000
6754 #define REG_A6XX_SP_DBG_ECO_CNTL				0x0000ae00
6756 #define REG_A6XX_SP_ADDR_MODE_CNTL				0x0000ae01
6758 #define REG_A6XX_SP_NC_MODE_CNTL				0x0000ae02
6760 #define REG_A6XX_SP_CHICKEN_BITS				0x0000ae03
6762 #define REG_A6XX_SP_FLOAT_CNTL					0x0000ae04
6763 #define A6XX_SP_FLOAT_CNTL_F16_NO_INF				0x00000008
6765 #define REG_A6XX_SP_PERFCTR_ENABLE				0x0000ae0f
6766 #define A6XX_SP_PERFCTR_ENABLE_VS				0x00000001
6767 #define A6XX_SP_PERFCTR_ENABLE_HS				0x00000002
6768 #define A6XX_SP_PERFCTR_ENABLE_DS				0x00000004
6769 #define A6XX_SP_PERFCTR_ENABLE_GS				0x00000008
6770 #define A6XX_SP_PERFCTR_ENABLE_FS				0x00000010
6771 #define A6XX_SP_PERFCTR_ENABLE_CS				0x00000020
6773 static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; }  in REG_A6XX_SP_PERFCTR_SP_SEL()
6775 static inline uint32_t REG_A7XX_SP_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000ae60 + 0x1*i0; }  in REG_A7XX_SP_PERFCTR_HLSQ_SEL()
6777 #define REG_A7XX_SP_READ_SEL					0x0000ae6d
6779 static inline uint32_t REG_A7XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae80 + 0x1*i0; }  in REG_A7XX_SP_PERFCTR_SP_SEL()
6781 #define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE	0x0000be22
6783 #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR		0x0000b180
6784 #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK		0xffffffff
6785 #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT		0
6791 #define REG_A6XX_SP_UNKNOWN_B182				0x0000b182
6793 #define REG_A6XX_SP_UNKNOWN_B183				0x0000b183
6795 #define REG_A6XX_SP_UNKNOWN_B190				0x0000b190
6797 #define REG_A6XX_SP_UNKNOWN_B191				0x0000b191
6799 #define REG_A6XX_SP_TP_RAS_MSAA_CNTL				0x0000b300
6800 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
6801 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT			0
6806 #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK			0x0000000c
6813 #define REG_A6XX_SP_TP_DEST_MSAA_CNTL				0x0000b301
6814 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK			0x00000003
6815 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT		0
6820 #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004
6822 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR			0x0000b302
6823 #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK			0xffffffff
6824 #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT		0
6830 #define REG_A6XX_SP_TP_SAMPLE_CONFIG				0x0000b304
6831 #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0				0x00000001
6832 #define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE		0x00000002
6834 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_0			0x0000b305
6835 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK		0x0000000f
6836 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT		0
6841 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK		0x000000f0
6847 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK		0x00000f00
6853 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK		0x0000f000
6859 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK		0x000f0000
6865 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK		0x00f00000
6871 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK		0x0f000000
6877 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK		0xf0000000
6884 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1			0x0000b306
6885 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK		0x0000000f
6886 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT		0
6891 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK		0x000000f0
6897 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK		0x00000f00
6903 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK		0x0000f000
6909 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK		0x000f0000
6915 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK		0x00f00000
6921 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK		0x0f000000
6927 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK		0xf0000000
6934 #define REG_A6XX_SP_TP_WINDOW_OFFSET				0x0000b307
6935 #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK			0x00003fff
6936 #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT			0
6941 #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK			0x3fff0000
6948 #define REG_A6XX_SP_TP_MODE_CNTL				0x0000b309
6949 #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK			0x00000003
6950 #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT			0
6955 #define A6XX_SP_TP_MODE_CNTL_UNK3__MASK				0x000000fc
6962 #define REG_A6XX_SP_PS_2D_SRC_INFO				0x0000b4c0
6963 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK		0x000000ff
6964 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT		0
6969 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK			0x00000300
6975 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK			0x00000c00
6981 #define A6XX_SP_PS_2D_SRC_INFO_FLAGS				0x00001000
6982 #define A6XX_SP_PS_2D_SRC_INFO_SRGB				0x00002000
6983 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK			0x0000c000
6989 #define A6XX_SP_PS_2D_SRC_INFO_FILTER				0x00010000
6990 #define A6XX_SP_PS_2D_SRC_INFO_UNK17				0x00020000
6991 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE			0x00040000
6992 #define A6XX_SP_PS_2D_SRC_INFO_UNK19				0x00080000
6993 #define A6XX_SP_PS_2D_SRC_INFO_UNK20				0x00100000
6994 #define A6XX_SP_PS_2D_SRC_INFO_UNK21				0x00200000
6995 #define A6XX_SP_PS_2D_SRC_INFO_UNK22				0x00400000
6996 #define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK			0x07800000
7002 #define A6XX_SP_PS_2D_SRC_INFO_UNK28				0x10000000
7004 #define REG_A6XX_SP_PS_2D_SRC_SIZE				0x0000b4c1
7005 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK			0x00007fff
7006 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT			0
7011 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK			0x3fff8000
7018 #define REG_A6XX_SP_PS_2D_SRC					0x0000b4c2
7019 #define A6XX_SP_PS_2D_SRC__MASK					0xffffffff
7020 #define A6XX_SP_PS_2D_SRC__SHIFT				0
7026 #define REG_A6XX_SP_PS_2D_SRC_PITCH				0x0000b4c4
7027 #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK			0x000001ff
7028 #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT			0
7033 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK			0x00fffe00
7040 #define REG_A6XX_SP_PS_2D_SRC_PLANE1				0x0000b4c5
7041 #define A6XX_SP_PS_2D_SRC_PLANE1__MASK				0xffffffff
7042 #define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT				0
7048 #define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH			0x0000b4c7
7049 #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK			0x00000fff
7050 #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT			0
7056 #define REG_A6XX_SP_PS_2D_SRC_PLANE2				0x0000b4c8
7057 #define A6XX_SP_PS_2D_SRC_PLANE2__MASK				0xffffffff
7058 #define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT				0
7064 #define REG_A6XX_SP_PS_2D_SRC_FLAGS				0x0000b4ca
7065 #define A6XX_SP_PS_2D_SRC_FLAGS__MASK				0xffffffff
7066 #define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT				0
7072 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH			0x0000b4cc
7073 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK			0x000000ff
7074 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT			0
7080 #define REG_A6XX_SP_PS_UNKNOWN_B4CD				0x0000b4cd
7082 #define REG_A6XX_SP_PS_UNKNOWN_B4CE				0x0000b4ce
7084 #define REG_A6XX_SP_PS_UNKNOWN_B4CF				0x0000b4cf
7086 #define REG_A6XX_SP_PS_UNKNOWN_B4D0				0x0000b4d0
7088 #define REG_A6XX_SP_WINDOW_OFFSET				0x0000b4d1
7089 #define A6XX_SP_WINDOW_OFFSET_X__MASK				0x00003fff
7090 #define A6XX_SP_WINDOW_OFFSET_X__SHIFT				0
7095 #define A6XX_SP_WINDOW_OFFSET_Y__MASK				0x3fff0000
7102 #define REG_A6XX_TPL1_DBG_ECO_CNTL				0x0000b600
7104 #define REG_A6XX_TPL1_ADDR_MODE_CNTL				0x0000b601
7106 #define REG_A6XX_TPL1_UNKNOWN_B602				0x0000b602
7108 #define REG_A6XX_TPL1_NC_MODE_CNTL				0x0000b604
7109 #define A6XX_TPL1_NC_MODE_CNTL_MODE				0x00000001
7110 #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK			0x00000006
7116 #define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH		0x00000008
7117 #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK			0x00000010
7123 #define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK			0x000000c0
7130 #define REG_A6XX_TPL1_UNKNOWN_B605				0x0000b605
7132 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0			0x0000b608
7134 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1			0x0000b609
7136 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2			0x0000b60a
7138 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3			0x0000b60b
7140 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4			0x0000b60c
7142 static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; }  in REG_A6XX_TPL1_PERFCTR_TP_SEL()
7144 #define REG_A6XX_HLSQ_VS_CNTL					0x0000b800
7145 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK			0x000000ff
7146 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT			0
7151 #define A6XX_HLSQ_VS_CNTL_ENABLED				0x00000100
7153 #define REG_A6XX_HLSQ_HS_CNTL					0x0000b801
7154 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK			0x000000ff
7155 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT			0
7160 #define A6XX_HLSQ_HS_CNTL_ENABLED				0x00000100
7162 #define REG_A6XX_HLSQ_DS_CNTL					0x0000b802
7163 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK			0x000000ff
7164 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT			0
7169 #define A6XX_HLSQ_DS_CNTL_ENABLED				0x00000100
7171 #define REG_A6XX_HLSQ_GS_CNTL					0x0000b803
7172 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK			0x000000ff
7173 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT			0
7178 #define A6XX_HLSQ_GS_CNTL_ENABLED				0x00000100
7180 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD			0x0000b820
7182 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR		0x0000b821
7183 #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK		0xffffffff
7184 #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT		0
7190 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA			0x0000b823
7192 #define REG_A6XX_HLSQ_FS_CNTL_0					0x0000b980
7193 #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK			0x00000001
7194 #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT			0
7199 #define A6XX_HLSQ_FS_CNTL_0_VARYINGS				0x00000002
7200 #define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK				0x00000ffc
7207 #define REG_A6XX_HLSQ_UNKNOWN_B981				0x0000b981
7209 #define REG_A6XX_HLSQ_CONTROL_1_REG				0x0000b982
7211 #define REG_A7XX_HLSQ_CONTROL_1_REG				0x0000a9c7
7213 #define REG_A6XX_HLSQ_CONTROL_2_REG				0x0000b983
7214 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK			0x000000ff
7215 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT		0
7220 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK			0x0000ff00
7226 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK		0x00ff0000
7232 #define A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK			0xff000000
7239 #define REG_A7XX_HLSQ_CONTROL_2_REG				0x0000a9c8
7240 #define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK			0x000000ff
7241 #define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT		0
7246 #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK			0x0000ff00
7252 #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK		0x00ff0000
7258 #define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK			0xff000000
7265 #define REG_A6XX_HLSQ_CONTROL_3_REG				0x0000b984
7266 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK		0x000000ff
7267 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT		0
7272 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK		0x0000ff00
7278 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK		0x00ff0000
7284 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK	0xff000000
7291 #define REG_A7XX_HLSQ_CONTROL_3_REG				0x0000a9c9
7292 #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK		0x000000ff
7293 #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT		0
7298 #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK		0x0000ff00
7304 #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK		0x00ff0000
7310 #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK	0xff000000
7317 #define REG_A6XX_HLSQ_CONTROL_4_REG				0x0000b985
7318 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK		0x000000ff
7319 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT		0
7324 #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK		0x0000ff00
7330 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK		0x00ff0000
7336 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK		0xff000000
7343 #define REG_A7XX_HLSQ_CONTROL_4_REG				0x0000a9ca
7344 #define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK		0x000000ff
7345 #define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT		0
7350 #define A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK		0x0000ff00
7356 #define A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK		0x00ff0000
7362 #define A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK		0xff000000
7369 #define REG_A6XX_HLSQ_CONTROL_5_REG				0x0000b986
7370 #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK		0x000000ff
7371 #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT		0
7376 #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK	0x0000ff00
7383 #define REG_A7XX_HLSQ_CONTROL_5_REG				0x0000a9cb
7384 #define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK		0x000000ff
7385 #define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT		0
7390 #define A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK	0x0000ff00
7397 #define REG_A6XX_HLSQ_CS_CNTL					0x0000b987
7398 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK			0x000000ff
7399 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT			0
7404 #define A6XX_HLSQ_CS_CNTL_ENABLED				0x00000100
7406 #define REG_A6XX_HLSQ_CS_NDRANGE_0				0x0000b990
7407 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK			0x00000003
7408 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT			0
7413 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK			0x00000ffc
7419 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK			0x003ff000
7425 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK			0xffc00000
7432 #define REG_A6XX_HLSQ_CS_NDRANGE_1				0x0000b991
7433 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK		0xffffffff
7434 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT		0
7440 #define REG_A6XX_HLSQ_CS_NDRANGE_2				0x0000b992
7441 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK		0xffffffff
7442 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT		0
7448 #define REG_A6XX_HLSQ_CS_NDRANGE_3				0x0000b993
7449 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK		0xffffffff
7450 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT		0
7456 #define REG_A6XX_HLSQ_CS_NDRANGE_4				0x0000b994
7457 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK		0xffffffff
7458 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT		0
7464 #define REG_A6XX_HLSQ_CS_NDRANGE_5				0x0000b995
7465 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK		0xffffffff
7466 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT		0
7472 #define REG_A6XX_HLSQ_CS_NDRANGE_6				0x0000b996
7473 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK		0xffffffff
7474 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT		0
7480 #define REG_A6XX_HLSQ_CS_CNTL_0					0x0000b997
7481 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK			0x000000ff
7482 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT			0
7487 #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK			0x0000ff00
7493 #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK		0x00ff0000
7499 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK			0xff000000
7506 #define REG_A6XX_HLSQ_CS_CNTL_1					0x0000b998
7507 #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK		0x000000ff
7508 #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT		0
7513 #define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE			0x00000100
7514 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK			0x00000200
7520 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR			0x00000400
7522 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X				0x0000b999
7524 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y				0x0000b99a
7526 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z				0x0000b99b
7528 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD			0x0000b9a0
7530 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR		0x0000b9a1
7531 #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK		0xffffffff
7532 #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT		0
7538 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA			0x0000b9a3
7540 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }  in REG_A6XX_HLSQ_CS_BINDLESS_BASE()
7542 …ine uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }  in REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR()
7543 #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK	0x00000003
7544 #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT	0
7549 #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK	0xfffffffc
7556 #define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0				0x0000b9d0
7557 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK		0x0000001f
7558 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT		0
7563 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5				0x00000020
7564 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6				0x00000040
7566 #define REG_A6XX_HLSQ_DRAW_CMD					0x0000bb00
7567 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK			0x000000ff
7568 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT			0
7574 #define REG_A6XX_HLSQ_DISPATCH_CMD				0x0000bb01
7575 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK			0x000000ff
7576 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT			0
7582 #define REG_A6XX_HLSQ_EVENT_CMD					0x0000bb02
7583 #define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK			0x00ff0000
7589 #define A6XX_HLSQ_EVENT_CMD_EVENT__MASK				0x0000007f
7590 #define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT			0
7596 #define REG_A6XX_HLSQ_INVALIDATE_CMD				0x0000bb08
7597 #define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE			0x00000001
7598 #define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE			0x00000002
7599 #define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE			0x00000004
7600 #define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE			0x00000008
7601 #define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE			0x00000010
7602 #define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE			0x00000020
7603 #define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO				0x00000040
7604 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO			0x00000080
7605 #define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST		0x00080000
7606 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST		0x00000100
7607 #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK		0x00003e00
7613 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK		0x0007c000
7620 #define REG_A6XX_HLSQ_FS_CNTL					0x0000bb10
7621 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK			0x000000ff
7622 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT			0
7627 #define A6XX_HLSQ_FS_CNTL_ENABLED				0x00000100
7629 #define REG_A6XX_HLSQ_SHARED_CONSTS				0x0000bb11
7630 #define A6XX_HLSQ_SHARED_CONSTS_ENABLE				0x00000001
7632 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }  in REG_A6XX_HLSQ_BINDLESS_BASE()
7634 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000bb20 + 0x…  in REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR()
7635 #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK	0x00000003
7636 #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT	0
7641 #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK		0xfffffffc
7648 #define REG_A6XX_HLSQ_2D_EVENT_CMD				0x0000bd80
7649 #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK			0x0000ff00
7655 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK			0x0000007f
7656 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT			0
7662 #define REG_A6XX_HLSQ_UNKNOWN_BE00				0x0000be00
7664 #define REG_A6XX_HLSQ_UNKNOWN_BE01				0x0000be01
7666 #define REG_A6XX_HLSQ_DBG_ECO_CNTL				0x0000be04
7668 #define REG_A6XX_HLSQ_ADDR_MODE_CNTL				0x0000be05
7670 #define REG_A6XX_HLSQ_UNKNOWN_BE08				0x0000be08
7672 static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; }  in REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL()
7674 #define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE	0x0000be22
7676 #define REG_A7XX_SP_AHB_READ_APERTURE				0x0000c000
7678 #define REG_A6XX_CP_EVENT_START					0x0000d600
7679 #define A6XX_CP_EVENT_START_STATE_ID__MASK			0x000000ff
7680 #define A6XX_CP_EVENT_START_STATE_ID__SHIFT			0
7686 #define REG_A6XX_CP_EVENT_END					0x0000d601
7687 #define A6XX_CP_EVENT_END_STATE_ID__MASK			0x000000ff
7688 #define A6XX_CP_EVENT_END_STATE_ID__SHIFT			0
7694 #define REG_A6XX_CP_2D_EVENT_START				0x0000d700
7695 #define A6XX_CP_2D_EVENT_START_STATE_ID__MASK			0x000000ff
7696 #define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT			0
7702 #define REG_A6XX_CP_2D_EVENT_END				0x0000d701
7703 #define A6XX_CP_2D_EVENT_END_STATE_ID__MASK			0x000000ff
7704 #define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT			0
7710 #define REG_A6XX_TEX_SAMP_0					0x00000000
7711 #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR			0x00000001
7712 #define A6XX_TEX_SAMP_0_XY_MAG__MASK				0x00000006
7718 #define A6XX_TEX_SAMP_0_XY_MIN__MASK				0x00000018
7724 #define A6XX_TEX_SAMP_0_WRAP_S__MASK				0x000000e0
7730 #define A6XX_TEX_SAMP_0_WRAP_T__MASK				0x00000700
7736 #define A6XX_TEX_SAMP_0_WRAP_R__MASK				0x00003800
7742 #define A6XX_TEX_SAMP_0_ANISO__MASK				0x0001c000
7748 #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK				0xfff80000
7755 #define REG_A6XX_TEX_SAMP_1					0x00000001
7756 #define A6XX_TEX_SAMP_1_CLAMPENABLE				0x00000001
7757 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK			0x0000000e
7763 #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF			0x00000010
7764 #define A6XX_TEX_SAMP_1_UNNORM_COORDS				0x00000020
7765 #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR			0x00000040
7766 #define A6XX_TEX_SAMP_1_MAX_LOD__MASK				0x000fff00
7772 #define A6XX_TEX_SAMP_1_MIN_LOD__MASK				0xfff00000
7779 #define REG_A6XX_TEX_SAMP_2					0x00000002
7780 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK			0x00000003
7781 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT			0
7786 #define A6XX_TEX_SAMP_2_CHROMA_LINEAR				0x00000020
7787 #define A6XX_TEX_SAMP_2_BCOLOR__MASK				0xffffff80
7794 #define REG_A6XX_TEX_SAMP_3					0x00000003
7796 #define REG_A6XX_TEX_CONST_0					0x00000000
7797 #define A6XX_TEX_CONST_0_TILE_MODE__MASK			0x00000003
7798 #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT			0
7803 #define A6XX_TEX_CONST_0_SRGB					0x00000004
7804 #define A6XX_TEX_CONST_0_SWIZ_X__MASK				0x00000070
7810 #define A6XX_TEX_CONST_0_SWIZ_Y__MASK				0x00000380
7816 #define A6XX_TEX_CONST_0_SWIZ_Z__MASK				0x00001c00
7822 #define A6XX_TEX_CONST_0_SWIZ_W__MASK				0x0000e000
7828 #define A6XX_TEX_CONST_0_MIPLVLS__MASK				0x000f0000
7834 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X			0x00010000
7835 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y			0x00040000
7836 #define A6XX_TEX_CONST_0_SAMPLES__MASK				0x00300000
7842 #define A6XX_TEX_CONST_0_FMT__MASK				0x3fc00000
7848 #define A6XX_TEX_CONST_0_SWAP__MASK				0xc0000000
7855 #define REG_A6XX_TEX_CONST_1					0x00000001
7856 #define A6XX_TEX_CONST_1_WIDTH__MASK				0x00007fff
7857 #define A6XX_TEX_CONST_1_WIDTH__SHIFT				0
7862 #define A6XX_TEX_CONST_1_HEIGHT__MASK				0x3fff8000
7869 #define REG_A6XX_TEX_CONST_2					0x00000002
7870 #define A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK			0x0000fff0
7876 #define A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK		0x003f0000
7882 #define A6XX_TEX_CONST_2_PITCHALIGN__MASK			0x0000000f
7883 #define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT			0
7888 #define A6XX_TEX_CONST_2_PITCH__MASK				0x1fffff80
7894 #define A6XX_TEX_CONST_2_TYPE__MASK				0xe0000000
7901 #define REG_A6XX_TEX_CONST_3					0x00000003
7902 #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK			0x00003fff
7903 #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT			0
7908 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK			0x07800000
7914 #define A6XX_TEX_CONST_3_TILE_ALL				0x08000000
7915 #define A6XX_TEX_CONST_3_FLAG					0x10000000
7917 #define REG_A6XX_TEX_CONST_4					0x00000004
7918 #define A6XX_TEX_CONST_4_BASE_LO__MASK				0xffffffe0
7925 #define REG_A6XX_TEX_CONST_5					0x00000005
7926 #define A6XX_TEX_CONST_5_BASE_HI__MASK				0x0001ffff
7927 #define A6XX_TEX_CONST_5_BASE_HI__SHIFT				0
7932 #define A6XX_TEX_CONST_5_DEPTH__MASK				0x3ffe0000
7939 #define REG_A6XX_TEX_CONST_6					0x00000006
7940 #define A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK			0x00000fff
7941 #define A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT			0
7946 #define A6XX_TEX_CONST_6_PLANE_PITCH__MASK			0xffffff00
7953 #define REG_A6XX_TEX_CONST_7					0x00000007
7954 #define A6XX_TEX_CONST_7_FLAG_LO__MASK				0xffffffe0
7961 #define REG_A6XX_TEX_CONST_8					0x00000008
7962 #define A6XX_TEX_CONST_8_FLAG_HI__MASK				0x0001ffff
7963 #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT				0
7969 #define REG_A6XX_TEX_CONST_9					0x00000009
7970 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK		0x0001ffff
7971 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT		0
7977 #define REG_A6XX_TEX_CONST_10					0x0000000a
7978 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK		0x0000007f
7979 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT		0
7984 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK		0x00000f00
7990 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK		0x0000f000
7997 #define REG_A6XX_TEX_CONST_11					0x0000000b
7999 #define REG_A6XX_TEX_CONST_12					0x0000000c
8001 #define REG_A6XX_TEX_CONST_13					0x0000000d
8003 #define REG_A6XX_TEX_CONST_14					0x0000000e
8005 #define REG_A6XX_TEX_CONST_15					0x0000000f
8007 #define REG_A6XX_UBO_0						0x00000000
8008 #define A6XX_UBO_0_BASE_LO__MASK				0xffffffff
8009 #define A6XX_UBO_0_BASE_LO__SHIFT				0
8015 #define REG_A6XX_UBO_1						0x00000001
8016 #define A6XX_UBO_1_BASE_HI__MASK				0x0001ffff
8017 #define A6XX_UBO_1_BASE_HI__SHIFT				0
8022 #define A6XX_UBO_1_SIZE__MASK					0xfffe0000
8029 #define REG_A6XX_PDC_GPU_ENABLE_PDC				0x00001140
8031 #define REG_A6XX_PDC_GPU_SEQ_START_ADDR				0x00001148
8033 #define REG_A6XX_PDC_GPU_TCS0_CONTROL				0x00001540
8035 #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK			0x00001541
8037 #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK		0x00001542
8039 #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID			0x00001543
8041 #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR				0x00001544
8043 #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA				0x00001545
8045 #define REG_A6XX_PDC_GPU_TCS1_CONTROL				0x00001572
8047 #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK			0x00001573
8049 #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK		0x00001574
8051 #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID			0x00001575
8053 #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR				0x00001576
8055 #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA				0x00001577
8057 #define REG_A6XX_PDC_GPU_TCS2_CONTROL				0x000015a4
8059 #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK			0x000015a5
8061 #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK		0x000015a6
8063 #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID			0x000015a7
8065 #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR				0x000015a8
8067 #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA				0x000015a9
8069 #define REG_A6XX_PDC_GPU_TCS3_CONTROL				0x000015d6
8071 #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK			0x000015d7
8073 #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK		0x000015d8
8075 #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID			0x000015d9
8077 #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR				0x000015da
8079 #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA				0x000015db
8081 #define REG_A6XX_PDC_GPU_SEQ_MEM_0				0x00000000
8083 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A			0x00000000
8084 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK		0x000000ff
8085 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT		0
8090 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK	0x0000ff00
8097 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B			0x00000001
8099 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C			0x00000002
8101 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D			0x00000003
8103 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT			0x00000004
8104 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK		0x0000003f
8105 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT		0
8110 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK		0x00007000
8116 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK		0xf0000000
8123 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM			0x00000005
8124 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK		0x0f000000
8131 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0			0x00000008
8133 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1			0x00000009
8135 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2			0x0000000a
8137 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3			0x0000000b
8139 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0			0x0000000c
8141 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1			0x0000000d
8143 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2			0x0000000e
8145 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3			0x0000000f
8147 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0			0x00000010
8148 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK		0x0000000f
8149 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT		0
8154 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK		0x000000f0
8160 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK		0x00000f00
8166 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK		0x0000f000
8172 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK		0x000f0000
8178 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK		0x00f00000
8184 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK		0x0f000000
8190 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK		0xf0000000
8197 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1			0x00000011
8198 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK		0x0000000f
8199 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT		0
8204 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK		0x000000f0
8210 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK		0x00000f00
8216 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK		0x0000f000
8222 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK		0x000f0000
8228 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK		0x00f00000
8234 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK		0x0f000000
8240 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK		0xf0000000
8247 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1			0x0000002f
8249 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2			0x00000030
8251 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0			0x00000001
8253 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1			0x00000002