121 	gpu_write(gpu, REG_AXXX_CP_ME_CNTL, AXXX_CP_ME_CNTL_HALT);  in a2xx_hw_init()
123 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE1, 0xfffffffe);  in a2xx_hw_init()
124 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, 0xffffffff);  in a2xx_hw_init()
127 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0xffffffff);  in a2xx_hw_init()
129 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0x00000000);  in a2xx_hw_init()
132 		gpu_write(gpu, REG_A2XX_SQ_FLOW_CONTROL, 0x18000000);  in a2xx_hw_init()
135 	gpu_write(gpu, REG_A2XX_RBBM_CNTL, 0x00004442);  in a2xx_hw_init()
138 	gpu_write(gpu, REG_A2XX_MH_MMU_MPU_BASE, 0x00000000);  in a2xx_hw_init()
139 	gpu_write(gpu, REG_A2XX_MH_MMU_MPU_END, 0xfffff000);  in a2xx_hw_init()
141 	gpu_write(gpu, REG_A2XX_MH_MMU_CONFIG, A2XX_MH_MMU_CONFIG_MMU_ENABLE |  in a2xx_hw_init()
155 	gpu_write(gpu, REG_A2XX_MH_MMU_VA_RANGE, SZ_16M |  in a2xx_hw_init()
158 	gpu_write(gpu, REG_A2XX_MH_MMU_PT_BASE, pt_base);  in a2xx_hw_init()
159 	gpu_write(gpu, REG_A2XX_MH_MMU_TRAN_ERROR, tran_error);  in a2xx_hw_init()
161 	gpu_write(gpu, REG_A2XX_MH_MMU_INVALIDATE,  in a2xx_hw_init()
165 	gpu_write(gpu, REG_A2XX_MH_ARBITER_CONFIG,  in a2xx_hw_init()
180 		gpu_write(gpu, REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1, 0x00032f07);  in a2xx_hw_init()
182 	gpu_write(gpu, REG_A2XX_SQ_VS_PROGRAM, 0x00000000);  in a2xx_hw_init()
183 	gpu_write(gpu, REG_A2XX_SQ_PS_PROGRAM, 0x00000000);  in a2xx_hw_init()
185 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE1, 0); /* 0x200 for msm8960? */  in a2xx_hw_init()
186 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, 0); /* 0x80/0x1a0 for a22x? */  in a2xx_hw_init()
189 	gpu_write(gpu, REG_A2XX_RBBM_DEBUG, 0x00080000);  in a2xx_hw_init()
191 	gpu_write(gpu, REG_A2XX_RBBM_INT_CNTL,  in a2xx_hw_init()
193 	gpu_write(gpu, REG_AXXX_CP_INT_CNTL,  in a2xx_hw_init()
201 	gpu_write(gpu, REG_A2XX_SQ_INT_CNTL, 0);  in a2xx_hw_init()
202 	gpu_write(gpu, REG_A2XX_MH_INTERRUPT_MASK,  in a2xx_hw_init()
210 	gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i);  in a2xx_hw_init()
216 	gpu_write(gpu, REG_AXXX_CP_RB_CNTL,  in a2xx_hw_init()
219 	gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));  in a2xx_hw_init()
243 	gpu_write(gpu, REG_AXXX_CP_DEBUG,  in a2xx_hw_init()
245 	gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0);  in a2xx_hw_init()
247 		gpu_write(gpu, REG_AXXX_CP_ME_RAM_DATA, ptr[i]);  in a2xx_hw_init()
254 	gpu_write(gpu, REG_A2XX_CP_PFP_UCODE_ADDR, 0);  in a2xx_hw_init()
256 		gpu_write(gpu, REG_A2XX_CP_PFP_UCODE_DATA, ptr[i]);  in a2xx_hw_init()
258 	gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x000C0804);  in a2xx_hw_init()
261 	gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0);  in a2xx_hw_init()
281 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 1);  in a2xx_recover()
283 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0);  in a2xx_recover()
330 		gpu_write(gpu, REG_A2XX_MH_INTERRUPT_CLEAR, status);  in a2xx_irq()
340 		gpu_write(gpu, REG_AXXX_CP_INT_ACK, status);  in a2xx_irq()
348 		gpu_write(gpu, REG_A2XX_RBBM_INT_ACK, status);  in a2xx_irq()