46 #define DISP_REG_OVL_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n))  argument
47 #define DISP_REG_OVL_HDR_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n) + 0x04)  argument
48 #define DISP_REG_OVL_HDR_PITCH(ovl, n)		((ovl)->data->addr + 0x20 * (n) + 0x08)  argument
61 #define OVL_CON_CLRFMT_RGB565(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \  argument
63 #define OVL_CON_CLRFMT_RGB888(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \  argument
65 #define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl)	(0xFF << 4 * (ovl))  argument
66 #define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl)	(depth << 4 * (ovl))  argument
150 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_register_vblank_cb()  local
152 	ovl->vblank_cb = vblank_cb;  in mtk_ovl_register_vblank_cb()
153 	ovl->vblank_cb_data = vblank_cb_data;  in mtk_ovl_register_vblank_cb()
158 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_unregister_vblank_cb()  local
160 	ovl->vblank_cb = NULL;  in mtk_ovl_unregister_vblank_cb()
161 	ovl->vblank_cb_data = NULL;  in mtk_ovl_unregister_vblank_cb()
166 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_enable_vblank()  local
168 	writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);  in mtk_ovl_enable_vblank()
169 	writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN);  in mtk_ovl_enable_vblank()
174 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_disable_vblank()  local
176 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);  in mtk_ovl_disable_vblank()
181 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_get_formats()  local
183 	return ovl->data->formats;  in mtk_ovl_get_formats()
188 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_get_num_formats()  local
190 	return ovl->data->num_formats;  in mtk_ovl_get_num_formats()
195 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_clk_enable()  local
197 	return clk_prepare_enable(ovl->clk);  in mtk_ovl_clk_enable()
202 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_clk_disable()  local
204 	clk_disable_unprepare(ovl->clk);  in mtk_ovl_clk_disable()
209 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_start()  local
211 	if (ovl->data->smi_id_en) {  in mtk_ovl_start()
214 		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_start()
216 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_start()
218 	writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);  in mtk_ovl_start()
223 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_stop()  local
225 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);  in mtk_ovl_stop()
226 	if (ovl->data->smi_id_en) {  in mtk_ovl_stop()
229 		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_stop()
231 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_stop()
235 static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt,  in mtk_ovl_set_afbc()  argument
239 			   &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_set_afbc()
246 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_set_bit_depth()  local
250 	if (!ovl->data->supports_clrfmt_ext)  in mtk_ovl_set_bit_depth()
253 	reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT);  in mtk_ovl_set_bit_depth()
263 	mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg,  in mtk_ovl_set_bit_depth()
264 		      ovl->regs, DISP_REG_OVL_CLRFMT_EXT);  in mtk_ovl_set_bit_depth()
271 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_config()  local
274 		mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_config()
276 	mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR);  in mtk_ovl_config()
278 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);  in mtk_ovl_config()
279 	mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);  in mtk_ovl_config()
284 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_layer_nr()  local
286 	return ovl->data->layer_nr;  in mtk_ovl_layer_nr()
329 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_layer_on()  local
331 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_on()
334 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);  in mtk_ovl_layer_on()
336 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);  in mtk_ovl_layer_on()
337 	if (ovl->data->gmc_bits == 10)  in mtk_ovl_layer_on()
343 		      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));  in mtk_ovl_layer_on()
344 	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_on()
351 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_layer_off()  local
353 	mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_off()
355 	mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_off()
359 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)  in ovl_fmt_convert()  argument
369 		return OVL_CON_CLRFMT_RGB565(ovl);  in ovl_fmt_convert()
371 		return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP;  in ovl_fmt_convert()
373 		return OVL_CON_CLRFMT_RGB888(ovl);  in ovl_fmt_convert()
375 		return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;  in ovl_fmt_convert()
401 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_layer_config()  local
427 	con = ovl_fmt_convert(ovl, fmt);  in mtk_ovl_layer_config()
441 	if (ovl->data->supports_afbc)  in mtk_ovl_layer_config()
442 		mtk_ovl_set_afbc(ovl, cmdq_pkt, idx, is_afbc);  in mtk_ovl_layer_config()
444 	mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
446 	mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
448 	mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
450 	mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
452 	mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
453 			      DISP_REG_OVL_ADDR(ovl, idx));  in mtk_ovl_layer_config()
456 		mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
457 				      DISP_REG_OVL_HDR_ADDR(ovl, idx));  in mtk_ovl_layer_config()
460 				      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));  in mtk_ovl_layer_config()
461 		mtk_ddp_write_relaxed(cmdq_pkt, hdr_pitch, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
462 				      DISP_REG_OVL_HDR_PITCH(ovl, idx));  in mtk_ovl_layer_config()
466 				      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));  in mtk_ovl_layer_config()
475 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_bgclr_in_on()  local
478 	reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_on()
480 	writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_on()
485 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_bgclr_in_off()  local
488 	reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_off()
490 	writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_off()