Lines Matching refs:lsdc_wreg32
35 lsdc_wreg32(ldev, LSDC_CRTC0_CFG_REG, val); in lsdc_crtc0_soft_reset()
41 lsdc_wreg32(ldev, LSDC_CRTC0_CFG_REG, val); in lsdc_crtc0_soft_reset()
61 lsdc_wreg32(ldev, LSDC_CRTC1_CFG_REG, val); in lsdc_crtc1_soft_reset()
67 lsdc_wreg32(ldev, LSDC_CRTC1_CFG_REG, val); in lsdc_crtc1_soft_reset()
90 lsdc_wreg32(ldev, LSDC_CRTC0_CFG_REG, val | CFG_OUTPUT_ENABLE); in lsdc_crtc0_enable()
118 lsdc_wreg32(ldev, LSDC_CRTC1_CFG_REG, val | CFG_OUTPUT_ENABLE); in lsdc_crtc1_enable()
222 lsdc_wreg32(ldev, LSDC_CRTC0_HDISPLAY_REG, in lsdc_crtc0_set_mode()
225 lsdc_wreg32(ldev, LSDC_CRTC0_VDISPLAY_REG, in lsdc_crtc0_set_mode()
228 lsdc_wreg32(ldev, LSDC_CRTC0_HSYNC_REG, in lsdc_crtc0_set_mode()
231 lsdc_wreg32(ldev, LSDC_CRTC0_VSYNC_REG, in lsdc_crtc0_set_mode()
240 lsdc_wreg32(ldev, LSDC_CRTC1_HDISPLAY_REG, in lsdc_crtc1_set_mode()
243 lsdc_wreg32(ldev, LSDC_CRTC1_VDISPLAY_REG, in lsdc_crtc1_set_mode()
246 lsdc_wreg32(ldev, LSDC_CRTC1_HSYNC_REG, in lsdc_crtc1_set_mode()
249 lsdc_wreg32(ldev, LSDC_CRTC1_VSYNC_REG, in lsdc_crtc1_set_mode()
268 lsdc_wreg32(ldev, LSDC_CRTC0_CFG_REG, CFG_RESET_N | LSDC_PF_XRGB8888); in lsdc_crtc0_reset()
275 lsdc_wreg32(ldev, LSDC_CRTC1_CFG_REG, CFG_RESET_N | LSDC_PF_XRGB8888); in lsdc_crtc1_reset()
343 lsdc_wreg32(ldev, LSDC_CRTC0_CFG_REG, val); in lsdc_crtc0_set_dma_step()
355 lsdc_wreg32(ldev, LSDC_CRTC1_CFG_REG, val); in lsdc_crtc1_set_dma_step()