68 	.active_lanes = MIPI_TX_ACTIVE_LANES,
515 	    ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes);  in mipi_tx_fg_cfg_regs()
520 		 fg_cfg->active_lanes);  in mipi_tx_fg_cfg_regs()
568 	    ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes);  in mipi_tx_fg_cfg_regs()
587 			   u8 active_lanes, u32 bpp, u32 wc,  in mipi_tx_fg_cfg()  argument
611 	fg_t_cfg.active_lanes = active_lanes;  in mipi_tx_fg_cfg()
618 					  u8 active_lanes, u8 vchannel_id)  in mipi_tx_multichannel_fifo_cfg()  argument
630 	fifo_size = ((active_lanes > MIPI_D_LANES_PER_DPHY) ?  in mipi_tx_multichannel_fifo_cfg()
693 	ctrl |= ACTIVE_LANES(ctrl_cfg->active_lanes - 1);  in mipi_tx_ctrl_cfg()
748 		mipi_tx_fg_cfg(kmb_dsi, frame_id, ctrl_cfg->active_lanes,  in mipi_tx_init_cntrl()
763 	mipi_tx_multichannel_fifo_cfg(kmb_dsi, ctrl_cfg->active_lanes, frame_id);  in mipi_tx_init_cntrl()
1120 			       int active_lanes, enum dphy_mode mode)  in dphy_init_sequence()  argument
1202 			    ((1 << active_lanes) - 1));  in dphy_init_sequence()
1239 			   u32 active_lanes)  in wait_init_done()  argument
1242 	u32 data_lanes = (1 << active_lanes) - 1;  in wait_init_done()
1291 	if (cfg->active_lanes > MIPI_DPHY_D_LANES) {  in mipi_tx_init_dphy()
1309 				   (cfg->active_lanes - MIPI_DPHY_D_LANES),  in mipi_tx_init_dphy()
1320 			       cfg->active_lanes - MIPI_DPHY_D_LANES);  in mipi_tx_init_dphy()
1325 		dphy_init_sequence(kmb_dsi, cfg, dphy_no, cfg->active_lanes,  in mipi_tx_init_dphy()
1328 		wait_init_done(kmb_dsi, dphy_no, cfg->active_lanes);  in mipi_tx_init_dphy()
1361 	mipi_tx_init_cfg.active_lanes = MIPI_TX_ACTIVE_LANES;  in kmb_dsi_mode_set()
1383 			MIPI_TX_BPP) / mipi_tx_init_cfg.active_lanes) /	1000000;  in kmb_dsi_mode_set()
1386 		(u32)data_rate, mipi_tx_init_cfg.active_lanes);  in kmb_dsi_mode_set()
1392 		mipi_tx_init_cfg.active_lanes = 2;  in kmb_dsi_mode_set()