65 		void *p_data, unsigned int bytes, bool read)  in failsafe_emulate_mmio_rw()  argument
80 					bytes);  in failsafe_emulate_mmio_rw()
83 					bytes);  in failsafe_emulate_mmio_rw()
88 			memcpy(p_data, pt, bytes);  in failsafe_emulate_mmio_rw()
90 			memcpy(pt, p_data, bytes);  in failsafe_emulate_mmio_rw()
107 		void *p_data, unsigned int bytes)  in intel_vgpu_emulate_mmio_read()  argument
115 		failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);  in intel_vgpu_emulate_mmio_read()
122 	if (drm_WARN_ON(&i915->drm, bytes > 8))  in intel_vgpu_emulate_mmio_read()
129 		if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8))  in intel_vgpu_emulate_mmio_read()
132 				!reg_is_gtt(gvt, offset + bytes - 1)))  in intel_vgpu_emulate_mmio_read()
136 				p_data, bytes);  in intel_vgpu_emulate_mmio_read()
143 		ret = intel_gvt_read_gpa(vgpu, pa, p_data, bytes);  in intel_vgpu_emulate_mmio_read()
147 	if (drm_WARN_ON(&i915->drm, !reg_is_mmio(gvt, offset + bytes - 1)))  in intel_vgpu_emulate_mmio_read()
151 		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, bytes)))  in intel_vgpu_emulate_mmio_read()
155 	ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);  in intel_vgpu_emulate_mmio_read()
165 			offset, bytes);  in intel_vgpu_emulate_mmio_read()
182 		void *p_data, unsigned int bytes)  in intel_vgpu_emulate_mmio_write()  argument
190 		failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false);  in intel_vgpu_emulate_mmio_write()
198 	if (drm_WARN_ON(&i915->drm, bytes > 8))  in intel_vgpu_emulate_mmio_write()
205 		if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8))  in intel_vgpu_emulate_mmio_write()
208 				!reg_is_gtt(gvt, offset + bytes - 1)))  in intel_vgpu_emulate_mmio_write()
212 				p_data, bytes);  in intel_vgpu_emulate_mmio_write()
219 		ret = intel_gvt_write_gpa(vgpu, pa, p_data, bytes);  in intel_vgpu_emulate_mmio_write()
223 	ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);  in intel_vgpu_emulate_mmio_write()
232 		     bytes);  in intel_vgpu_emulate_mmio_write()