74 			struct vfio_region *region);
404 	void *base = vgpu->region[i].data;  in intel_vgpu_reg_rw_opregion()
408 	if (pos >= vgpu->region[i].size || iswrite) {  in intel_vgpu_reg_rw_opregion()
412 	count = min(count, (size_t)(vgpu->region[i].size - pos));  in intel_vgpu_reg_rw_opregion()
419 		struct vfio_region *region)  in intel_vgpu_reg_release_opregion()  argument
429 			struct vfio_edid_region *region, char *buf,  in handle_edid_regs()  argument
432 	struct vfio_region_gfx_edid *regs = &region->vfio_edid_regs;  in handle_edid_regs()
447 					(u8 *)region->edid_blob,  in handle_edid_regs()
485 static int handle_edid_blob(struct vfio_edid_region *region, char *buf,  in handle_edid_blob()  argument
488 	if (offset + count > region->vfio_edid_regs.edid_size)  in handle_edid_blob()
492 		memcpy(region->edid_blob + offset, buf, count);  in handle_edid_blob()
494 		memcpy(buf, region->edid_blob + offset, count);  in handle_edid_blob()
505 	struct vfio_edid_region *region = vgpu->region[i].data;  in intel_vgpu_reg_rw_edid()  local
508 	if (pos < region->vfio_edid_regs.edid_offset) {  in intel_vgpu_reg_rw_edid()
509 		ret = handle_edid_regs(vgpu, region, buf, count, pos, iswrite);  in intel_vgpu_reg_rw_edid()
512 		ret = handle_edid_blob(region, buf, count, pos, iswrite);  in intel_vgpu_reg_rw_edid()
522 					struct vfio_region *region)  in intel_vgpu_reg_release_edid()  argument
524 	kfree(region->data);  in intel_vgpu_reg_release_edid()
537 	struct vfio_region *region;  in intel_vgpu_register_reg()  local
539 	region = krealloc(vgpu->region,  in intel_vgpu_register_reg()
540 			(vgpu->num_regions + 1) * sizeof(*region),  in intel_vgpu_register_reg()
542 	if (!region)  in intel_vgpu_register_reg()
545 	vgpu->region = region;  in intel_vgpu_register_reg()
546 	vgpu->region[vgpu->num_regions].type = type;  in intel_vgpu_register_reg()
547 	vgpu->region[vgpu->num_regions].subtype = subtype;  in intel_vgpu_register_reg()
548 	vgpu->region[vgpu->num_regions].ops = ops;  in intel_vgpu_register_reg()
549 	vgpu->region[vgpu->num_regions].size = size;  in intel_vgpu_register_reg()
550 	vgpu->region[vgpu->num_regions].flags = flags;  in intel_vgpu_register_reg()
551 	vgpu->region[vgpu->num_regions].data = data;  in intel_vgpu_register_reg()
597 	base->vfio_edid_regs.max_xres = vgpu_edid_xres(port->id);  in intel_gvt_set_edid()
598 	base->vfio_edid_regs.max_yres = vgpu_edid_yres(port->id);  in intel_gvt_set_edid()
636 	int id;  in __kvmgt_vgpu_exist()  local
640 	for_each_active_vgpu(vgpu->gvt, itr, id) {  in __kvmgt_vgpu_exist()
832 		return vgpu->region[index].ops->rw(vgpu, buf, count,  in intel_vgpu_rw()
1141 	gvt_dbg_core("vgpu%d ioctl, cmd: %d\n", vgpu->id, cmd);  in intel_vgpu_ioctl()
1216 			sparse->header.id = VFIO_REGION_INFO_CAP_SPARSE_MMAP;  in intel_vgpu_ioctl()
1244 					.header.id = VFIO_REGION_INFO_CAP_TYPE,  in intel_vgpu_ioctl()
1259 				info.size = vgpu->region[i].size;  in intel_vgpu_ioctl()
1260 				info.flags = vgpu->region[i].flags;  in intel_vgpu_ioctl()
1262 				cap_type.type = vgpu->region[i].type;  in intel_vgpu_ioctl()
1263 				cap_type.subtype = vgpu->region[i].subtype;  in intel_vgpu_ioctl()
1415 	return sprintf(buf, "%d\n", vgpu->id);  in vgpu_id_show()
1427 	.attrs = intel_vgpu_attrs,
1617 	if (!vgpu->region)  in intel_vgpu_detach_regions()
1621 		if (vgpu->region[i].ops->release)  in intel_vgpu_detach_regions()
1622 			vgpu->region[i].ops->release(vgpu,  in intel_vgpu_detach_regions()
1623 					&vgpu->region[i]);  in intel_vgpu_detach_regions()
1625 	kfree(vgpu->region);  in intel_vgpu_detach_regions()
1626 	vgpu->region = NULL;  in intel_vgpu_detach_regions()
1739 	int id;  in intel_gvt_test_and_emulate_vblank()  local
1742 	idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) {  in intel_gvt_test_and_emulate_vblank()
1743 		if (test_and_clear_bit(INTEL_GVT_REQUEST_EMULATE_VBLANK + id,  in intel_gvt_test_and_emulate_vblank()