Lines Matching +full:0 +full:xcfff
129 enum forcewake_domains fw = 0; in wal_get_fw_for_rmw()
133 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in wal_get_fw_for_rmw()
146 unsigned int start = 0, end = wal->count; in _wa_add()
202 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == in _wa_add()
205 i915_mmio_reg_offset(wa_[0].reg)) in _wa_add()
208 swap(wa_[1], wa_[0]); in _wa_add()
256 wa_write_clr_set(wal, reg, ~0, set); in wa_write()
262 wa_mcr_write_clr_set(wal, reg, ~0, set); in wa_mcr_write()
280 wa_write_clr_set(wal, reg, clr, 0); in wa_write_clr()
286 wa_mcr_write_clr_set(wal, reg, clr, 0); in wa_mcr_write_clr()
303 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_masked_en()
309 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_mcr_masked_en()
315 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); in wa_masked_dis()
321 wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); in wa_mcr_masked_dis()
328 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); in wa_masked_field_set()
335 wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); in wa_mcr_masked_field_set()
423 (IS_BROADWELL_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); in bdw_ctx_workarounds_init()
538 u8 vals[3] = { 0, 0, 0 }; in skl_tune_iz_hashing()
541 for (i = 0; i < 3; i++) { in skl_tune_iz_hashing()
552 * subslice_7eu[i] != 0 (because of the check above) and in skl_tune_iz_hashing()
555 * -> 0 <= ss <= 3; in skl_tune_iz_hashing()
561 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) in skl_tune_iz_hashing()
568 GEN9_IZ_HASHING_MASK(0), in skl_tune_iz_hashing()
571 GEN9_IZ_HASHING(0, vals[0])); in skl_tune_iz_hashing()
652 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, in icl_ctx_workarounds_init()
654 0 /* write-only, so skip validation */, in icl_ctx_workarounds_init()
667 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); in icl_ctx_workarounds_init()
669 0, in icl_ctx_workarounds_init()
670 0xFFFFFFFF); in icl_ctx_workarounds_init()
685 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); in dg2_ctx_gt_tuning_init()
730 * the clear mask is just set to ~0 to make sure other bits are not in gen12_ctx_workarounds_init()
735 ~0, in gen12_ctx_workarounds_init()
737 0, false); in gen12_ctx_workarounds_init()
794 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); in dg2_ctx_workarounds_init()
817 wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false); in mtl_ctx_gt_tuning_init()
831 PREEMPTION_VERTEX_COUNT, 0x4000); in mtl_ctx_workarounds_init()
991 if (wal->count == 0) in intel_engine_emit_ctx_wa()
992 return 0; in intel_engine_emit_ctx_wa()
1009 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in intel_engine_emit_ctx_wa()
1038 return 0; in intel_engine_emit_ctx_wa()
1107 HSW_ROW_CHICKEN3, 0, in hsw_gt_workarounds_init()
1109 0 /* XXX does this reg exist? */, true); in hsw_gt_workarounds_init()
1207 if (IS_KABYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) in kbl_gt_workarounds_init()
1291 * one of the higher subslices, we run the risk of reading back 0's or in icl_wa_init_mcr()
1294 subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0)); in icl_wa_init_mcr()
1304 __add_mcr_wa(gt, wal, 0, subslice); in icl_wa_init_mcr()
1311 unsigned long slice, subslice = 0, slice_mask = 0; in xehp_init_mcr()
1312 u32 lncf_mask = 0; in xehp_init_mcr()
1350 lncf_mask |= (0x3 << (i * 2)); in xehp_init_mcr()
1367 if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0)) in xehp_init_mcr()
1385 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); in xehp_init_mcr()
1386 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); in xehp_init_mcr()
1393 __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0); in xehp_init_mcr()
1406 dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0); in pvc_init_mcr()
1519 0, 0, false); in gen12_gt_workarounds_init()
1888 "%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", in wa_verify()
1916 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_apply()
1917 u32 val, old = 0; in wa_list_apply()
1968 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in wa_list_verify()
2183 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), in icl_whitelist_build()
2186 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), in icl_whitelist_build()
2189 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), in icl_whitelist_build()
2278 * Prevent read/write access to [0x4400, 0x4600) which covers in blacklist_trtt()
2283 whitelist_reg_ext(w, _MMIO(0x4400), in blacklist_trtt()
2286 whitelist_reg_ext(w, _MMIO(0x4500), in blacklist_trtt()
2362 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in intel_engine_apply_whitelist()
2403 * Even on the few platforms where MOCS 0 is a in engine_fake_wa_init()
2408 drm_WARN_ON(&engine->i915->drm, mocs_r == 0); in engine_fake_wa_init()
2420 return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >= in needs_wa_1308578152()
2511 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, in rcs_engine_wa_init()
2513 0 /* Wa_14012342262 write-only reg, so skip verification */, in rcs_engine_wa_init()
2621 0); in rcs_engine_wa_init()
2648 * kernel-only register CS_DEBUG_MODE1 (0x20EC). Any granularity in rcs_engine_wa_init()
2654 * register CS_CHICKEN1 (0x2580). CS_CHICKEN1 is saved/restored on in rcs_engine_wa_init()
2681 * CS_CHICKEN1[0] does not disable object-level preemption as in rcs_engine_wa_init()
2682 * it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been in rcs_engine_wa_init()
2743 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); in rcs_engine_wa_init()
2745 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); in rcs_engine_wa_init()
2747 EVICTION_PERF_FIX_ENABLE, 0); in rcs_engine_wa_init()
2794 if (0) { /* causes HiZ corruption on ivb:gt1 */ in rcs_engine_wa_init()
2922 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), in rcs_engine_wa_init()
2924 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); in rcs_engine_wa_init()
2938 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), in rcs_engine_wa_init()
2939 0 /* XXX bit doesn't stick on Broadwater */, in rcs_engine_wa_init()
3094 * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, in general_render_compute_wa_init()
3097 wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, in general_render_compute_wa_init()
3099 0, false); in general_render_compute_wa_init()
3138 * Note that register 0xE420 is write-only and cannot be read in general_render_compute_wa_init()
3142 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, in general_render_compute_wa_init()
3144 0 /* write-only, so skip validation */, in general_render_compute_wa_init()
3187 { .start = 0x5500, .end = 0x55ff },
3188 { .start = 0x7000, .end = 0x7fff },
3189 { .start = 0x9400, .end = 0x97ff },
3190 { .start = 0xb000, .end = 0xb3ff },
3191 { .start = 0xe000, .end = 0xe7ff },
3196 { .start = 0x8150, .end = 0x815f },
3197 { .start = 0x9520, .end = 0x955f },
3198 { .start = 0xb100, .end = 0xb3ff },
3199 { .start = 0xde80, .end = 0xe8ff },
3200 { .start = 0x24a00, .end = 0x24a7f },
3205 { .start = 0x4000, .end = 0x4aff },
3206 { .start = 0x5200, .end = 0x52ff },
3207 { .start = 0x5400, .end = 0x7fff },
3208 { .start = 0x8140, .end = 0x815f },
3209 { .start = 0x8c80, .end = 0x8dff },
3210 { .start = 0x94d0, .end = 0x955f },
3211 { .start = 0x9680, .end = 0x96ff },
3212 { .start = 0xb000, .end = 0xb3ff },
3213 { .start = 0xc800, .end = 0xcfff },
3214 { .start = 0xd800, .end = 0xd8ff },
3215 { .start = 0xdc00, .end = 0xffff },
3216 { .start = 0x17000, .end = 0x17fff },
3217 { .start = 0x24a00, .end = 0x24a7f },
3240 for (i = 0; mcr_ranges[i].start; i++) in mcr_range()
3254 unsigned int i, count = 0; in wa_list_srm()
3262 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_srm()
3271 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_srm()
3280 *cs++ = 0; in wa_list_srm()
3284 return 0; in wa_list_srm()
3300 return 0; in engine_wa_list_verify()
3311 if (err == 0) in engine_wa_list_verify()
3316 err = i915_vma_pin_ww(vma, &ww, 0, 0, in engine_wa_list_verify()
3328 if (err == 0) in engine_wa_list_verify()
3339 if (i915_request_wait(rq, 0, HZ / 5) < 0) { in engine_wa_list_verify()
3350 err = 0; in engine_wa_list_verify()
3351 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in engine_wa_list_verify()