Lines Matching full:engine
260 * intel_engine_context_size() - return the size of the context for an engine
262 * @class: engine class
264 * Each engine class may require a different amount of space for a context
267 * Return: size (in bytes) of an engine class specific context image
359 static void __sprint_engine_name(struct intel_engine_cs *engine) in __sprint_engine_name() argument
362 * Before we know what the uABI name for this engine will be, in __sprint_engine_name()
363 * we still would like to keep track of this engine in the debug logs. in __sprint_engine_name()
366 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u", in __sprint_engine_name()
367 intel_engine_class_repr(engine->class), in __sprint_engine_name()
368 engine->instance) >= sizeof(engine->name)); in __sprint_engine_name()
371 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask) in intel_engine_set_hwsp_writemask() argument
375 * per-engine HWSTAM until gen6. in intel_engine_set_hwsp_writemask()
377 if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS) in intel_engine_set_hwsp_writemask()
380 if (GRAPHICS_VER(engine->i915) >= 3) in intel_engine_set_hwsp_writemask()
381 ENGINE_WRITE(engine, RING_HWSTAM, mask); in intel_engine_set_hwsp_writemask()
383 ENGINE_WRITE16(engine, RING_HWSTAM, mask); in intel_engine_set_hwsp_writemask()
386 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine) in intel_engine_sanitize_mmio() argument
389 intel_engine_set_hwsp_writemask(engine, ~0u); in intel_engine_sanitize_mmio()
392 static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir) in nop_irq_handler() argument
455 struct intel_engine_cs *engine; in intel_engine_setup() local
463 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine))) in intel_engine_setup()
475 engine = kzalloc(sizeof(*engine), GFP_KERNEL); in intel_engine_setup()
476 if (!engine) in intel_engine_setup()
479 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES); in intel_engine_setup()
481 INIT_LIST_HEAD(&engine->pinned_contexts_list); in intel_engine_setup()
482 engine->id = id; in intel_engine_setup()
483 engine->legacy_idx = INVALID_ENGINE; in intel_engine_setup()
484 engine->mask = BIT(id); in intel_engine_setup()
485 engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915), in intel_engine_setup()
487 engine->i915 = i915; in intel_engine_setup()
488 engine->gt = gt; in intel_engine_setup()
489 engine->uncore = gt->uncore; in intel_engine_setup()
491 engine->guc_id = MAKE_GUC_ID(guc_class, info->instance); in intel_engine_setup()
492 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases); in intel_engine_setup()
494 engine->irq_handler = nop_irq_handler; in intel_engine_setup()
496 engine->class = info->class; in intel_engine_setup()
497 engine->instance = info->instance; in intel_engine_setup()
498 engine->logical_mask = BIT(logical_instance); in intel_engine_setup()
499 __sprint_engine_name(engine); in intel_engine_setup()
501 if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) && in intel_engine_setup()
502 __ffs(CCS_MASK(engine->gt)) == engine->instance) || in intel_engine_setup()
503 engine->class == RENDER_CLASS) in intel_engine_setup()
504 engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE; in intel_engine_setup()
507 if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) { in intel_engine_setup()
508 engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE; in intel_engine_setup()
509 engine->flags |= I915_ENGINE_HAS_EU_PRIORITY; in intel_engine_setup()
512 engine->props.heartbeat_interval_ms = in intel_engine_setup()
514 engine->props.max_busywait_duration_ns = in intel_engine_setup()
516 engine->props.preempt_timeout_ms = in intel_engine_setup()
518 engine->props.stop_timeout_ms = in intel_engine_setup()
520 engine->props.timeslice_duration_ms = in intel_engine_setup()
529 if (GRAPHICS_VER(i915) == 12 && (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)) in intel_engine_setup()
530 engine->props.preempt_timeout_ms = CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE; in intel_engine_setup()
535 u64 clamp = intel_clamp_##field(engine, engine->props.field); \ in intel_engine_setup()
536 if (clamp != engine->props.field) { \ in intel_engine_setup()
537 drm_notice(&engine->i915->drm, \ in intel_engine_setup()
540 engine->props.field = clamp; \ in intel_engine_setup()
552 engine->defaults = engine->props; /* never to change again */ in intel_engine_setup()
554 engine->context_size = intel_engine_context_size(gt, engine->class); in intel_engine_setup()
555 if (WARN_ON(engine->context_size > BIT(20))) in intel_engine_setup()
556 engine->context_size = 0; in intel_engine_setup()
557 if (engine->context_size) in intel_engine_setup()
560 ewma__engine_latency_init(&engine->latency); in intel_engine_setup()
562 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); in intel_engine_setup()
565 intel_engine_sanitize_mmio(engine); in intel_engine_setup()
567 gt->engine_class[info->class][info->instance] = engine; in intel_engine_setup()
568 gt->engine[id] = engine; in intel_engine_setup()
573 u64 intel_clamp_heartbeat_interval_ms(struct intel_engine_cs *engine, u64 value) in intel_clamp_heartbeat_interval_ms() argument
580 u64 intel_clamp_max_busywait_duration_ns(struct intel_engine_cs *engine, u64 value) in intel_clamp_max_busywait_duration_ns() argument
587 u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value) in intel_clamp_preempt_timeout_ms() argument
593 if (intel_guc_submission_is_wanted(&engine->gt->uc.guc)) in intel_clamp_preempt_timeout_ms()
601 u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value) in intel_clamp_stop_timeout_ms() argument
608 u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value) in intel_clamp_timeslice_duration_ms() argument
614 if (intel_guc_submission_is_wanted(&engine->gt->uc.guc)) in intel_clamp_timeslice_duration_ms()
622 static void __setup_engine_capabilities(struct intel_engine_cs *engine) in __setup_engine_capabilities() argument
624 struct drm_i915_private *i915 = engine->i915; in __setup_engine_capabilities()
626 if (engine->class == VIDEO_DECODE_CLASS) { in __setup_engine_capabilities()
628 * HEVC support is present on first engine instance in __setup_engine_capabilities()
632 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0)) in __setup_engine_capabilities()
633 engine->uabi_capabilities |= in __setup_engine_capabilities()
637 * SFC block is present only on even logical engine in __setup_engine_capabilities()
641 (engine->gt->info.vdbox_sfc_access & in __setup_engine_capabilities()
642 BIT(engine->instance))) || in __setup_engine_capabilities()
643 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0)) in __setup_engine_capabilities()
644 engine->uabi_capabilities |= in __setup_engine_capabilities()
646 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) { in __setup_engine_capabilities()
648 engine->gt->info.sfc_mask & BIT(engine->instance)) in __setup_engine_capabilities()
649 engine->uabi_capabilities |= in __setup_engine_capabilities()
656 struct intel_engine_cs *engine; in intel_setup_engine_capabilities() local
659 for_each_engine(engine, gt, id) in intel_setup_engine_capabilities()
660 __setup_engine_capabilities(engine); in intel_setup_engine_capabilities()
669 struct intel_engine_cs *engine; in intel_engines_release() local
673 * Before we release the resources held by engine, we must be certain in intel_engines_release()
686 for_each_engine(engine, gt, id) { in intel_engines_release()
687 if (!engine->release) in intel_engines_release()
690 intel_wakeref_wait_for_idle(&engine->wakeref); in intel_engines_release()
691 GEM_BUG_ON(intel_engine_pm_is_awake(engine)); in intel_engines_release()
693 engine->release(engine); in intel_engines_release()
694 engine->release = NULL; in intel_engines_release()
696 memset(&engine->reset, 0, sizeof(engine->reset)); in intel_engines_release()
700 void intel_engine_free_request_pool(struct intel_engine_cs *engine) in intel_engine_free_request_pool() argument
702 if (!engine->request_pool) in intel_engine_free_request_pool()
705 kmem_cache_free(i915_request_slab_cache(), engine->request_pool); in intel_engine_free_request_pool()
710 struct intel_engine_cs *engine; in intel_engines_free() local
716 for_each_engine(engine, gt, id) { in intel_engines_free()
717 intel_engine_free_request_pool(engine); in intel_engines_free()
718 kfree(engine); in intel_engines_free()
719 gt->engine[id] = NULL; in intel_engines_free()
837 * engine is not available for use. in engine_mask_apply_compute_fuses()
880 * the blitter forcewake domain to read the engine fuses, but at the same time
883 * domains based on the full engine mask in the platform capabilities before
962 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
1025 void intel_engine_init_execlists(struct intel_engine_cs *engine) in intel_engine_init_execlists() argument
1027 struct intel_engine_execlists * const execlists = &engine->execlists; in intel_engine_init_execlists()
1038 static void cleanup_status_page(struct intel_engine_cs *engine) in cleanup_status_page() argument
1043 intel_engine_set_hwsp_writemask(engine, ~0u); in cleanup_status_page()
1045 vma = fetch_and_zero(&engine->status_page.vma); in cleanup_status_page()
1049 if (!HWS_NEEDS_PHYSICAL(engine->i915)) in cleanup_status_page()
1056 static int pin_ggtt_status_page(struct intel_engine_cs *engine, in pin_ggtt_status_page() argument
1062 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt)) in pin_ggtt_status_page()
1081 static int init_status_page(struct intel_engine_cs *engine) in init_status_page() argument
1089 INIT_LIST_HEAD(&engine->status_page.timelines); in init_status_page()
1098 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); in init_status_page()
1100 drm_err(&engine->i915->drm, in init_status_page()
1107 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); in init_status_page()
1116 if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915)) in init_status_page()
1117 ret = pin_ggtt_status_page(engine, &ww, vma); in init_status_page()
1127 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE); in init_status_page()
1128 engine->status_page.vma = vma; in init_status_page()
1146 static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine) in intel_engine_init_tlb_invalidation() argument
1173 struct drm_i915_private *i915 = engine->i915; in intel_engine_init_tlb_invalidation()
1174 const unsigned int instance = engine->instance; in intel_engine_init_tlb_invalidation()
1175 const unsigned int class = engine->class; in intel_engine_init_tlb_invalidation()
1188 * respective engine registers were moved to masked type. Then after the in intel_engine_init_tlb_invalidation()
1192 if (engine->gt->type == GT_MEDIA) { in intel_engine_init_tlb_invalidation()
1216 if (gt_WARN_ONCE(engine->gt, !num, in intel_engine_init_tlb_invalidation()
1220 if (gt_WARN_ON_ONCE(engine->gt, in intel_engine_init_tlb_invalidation()
1244 engine->tlb_inv.mcr = regs == xehp_regs; in intel_engine_init_tlb_invalidation()
1245 engine->tlb_inv.reg = reg; in intel_engine_init_tlb_invalidation()
1246 engine->tlb_inv.done = val; in intel_engine_init_tlb_invalidation()
1249 (engine->class == VIDEO_DECODE_CLASS || in intel_engine_init_tlb_invalidation()
1250 engine->class == VIDEO_ENHANCEMENT_CLASS || in intel_engine_init_tlb_invalidation()
1251 engine->class == COMPUTE_CLASS || in intel_engine_init_tlb_invalidation()
1252 engine->class == OTHER_CLASS)) in intel_engine_init_tlb_invalidation()
1253 engine->tlb_inv.request = _MASKED_BIT_ENABLE(val); in intel_engine_init_tlb_invalidation()
1255 engine->tlb_inv.request = val; in intel_engine_init_tlb_invalidation()
1260 static int engine_setup_common(struct intel_engine_cs *engine) in engine_setup_common() argument
1264 init_llist_head(&engine->barrier_tasks); in engine_setup_common()
1266 err = intel_engine_init_tlb_invalidation(engine); in engine_setup_common()
1270 err = init_status_page(engine); in engine_setup_common()
1274 engine->breadcrumbs = intel_breadcrumbs_create(engine); in engine_setup_common()
1275 if (!engine->breadcrumbs) { in engine_setup_common()
1280 engine->sched_engine = i915_sched_engine_create(ENGINE_PHYSICAL); in engine_setup_common()
1281 if (!engine->sched_engine) { in engine_setup_common()
1285 engine->sched_engine->private_data = engine; in engine_setup_common()
1287 err = intel_engine_init_cmd_parser(engine); in engine_setup_common()
1291 intel_engine_init_execlists(engine); in engine_setup_common()
1292 intel_engine_init__pm(engine); in engine_setup_common()
1293 intel_engine_init_retire(engine); in engine_setup_common()
1296 engine->sseu = in engine_setup_common()
1297 intel_sseu_from_device_info(&engine->gt->info.sseu); in engine_setup_common()
1299 intel_engine_init_workarounds(engine); in engine_setup_common()
1300 intel_engine_init_whitelist(engine); in engine_setup_common()
1301 intel_engine_init_ctx_wa(engine); in engine_setup_common()
1303 if (GRAPHICS_VER(engine->i915) >= 12) in engine_setup_common()
1304 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO; in engine_setup_common()
1309 i915_sched_engine_put(engine->sched_engine); in engine_setup_common()
1311 intel_breadcrumbs_put(engine->breadcrumbs); in engine_setup_common()
1313 cleanup_status_page(engine); in engine_setup_common()
1325 struct intel_engine_cs *engine = ce->engine; in measure_breadcrumb_dw() local
1329 GEM_BUG_ON(!engine->gt->scratch); in measure_breadcrumb_dw()
1335 frame->rq.i915 = engine->i915; in measure_breadcrumb_dw()
1336 frame->rq.engine = engine; in measure_breadcrumb_dw()
1350 spin_lock_irq(&engine->sched_engine->lock); in measure_breadcrumb_dw()
1352 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs; in measure_breadcrumb_dw()
1354 spin_unlock_irq(&engine->sched_engine->lock); in measure_breadcrumb_dw()
1364 intel_engine_create_pinned_context(struct intel_engine_cs *engine, in intel_engine_create_pinned_context() argument
1374 ce = intel_context_create(engine); in intel_engine_create_pinned_context()
1392 list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list); in intel_engine_create_pinned_context()
1407 struct intel_engine_cs *engine = ce->engine; in intel_engine_destroy_pinned_context() local
1408 struct i915_vma *hwsp = engine->status_page.vma; in intel_engine_destroy_pinned_context()
1422 create_kernel_context(struct intel_engine_cs *engine) in create_kernel_context() argument
1426 return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K, in create_kernel_context()
1432 * engine_init_common - initialize engine state which might require hw access
1433 * @engine: Engine to initialize.
1435 * Initializes @engine@ structure members shared between legacy and execlists
1438 * Typcally done at later stages of submission mode specific engine setup.
1442 static int engine_init_common(struct intel_engine_cs *engine) in engine_init_common() argument
1447 engine->set_default_submission(engine); in engine_init_common()
1457 ce = create_kernel_context(engine); in engine_init_common()
1465 engine->emit_fini_breadcrumb_dw = ret; in engine_init_common()
1466 engine->kernel_context = ce; in engine_init_common()
1477 int (*setup)(struct intel_engine_cs *engine); in intel_engines_init()
1478 struct intel_engine_cs *engine; in intel_engines_init() local
1493 for_each_engine(engine, gt, id) { in intel_engines_init()
1494 err = engine_setup_common(engine); in intel_engines_init()
1498 err = setup(engine); in intel_engines_init()
1500 intel_engine_cleanup_common(engine); in intel_engines_init()
1505 GEM_BUG_ON(engine->release == NULL); in intel_engines_init()
1507 err = engine_init_common(engine); in intel_engines_init()
1511 intel_engine_add_user(engine); in intel_engines_init()
1518 * intel_engine_cleanup_common - cleans up the engine state created by
1520 * @engine: Engine to cleanup.
1524 void intel_engine_cleanup_common(struct intel_engine_cs *engine) in intel_engine_cleanup_common() argument
1526 GEM_BUG_ON(!list_empty(&engine->sched_engine->requests)); in intel_engine_cleanup_common()
1528 i915_sched_engine_put(engine->sched_engine); in intel_engine_cleanup_common()
1529 intel_breadcrumbs_put(engine->breadcrumbs); in intel_engine_cleanup_common()
1531 intel_engine_fini_retire(engine); in intel_engine_cleanup_common()
1532 intel_engine_cleanup_cmd_parser(engine); in intel_engine_cleanup_common()
1534 if (engine->default_state) in intel_engine_cleanup_common()
1535 fput(engine->default_state); in intel_engine_cleanup_common()
1537 if (engine->kernel_context) in intel_engine_cleanup_common()
1538 intel_engine_destroy_pinned_context(engine->kernel_context); in intel_engine_cleanup_common()
1540 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks)); in intel_engine_cleanup_common()
1541 cleanup_status_page(engine); in intel_engine_cleanup_common()
1543 intel_wa_list_free(&engine->ctx_wa_list); in intel_engine_cleanup_common()
1544 intel_wa_list_free(&engine->wa_list); in intel_engine_cleanup_common()
1545 intel_wa_list_free(&engine->whitelist); in intel_engine_cleanup_common()
1549 * intel_engine_resume - re-initializes the HW state of the engine
1550 * @engine: Engine to resume.
1554 int intel_engine_resume(struct intel_engine_cs *engine) in intel_engine_resume() argument
1556 intel_engine_apply_workarounds(engine); in intel_engine_resume()
1557 intel_engine_apply_whitelist(engine); in intel_engine_resume()
1559 return engine->resume(engine); in intel_engine_resume()
1562 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine) in intel_engine_get_active_head() argument
1564 struct drm_i915_private *i915 = engine->i915; in intel_engine_get_active_head()
1569 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW); in intel_engine_get_active_head()
1571 acthd = ENGINE_READ(engine, RING_ACTHD); in intel_engine_get_active_head()
1573 acthd = ENGINE_READ(engine, ACTHD); in intel_engine_get_active_head()
1578 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine) in intel_engine_get_last_batch_head() argument
1582 if (GRAPHICS_VER(engine->i915) >= 8) in intel_engine_get_last_batch_head()
1583 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW); in intel_engine_get_last_batch_head()
1585 bbaddr = ENGINE_READ(engine, RING_BBADDR); in intel_engine_get_last_batch_head()
1590 static unsigned long stop_timeout(const struct intel_engine_cs *engine) in stop_timeout() argument
1597 * the engine to quiesce. We've stopped submission to the engine, and in stop_timeout()
1599 * leave the engine idle. So they should not be caught unaware by in stop_timeout()
1602 return READ_ONCE(engine->props.stop_timeout_ms); in stop_timeout()
1605 static int __intel_engine_stop_cs(struct intel_engine_cs *engine, in __intel_engine_stop_cs() argument
1609 struct intel_uncore *uncore = engine->uncore; in __intel_engine_stop_cs()
1610 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); in __intel_engine_stop_cs()
1619 if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) || in __intel_engine_stop_cs()
1620 (GRAPHICS_VER(engine->i915) >= 11 && in __intel_engine_stop_cs()
1621 GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) in __intel_engine_stop_cs()
1622 intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base), in __intel_engine_stop_cs()
1625 err = __intel_wait_for_register_fw(engine->uncore, mode, in __intel_engine_stop_cs()
1636 int intel_engine_stop_cs(struct intel_engine_cs *engine) in intel_engine_stop_cs() argument
1640 if (GRAPHICS_VER(engine->i915) < 3) in intel_engine_stop_cs()
1643 ENGINE_TRACE(engine, "\n"); in intel_engine_stop_cs()
1656 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { in intel_engine_stop_cs()
1657 ENGINE_TRACE(engine, in intel_engine_stop_cs()
1659 ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR, in intel_engine_stop_cs()
1660 ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR); in intel_engine_stop_cs()
1667 if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) != in intel_engine_stop_cs()
1668 (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR)) in intel_engine_stop_cs()
1675 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) in intel_engine_cancel_stop_cs() argument
1677 ENGINE_TRACE(engine, "\n"); in intel_engine_cancel_stop_cs()
1679 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in intel_engine_cancel_stop_cs()
1682 static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine) in __cs_pending_mi_force_wakes() argument
1706 if (!_reg[engine->id].reg) in __cs_pending_mi_force_wakes()
1709 val = intel_uncore_read(engine->uncore, _reg[engine->id]); in __cs_pending_mi_force_wakes()
1743 void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine) in intel_engine_wait_for_pending_mi_fw() argument
1745 u32 fw_pending = __cs_pending_mi_force_wakes(engine); in intel_engine_wait_for_pending_mi_fw()
1748 __gpm_wait_for_fw_complete(engine->gt, fw_pending); in intel_engine_wait_for_pending_mi_fw()
1752 void intel_engine_get_instdone(const struct intel_engine_cs *engine, in intel_engine_get_instdone() argument
1755 struct drm_i915_private *i915 = engine->i915; in intel_engine_get_instdone()
1756 struct intel_uncore *uncore = engine->uncore; in intel_engine_get_instdone()
1757 u32 mmio_base = engine->mmio_base; in intel_engine_get_instdone()
1768 if (engine->id != RCS0) in intel_engine_get_instdone()
1780 for_each_ss_steering(iter, engine->gt, slice, subslice) { in intel_engine_get_instdone()
1782 intel_gt_mcr_read(engine->gt, in intel_engine_get_instdone()
1786 intel_gt_mcr_read(engine->gt, in intel_engine_get_instdone()
1792 for_each_ss_steering(iter, engine->gt, slice, subslice) in intel_engine_get_instdone()
1794 intel_gt_mcr_read(engine->gt, in intel_engine_get_instdone()
1802 if (engine->id != RCS0) in intel_engine_get_instdone()
1814 if (engine->id == RCS0) in intel_engine_get_instdone()
1823 static bool ring_is_idle(struct intel_engine_cs *engine) in ring_is_idle() argument
1827 if (I915_SELFTEST_ONLY(!engine->mmio_base)) in ring_is_idle()
1830 if (!intel_engine_pm_get_if_awake(engine)) in ring_is_idle()
1834 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) != in ring_is_idle()
1835 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR)) in ring_is_idle()
1839 if (GRAPHICS_VER(engine->i915) > 2 && in ring_is_idle()
1840 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE)) in ring_is_idle()
1843 intel_engine_pm_put(engine); in ring_is_idle()
1848 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync) in __intel_engine_flush_submission() argument
1850 struct tasklet_struct *t = &engine->sched_engine->tasklet; in __intel_engine_flush_submission()
1870 * intel_engine_is_idle() - Report if the engine has finished process all work
1871 * @engine: the intel_engine_cs
1874 * to hardware, and that the engine is idle.
1876 bool intel_engine_is_idle(struct intel_engine_cs *engine) in intel_engine_is_idle() argument
1879 if (intel_gt_is_wedged(engine->gt)) in intel_engine_is_idle()
1882 if (!intel_engine_pm_is_awake(engine)) in intel_engine_is_idle()
1886 intel_synchronize_hardirq(engine->i915); in intel_engine_is_idle()
1887 intel_engine_flush_submission(engine); in intel_engine_is_idle()
1890 if (!i915_sched_engine_is_empty(engine->sched_engine)) in intel_engine_is_idle()
1894 return ring_is_idle(engine); in intel_engine_is_idle()
1899 struct intel_engine_cs *engine; in intel_engines_are_idle() local
1913 for_each_engine(engine, gt, id) { in intel_engines_are_idle()
1914 if (!intel_engine_is_idle(engine)) in intel_engines_are_idle()
1921 bool intel_engine_irq_enable(struct intel_engine_cs *engine) in intel_engine_irq_enable() argument
1923 if (!engine->irq_enable) in intel_engine_irq_enable()
1927 spin_lock(engine->gt->irq_lock); in intel_engine_irq_enable()
1928 engine->irq_enable(engine); in intel_engine_irq_enable()
1929 spin_unlock(engine->gt->irq_lock); in intel_engine_irq_enable()
1934 void intel_engine_irq_disable(struct intel_engine_cs *engine) in intel_engine_irq_disable() argument
1936 if (!engine->irq_disable) in intel_engine_irq_disable()
1940 spin_lock(engine->gt->irq_lock); in intel_engine_irq_disable()
1941 engine->irq_disable(engine); in intel_engine_irq_disable()
1942 spin_unlock(engine->gt->irq_lock); in intel_engine_irq_disable()
1947 struct intel_engine_cs *engine; in intel_engines_reset_default_submission() local
1950 for_each_engine(engine, gt, id) { in intel_engines_reset_default_submission()
1951 if (engine->sanitize) in intel_engines_reset_default_submission()
1952 engine->sanitize(engine); in intel_engines_reset_default_submission()
1954 engine->set_default_submission(engine); in intel_engines_reset_default_submission()
1958 bool intel_engine_can_store_dword(struct intel_engine_cs *engine) in intel_engine_can_store_dword() argument
1960 switch (GRAPHICS_VER(engine->i915)) { in intel_engine_can_store_dword()
1965 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915)); in intel_engine_can_store_dword()
1967 return !IS_I965G(engine->i915); /* who knows! */ in intel_engine_can_store_dword()
1969 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */ in intel_engine_can_store_dword()
1980 * Even though we are holding the engine->sched_engine->lock here, there in get_timeline()
2058 static void intel_engine_print_registers(struct intel_engine_cs *engine, in intel_engine_print_registers() argument
2061 struct drm_i915_private *i915 = engine->i915; in intel_engine_print_registers()
2062 struct intel_engine_execlists * const execlists = &engine->execlists; in intel_engine_print_registers()
2065 if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(i915, 4, 7)) in intel_engine_print_registers()
2066 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID)); in intel_engine_print_registers()
2069 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI)); in intel_engine_print_registers()
2071 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO)); in intel_engine_print_registers()
2074 ENGINE_READ(engine, RING_START)); in intel_engine_print_registers()
2076 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR); in intel_engine_print_registers()
2078 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR); in intel_engine_print_registers()
2080 ENGINE_READ(engine, RING_CTL), in intel_engine_print_registers()
2081 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : ""); in intel_engine_print_registers()
2082 if (GRAPHICS_VER(engine->i915) > 2) { in intel_engine_print_registers()
2084 ENGINE_READ(engine, RING_MI_MODE), in intel_engine_print_registers()
2085 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : ""); in intel_engine_print_registers()
2090 ENGINE_READ(engine, RING_IMR)); in intel_engine_print_registers()
2092 ENGINE_READ(engine, RING_ESR)); in intel_engine_print_registers()
2094 ENGINE_READ(engine, RING_EMR)); in intel_engine_print_registers()
2096 ENGINE_READ(engine, RING_EIR)); in intel_engine_print_registers()
2099 addr = intel_engine_get_active_head(engine); in intel_engine_print_registers()
2102 addr = intel_engine_get_last_batch_head(engine); in intel_engine_print_registers()
2106 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW); in intel_engine_print_registers()
2108 addr = ENGINE_READ(engine, RING_DMA_FADD); in intel_engine_print_registers()
2110 addr = ENGINE_READ(engine, DMA_FADD_I8XX); in intel_engine_print_registers()
2115 ENGINE_READ(engine, RING_IPEIR)); in intel_engine_print_registers()
2117 ENGINE_READ(engine, RING_IPEHR)); in intel_engine_print_registers()
2119 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR)); in intel_engine_print_registers()
2120 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR)); in intel_engine_print_registers()
2123 if (HAS_EXECLISTS(i915) && !intel_engine_uses_guc(engine)) { in intel_engine_print_registers()
2126 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; in intel_engine_print_registers()
2132 str_yes_no(test_bit(TASKLET_STATE_SCHED, &engine->sched_engine->tasklet.state)), in intel_engine_print_registers()
2133 str_enabled_disabled(!atomic_read(&engine->sched_engine->tasklet.count)), in intel_engine_print_registers()
2134 repr_timer(&engine->execlists.preempt), in intel_engine_print_registers()
2135 repr_timer(&engine->execlists.timer)); in intel_engine_print_registers()
2141 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO), in intel_engine_print_registers()
2142 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI), in intel_engine_print_registers()
2157 i915_sched_engine_active_lock_bh(engine->sched_engine); in intel_engine_print_registers()
2188 i915_sched_engine_active_unlock_bh(engine->sched_engine); in intel_engine_print_registers()
2191 ENGINE_READ(engine, RING_PP_DIR_BASE)); in intel_engine_print_registers()
2193 ENGINE_READ(engine, RING_PP_DIR_BASE_READ)); in intel_engine_print_registers()
2195 ENGINE_READ(engine, RING_PP_DIR_DCLV)); in intel_engine_print_registers()
2238 static void print_properties(struct intel_engine_cs *engine, in print_properties() argument
2246 .offset = offsetof(typeof(engine->props), x), \ in print_properties()
2264 read_ul(&engine->props, p->offset), in print_properties()
2265 read_ul(&engine->defaults, p->offset)); in print_properties()
2316 msg = "\t\tactive on engine"; in intel_engine_dump_active_requests()
2324 static void engine_dump_active_requests(struct intel_engine_cs *engine, in engine_dump_active_requests() argument
2331 * No need for an engine->irq_seqno_barrier() before the seqno reads. in engine_dump_active_requests()
2337 intel_engine_get_hung_entity(engine, &hung_ce, &hung_rq); in engine_dump_active_requests()
2346 if (intel_uc_uses_guc_submission(&engine->gt->uc)) in engine_dump_active_requests()
2347 intel_guc_dump_active_requests(engine, hung_rq, m); in engine_dump_active_requests()
2349 intel_execlists_dump_active_requests(engine, hung_rq, m); in engine_dump_active_requests()
2355 void intel_engine_dump(struct intel_engine_cs *engine, in intel_engine_dump() argument
2359 struct i915_gpu_error * const error = &engine->i915->gpu_error; in intel_engine_dump()
2372 if (intel_gt_is_wedged(engine->gt)) in intel_engine_dump()
2375 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count)); in intel_engine_dump()
2377 str_yes_no(!llist_empty(&engine->barrier_tasks))); in intel_engine_dump()
2379 ewma__engine_latency_read(&engine->latency)); in intel_engine_dump()
2380 if (intel_engine_supports_stats(engine)) in intel_engine_dump()
2382 ktime_to_ms(intel_engine_get_busy_time(engine, in intel_engine_dump()
2385 engine->fw_domain, READ_ONCE(engine->fw_active)); in intel_engine_dump()
2388 rq = READ_ONCE(engine->heartbeat.systole); in intel_engine_dump()
2394 i915_reset_engine_count(error, engine), in intel_engine_dump()
2396 print_properties(engine, m); in intel_engine_dump()
2398 engine_dump_active_requests(engine, m); in intel_engine_dump()
2400 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base); in intel_engine_dump()
2401 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm); in intel_engine_dump()
2403 intel_engine_print_registers(engine, m); in intel_engine_dump()
2404 intel_runtime_pm_put(engine->uncore->rpm, wakeref); in intel_engine_dump()
2409 intel_execlists_show_requests(engine, m, i915_request_show, 8); in intel_engine_dump()
2412 hexdump(m, engine->status_page.addr, PAGE_SIZE); in intel_engine_dump()
2414 drm_printf(m, "Idle? %s\n", str_yes_no(intel_engine_is_idle(engine))); in intel_engine_dump()
2416 intel_engine_print_breadcrumbs(engine, m); in intel_engine_dump()
2420 * intel_engine_get_busy_time() - Return current accumulated engine busyness
2421 * @engine: engine to report on
2424 * Returns accumulated time @engine was busy since engine stats were enabled.
2426 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) in intel_engine_get_busy_time() argument
2428 return engine->busyness(engine, now); in intel_engine_get_busy_time()
2445 static struct i915_request *engine_execlist_find_hung_request(struct intel_engine_cs *engine) in engine_execlist_find_hung_request() argument
2454 GEM_BUG_ON(intel_uc_uses_guc_submission(&engine->gt->uc)); in engine_execlist_find_hung_request()
2457 * We are called by the error capture, reset and to dump engine in engine_execlist_find_hung_request()
2463 * not need an engine->irq_seqno_barrier() before the seqno reads. in engine_execlist_find_hung_request()
2467 lockdep_assert_held(&engine->sched_engine->lock); in engine_execlist_find_hung_request()
2470 request = execlists_active(&engine->execlists); in engine_execlist_find_hung_request()
2485 list_for_each_entry(request, &engine->sched_engine->requests, in engine_execlist_find_hung_request()
2497 void intel_engine_get_hung_entity(struct intel_engine_cs *engine, in intel_engine_get_hung_entity() argument
2502 *ce = intel_engine_get_hung_context(engine); in intel_engine_get_hung_entity()
2504 intel_engine_clear_hung_context(engine); in intel_engine_get_hung_entity()
2514 if (intel_uc_uses_guc_submission(&engine->gt->uc)) in intel_engine_get_hung_entity()
2517 spin_lock_irqsave(&engine->sched_engine->lock, flags); in intel_engine_get_hung_entity()
2518 *rq = engine_execlist_find_hung_request(engine); in intel_engine_get_hung_entity()
2521 spin_unlock_irqrestore(&engine->sched_engine->lock, flags); in intel_engine_get_hung_entity()
2524 void xehp_enable_ccs_engines(struct intel_engine_cs *engine) in xehp_enable_ccs_engines() argument
2529 * so for simplicity we'll take care of this in the RCS engine's in xehp_enable_ccs_engines()
2534 if (!CCS_MASK(engine->gt)) in xehp_enable_ccs_engines()
2537 intel_uncore_write(engine->uncore, GEN12_RCU_MODE, in xehp_enable_ccs_engines()