Lines Matching refs:dev_priv
89 struct drm_i915_private *dev_priv = to_i915(dev); in vlv_dsi_wait_for_fifo_empty() local
95 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), in vlv_dsi_wait_for_fifo_empty()
97 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
100 static void write_data(struct drm_i915_private *dev_priv, in write_data() argument
112 intel_de_write(dev_priv, reg, val); in write_data()
116 static void read_data(struct drm_i915_private *dev_priv, in read_data() argument
123 u32 val = intel_de_read(dev_priv, reg); in read_data()
135 struct drm_i915_private *dev_priv = to_i915(dev); in intel_dsi_host_transfer() local
163 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), in intel_dsi_host_transfer()
165 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
168 write_data(dev_priv, data_reg, packet.payload, in intel_dsi_host_transfer()
173 intel_de_write(dev_priv, MIPI_INTR_STAT(port), in intel_dsi_host_transfer()
177 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), in intel_dsi_host_transfer()
179 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
183 intel_de_write(dev_priv, ctrl_reg, in intel_dsi_host_transfer()
189 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), in intel_dsi_host_transfer()
191 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
194 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); in intel_dsi_host_transfer()
229 struct drm_i915_private *dev_priv = to_i915(dev); in dpi_send_cmd() local
239 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); in dpi_send_cmd()
242 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) in dpi_send_cmd()
243 drm_dbg_kms(&dev_priv->drm, in dpi_send_cmd()
246 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); in dpi_send_cmd()
249 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) in dpi_send_cmd()
250 drm_err(&dev_priv->drm, in dpi_send_cmd()
256 static void band_gap_reset(struct drm_i915_private *dev_priv) in band_gap_reset() argument
258 vlv_flisdsi_get(dev_priv); in band_gap_reset()
260 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); in band_gap_reset()
261 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); in band_gap_reset()
262 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); in band_gap_reset()
264 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); in band_gap_reset()
265 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); in band_gap_reset()
267 vlv_flisdsi_put(dev_priv); in band_gap_reset()
274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_compute_config() local
281 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_compute_config()
304 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_compute_config()
331 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_enable_io() local
341 intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE); in glk_dsi_enable_io()
344 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); in glk_dsi_enable_io()
348 u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in glk_dsi_enable_io()
349 intel_de_rmw(dev_priv, MIPI_CTRL(port), in glk_dsi_enable_io()
355 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), in glk_dsi_enable_io()
357 drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); in glk_dsi_enable_io()
363 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); in glk_dsi_enable_io()
371 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_device_ready() local
377 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), in glk_dsi_device_ready()
379 drm_err(&dev_priv->drm, "PHY is not ON\n"); in glk_dsi_device_ready()
383 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); in glk_dsi_device_ready()
387 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { in glk_dsi_device_ready()
388 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), in glk_dsi_device_ready()
393 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), in glk_dsi_device_ready()
397 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), in glk_dsi_device_ready()
399 drm_err(&dev_priv->drm, "ULPS not active\n"); in glk_dsi_device_ready()
402 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), in glk_dsi_device_ready()
406 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), in glk_dsi_device_ready()
410 intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0); in glk_dsi_device_ready()
416 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), in glk_dsi_device_ready()
418 drm_err(&dev_priv->drm, in glk_dsi_device_ready()
424 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), in glk_dsi_device_ready()
426 drm_err(&dev_priv->drm, in glk_dsi_device_ready()
433 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_dsi_device_ready() local
438 drm_dbg_kms(&dev_priv->drm, "\n"); in bxt_dsi_device_ready()
442 intel_de_rmw(dev_priv, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); in bxt_dsi_device_ready()
448 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in bxt_dsi_device_ready()
450 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in bxt_dsi_device_ready()
453 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in bxt_dsi_device_ready()
459 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_dsi_device_ready() local
463 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_device_ready()
465 vlv_flisdsi_get(dev_priv); in vlv_dsi_device_ready()
468 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); in vlv_dsi_device_ready()
469 vlv_flisdsi_put(dev_priv); in vlv_dsi_device_ready()
472 band_gap_reset(dev_priv); in vlv_dsi_device_ready()
476 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_device_ready()
484 intel_de_rmw(dev_priv, MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); in vlv_dsi_device_ready()
487 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_device_ready()
491 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_device_ready()
499 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_device_ready() local
501 if (IS_GEMINILAKE(dev_priv)) in intel_dsi_device_ready()
503 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in intel_dsi_device_ready()
511 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_enter_low_power_mode() local
517 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), in glk_dsi_enter_low_power_mode()
522 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), in glk_dsi_enter_low_power_mode()
524 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); in glk_dsi_enter_low_power_mode()
529 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), in glk_dsi_enter_low_power_mode()
531 drm_err(&dev_priv->drm, in glk_dsi_enter_low_power_mode()
538 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_disable_mipi_io() local
543 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); in glk_dsi_disable_mipi_io()
547 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), in glk_dsi_disable_mipi_io()
549 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); in glk_dsi_disable_mipi_io()
554 intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_ENABLE, 0); in glk_dsi_disable_mipi_io()
565 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_dsi_clear_device_ready() local
569 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_clear_device_ready()
572 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? in vlv_dsi_clear_device_ready()
575 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_clear_device_ready()
579 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_clear_device_ready()
583 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_clear_device_ready()
591 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || port == PORT_A) && in vlv_dsi_clear_device_ready()
592 intel_de_wait_for_clear(dev_priv, port_ctrl, in vlv_dsi_clear_device_ready()
594 drm_err(&dev_priv->drm, "DSI LP not going Low\n"); in vlv_dsi_clear_device_ready()
597 intel_de_rmw(dev_priv, port_ctrl, LP_OUTPUT_HOLD, 0); in vlv_dsi_clear_device_ready()
600 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00); in vlv_dsi_clear_device_ready()
608 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_port_enable() local
616 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_port_enable()
618 intel_de_rmw(dev_priv, MIPI_CTRL(port), in intel_dsi_port_enable()
622 intel_de_rmw(dev_priv, VLV_CHICKEN_3, in intel_dsi_port_enable()
629 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? in intel_dsi_port_enable()
633 temp = intel_de_read(dev_priv, port_ctrl); in intel_dsi_port_enable()
641 if (IS_BROXTON(dev_priv)) in intel_dsi_port_enable()
653 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE); in intel_dsi_port_enable()
654 intel_de_posting_read(dev_priv, port_ctrl); in intel_dsi_port_enable()
661 struct drm_i915_private *dev_priv = to_i915(dev); in intel_dsi_port_disable() local
666 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? in intel_dsi_port_disable()
670 intel_de_rmw(dev_priv, port_ctrl, DPI_ENABLE, 0); in intel_dsi_port_disable()
671 intel_de_posting_read(dev_priv, port_ctrl); in intel_dsi_port_disable()
726 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsi_pre_enable() local
731 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_pre_enable()
735 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in intel_dsi_pre_enable()
741 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_pre_enable()
749 if (IS_BROXTON(dev_priv)) { in intel_dsi_pre_enable()
751 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL); in intel_dsi_pre_enable()
754 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); in intel_dsi_pre_enable()
755 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0); in intel_dsi_pre_enable()
758 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dsi_pre_enable()
760 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), in intel_dsi_pre_enable()
764 if (!IS_GEMINILAKE(dev_priv)) in intel_dsi_pre_enable()
772 if (IS_GEMINILAKE(dev_priv)) { in intel_dsi_pre_enable()
784 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) in intel_dsi_pre_enable()
796 intel_de_write(dev_priv, in intel_dsi_pre_enable()
856 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_clear_device_ready() local
858 if (IS_GEMINILAKE(dev_priv)) in intel_dsi_clear_device_ready()
869 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_post_disable() local
873 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_post_disable()
875 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_post_disable()
902 if (IS_BROXTON(dev_priv)) { in intel_dsi_post_disable()
904 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); in intel_dsi_post_disable()
905 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, in intel_dsi_post_disable()
909 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0); in intel_dsi_post_disable()
912 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_post_disable()
917 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), in intel_dsi_post_disable()
933 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_get_hw_state() local
939 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_get_hw_state()
941 wakeref = intel_display_power_get_if_enabled(dev_priv, in intel_dsi_get_hw_state()
951 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && in intel_dsi_get_hw_state()
952 !bxt_dsi_pll_is_enabled(dev_priv)) in intel_dsi_get_hw_state()
957 i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? in intel_dsi_get_hw_state()
959 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE; in intel_dsi_get_hw_state()
966 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_dsi_get_hw_state()
968 enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; in intel_dsi_get_hw_state()
972 u32 tmp = intel_de_read(dev_priv, in intel_dsi_get_hw_state()
980 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) in intel_dsi_get_hw_state()
983 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_get_hw_state()
984 u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in intel_dsi_get_hw_state()
988 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) in intel_dsi_get_hw_state()
1001 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_dsi_get_hw_state()
1010 struct drm_i915_private *dev_priv = to_i915(dev); in bxt_dsi_get_pipe_config() local
1032 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) in bxt_dsi_get_pipe_config()
1036 fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; in bxt_dsi_get_pipe_config()
1048 intel_de_read(dev_priv, in bxt_dsi_get_pipe_config()
1051 intel_de_read(dev_priv, in bxt_dsi_get_pipe_config()
1054 intel_de_read(dev_priv, in bxt_dsi_get_pipe_config()
1058 hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)); in bxt_dsi_get_pipe_config()
1064 hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)); in bxt_dsi_get_pipe_config()
1065 hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)); in bxt_dsi_get_pipe_config()
1082 vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)); in bxt_dsi_get_pipe_config()
1083 vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)); in bxt_dsi_get_pipe_config()
1172 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_get_config() local
1176 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_get_config()
1180 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_get_config()
1213 struct drm_i915_private *dev_priv = to_i915(dev); in set_dsi_timings() local
1248 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in set_dsi_timings()
1255 intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port), in set_dsi_timings()
1257 intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port), in set_dsi_timings()
1259 intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port), in set_dsi_timings()
1263 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port), in set_dsi_timings()
1265 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp); in set_dsi_timings()
1269 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port), in set_dsi_timings()
1271 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp); in set_dsi_timings()
1274 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp); in set_dsi_timings()
1275 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port), in set_dsi_timings()
1277 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp); in set_dsi_timings()
1303 struct drm_i915_private *dev_priv = to_i915(dev); in intel_dsi_prepare() local
1312 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe)); in intel_dsi_prepare()
1323 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dsi_prepare()
1328 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); in intel_dsi_prepare()
1330 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), in intel_dsi_prepare()
1334 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in intel_dsi_prepare()
1336 intel_de_write(dev_priv, MIPI_CTRL(port), in intel_dsi_prepare()
1338 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_prepare()
1341 intel_de_rmw(dev_priv, MIPI_CTRL(port), in intel_dsi_prepare()
1346 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff); in intel_dsi_prepare()
1347 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff); in intel_dsi_prepare()
1349 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port), in intel_dsi_prepare()
1352 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port), in intel_dsi_prepare()
1373 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_prepare()
1380 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); in intel_dsi_prepare()
1401 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), in intel_dsi_prepare()
1404 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), in intel_dsi_prepare()
1407 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port), in intel_dsi_prepare()
1409 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port), in intel_dsi_prepare()
1411 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port), in intel_dsi_prepare()
1417 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), in intel_dsi_prepare()
1420 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && in intel_dsi_prepare()
1428 intel_de_write(dev_priv, in intel_dsi_prepare()
1434 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp); in intel_dsi_prepare()
1437 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), in intel_dsi_prepare()
1445 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port), in intel_dsi_prepare()
1454 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port), in intel_dsi_prepare()
1457 if (IS_GEMINILAKE(dev_priv)) { in intel_dsi_prepare()
1458 intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port), in intel_dsi_prepare()
1461 intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port), in intel_dsi_prepare()
1470 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port), in intel_dsi_prepare()
1473 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port), in intel_dsi_prepare()
1501 intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt); in intel_dsi_prepare()
1508 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_unprepare() local
1512 if (IS_GEMINILAKE(dev_priv)) in intel_dsi_unprepare()
1517 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); in intel_dsi_unprepare()
1519 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in intel_dsi_unprepare()
1523 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); in intel_dsi_unprepare()
1525 intel_de_rmw(dev_priv, MIPI_DSI_FUNC_PRG(port), VID_MODE_FORMAT_MASK, 0); in intel_dsi_unprepare()
1527 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1); in intel_dsi_unprepare()
1584 struct drm_i915_private *dev_priv = to_i915(dev); in vlv_dphy_param_init() local
1633 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2; in vlv_dphy_param_init()
1641 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", in vlv_dphy_param_init()
1662 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", in vlv_dphy_param_init()
1673 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", in vlv_dphy_param_init()
1683 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", in vlv_dphy_param_init()
1747 void vlv_dsi_init(struct drm_i915_private *dev_priv) in vlv_dsi_init() argument
1758 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_init()
1761 if (!intel_bios_is_dsi_present(dev_priv, &port)) in vlv_dsi_init()
1764 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in vlv_dsi_init()
1765 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE; in vlv_dsi_init()
1767 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE; in vlv_dsi_init()
1785 drm_encoder_init(&dev_priv->drm, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, in vlv_dsi_init()
1790 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in vlv_dsi_init()
1810 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in vlv_dsi_init()
1819 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, NULL, NULL); in vlv_dsi_init()
1826 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) in vlv_dsi_init()
1829 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) in vlv_dsi_init()
1845 drm_dbg_kms(&dev_priv->drm, "no device found\n"); in vlv_dsi_init()
1852 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", in vlv_dsi_init()
1856 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); in vlv_dsi_init()
1868 drm_connector_init(&dev_priv->drm, connector, &intel_dsi_connector_funcs, in vlv_dsi_init()
1877 mutex_lock(&dev_priv->drm.mode_config.mutex); in vlv_dsi_init()
1879 mutex_unlock(&dev_priv->drm.mode_config.mutex); in vlv_dsi_init()
1882 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); in vlv_dsi_init()