Lines Matching refs:psr
178 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in psr_global_enabled()
181 return connector->panel.vbt.psr.enable; in psr_global_enabled()
194 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in psr2_global_enabled()
210 EDP_PSR_ERROR(intel_dp->psr.transcoder); in psr_irq_psr_error_bit_get()
218 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); in psr_irq_post_exit_bit_get()
226 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); in psr_irq_pre_entry_bit_get()
234 EDP_PSR_MASK(intel_dp->psr.transcoder); in psr_irq_mask_get()
312 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_irq_control()
316 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) in psr_irq_control()
365 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_irq_handler()
369 intel_dp->psr.last_entry_attempt = time_ns; in intel_psr_irq_handler()
376 intel_dp->psr.last_exit = time_ns; in intel_psr_irq_handler()
386 psr_event_print(dev_priv, val, intel_dp->psr.psr2_enabled); in intel_psr_irq_handler()
394 intel_dp->psr.irq_aux_error = true; in intel_psr_irq_handler()
407 queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); in intel_psr_irq_handler()
471 intel_dp->psr.su_w_granularity = w; in intel_dp_get_su_granularity()
472 intel_dp->psr.su_y_granularity = y; in intel_dp_get_su_granularity()
500 intel_dp->psr.sink_support = true; in intel_psr_init_dpcd()
501 intel_dp->psr.sink_sync_latency = in intel_psr_init_dpcd()
521 intel_dp->psr.sink_psr2_support = y_req && alpm; in intel_psr_init_dpcd()
523 intel_dp->psr.sink_psr2_support ? "" : "not "); in intel_psr_init_dpcd()
525 if (intel_dp->psr.sink_psr2_support) { in intel_psr_init_dpcd()
526 intel_dp->psr.colorimetry_support = in intel_psr_init_dpcd()
536 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in hsw_psr_setup_aux()
576 if (intel_dp->psr.psr2_enabled) { in intel_psr_enable_sink()
583 if (intel_dp->psr.link_standby) in intel_psr_enable_sink()
590 if (intel_dp->psr.req_psr2_sdp_prior_scanline) in intel_psr_enable_sink()
613 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) in intel_psr1_get_tp_time()
615 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) in intel_psr1_get_tp_time()
617 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) in intel_psr1_get_tp_time()
622 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) in intel_psr1_get_tp_time()
624 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) in intel_psr1_get_tp_time()
626 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) in intel_psr1_get_tp_time()
636 connector->panel.vbt.psr.tp1_wakeup_time_us == 0 && in intel_psr1_get_tp_time()
637 connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) in intel_psr1_get_tp_time()
659 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); in psr_compute_idle_frames()
660 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); in psr_compute_idle_frames()
671 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in hsw_activate_psr1()
681 if (intel_dp->psr.link_standby) in hsw_activate_psr1()
702 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && in intel_psr2_get_tp_time()
703 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) in intel_psr2_get_tp_time()
705 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) in intel_psr2_get_tp_time()
707 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) in intel_psr2_get_tp_time()
717 return intel_dp->psr.io_wake_lines < 9 && in psr2_block_count_lines()
718 intel_dp->psr.fast_wake_lines < 9 ? 8 : 12; in psr2_block_count_lines()
729 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in hsw_activate_psr2()
740 val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2)); in hsw_activate_psr2()
768 tmp = map[intel_dp->psr.io_wake_lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; in hsw_activate_psr2()
771 tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; in hsw_activate_psr2()
774 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); in hsw_activate_psr2()
775 val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); in hsw_activate_psr2()
777 val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); in hsw_activate_psr2()
778 val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); in hsw_activate_psr2()
781 if (intel_dp->psr.req_psr2_sdp_prior_scanline) in hsw_activate_psr2()
784 if (intel_dp->psr.psr2_sel_fetch_enabled) { in hsw_activate_psr2()
828 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr2_program_idle_frames()
854 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); in tgl_dc3co_disable_work()
856 mutex_lock(&intel_dp->psr.lock); in tgl_dc3co_disable_work()
858 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) in tgl_dc3co_disable_work()
863 mutex_unlock(&intel_dp->psr.lock); in tgl_dc3co_disable_work()
868 if (!intel_dp->psr.dc3co_exitline) in tgl_disallow_dc3co_on_psr2_exit()
871 cancel_delayed_work(&intel_dp->psr.dc3co_work); in tgl_disallow_dc3co_on_psr2_exit()
943 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { in intel_psr2_sel_fetch_config_valid()
968 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) in psr2_granularity_check()
971 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) in psr2_granularity_check()
976 return intel_dp->psr.su_y_granularity == 4; in psr2_granularity_check()
984 y_granularity = intel_dp->psr.su_y_granularity; in psr2_granularity_check()
985 else if (intel_dp->psr.su_y_granularity <= 2) in psr2_granularity_check()
987 else if ((intel_dp->psr.su_y_granularity % 4) == 0) in psr2_granularity_check()
988 y_granularity = intel_dp->psr.su_y_granularity; in psr2_granularity_check()
1059 intel_dp->psr.io_wake_lines = max(io_wake_lines, 7); in _compute_psr2_wake_times()
1060 intel_dp->psr.fast_wake_lines = max(fast_wake_lines, 7); in _compute_psr2_wake_times()
1073 if (!intel_dp->psr.sink_psr2_support) in intel_psr2_config_valid()
1229 if (intel_dp->psr.sink_not_reliable) { in intel_psr_compute_config()
1281 mutex_lock(&intel_dp->psr.lock); in intel_psr_get_config()
1282 if (!intel_dp->psr.enabled) in intel_psr_get_config()
1290 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; in intel_psr_get_config()
1293 if (!intel_dp->psr.psr2_enabled) in intel_psr_get_config()
1307 mutex_unlock(&intel_dp->psr.lock); in intel_psr_get_config()
1313 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_activate()
1322 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); in intel_psr_activate()
1324 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_activate()
1327 if (intel_dp->psr.psr2_enabled) in intel_psr_activate()
1332 intel_dp->psr.active = true; in intel_psr_activate()
1337 switch (intel_dp->psr.pipe) { in wa_16013835468_bit_get()
1347 MISSING_CASE(intel_dp->psr.pipe); in wa_16013835468_bit_get()
1384 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_enable_source()
1424 if (intel_dp->psr.dc3co_exitline) in intel_psr_enable_source()
1426 intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE); in intel_psr_enable_source()
1430 intel_dp->psr.psr2_sel_fetch_enabled ? in intel_psr_enable_source()
1439 if (intel_dp->psr.psr2_enabled) { in intel_psr_enable_source()
1471 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_interrupt_error_check()
1485 intel_dp->psr.sink_not_reliable = true; in psr_interrupt_error_check()
1503 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); in intel_psr_enable_locked()
1505 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; in intel_psr_enable_locked()
1506 intel_dp->psr.busy_frontbuffer_bits = 0; in intel_psr_enable_locked()
1507 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; in intel_psr_enable_locked()
1508 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; in intel_psr_enable_locked()
1511 intel_dp->psr.dc3co_exit_delay = val; in intel_psr_enable_locked()
1512 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; in intel_psr_enable_locked()
1513 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; in intel_psr_enable_locked()
1514 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; in intel_psr_enable_locked()
1515 intel_dp->psr.req_psr2_sdp_prior_scanline = in intel_psr_enable_locked()
1522 intel_dp->psr.psr2_enabled ? "2" : "1"); in intel_psr_enable_locked()
1527 intel_dp->psr.enabled = true; in intel_psr_enable_locked()
1528 intel_dp->psr.paused = false; in intel_psr_enable_locked()
1536 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_exit()
1539 if (!intel_dp->psr.active) { in intel_psr_exit()
1551 if (intel_dp->psr.psr2_enabled) { in intel_psr_exit()
1564 intel_dp->psr.active = false; in intel_psr_exit()
1570 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_wait_exit_locked()
1574 if (intel_dp->psr.psr2_enabled) { in intel_psr_wait_exit_locked()
1591 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_disable_locked()
1595 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_disable_locked()
1597 if (!intel_dp->psr.enabled) in intel_psr_disable_locked()
1601 intel_dp->psr.psr2_enabled ? "2" : "1"); in intel_psr_disable_locked()
1614 if (intel_dp->psr.psr2_enabled) { in intel_psr_disable_locked()
1630 if (intel_dp->psr.psr2_enabled) in intel_psr_disable_locked()
1633 intel_dp->psr.enabled = false; in intel_psr_disable_locked()
1634 intel_dp->psr.psr2_enabled = false; in intel_psr_disable_locked()
1635 intel_dp->psr.psr2_sel_fetch_enabled = false; in intel_psr_disable_locked()
1636 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; in intel_psr_disable_locked()
1657 mutex_lock(&intel_dp->psr.lock); in intel_psr_disable()
1661 mutex_unlock(&intel_dp->psr.lock); in intel_psr_disable()
1662 cancel_work_sync(&intel_dp->psr.work); in intel_psr_disable()
1663 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); in intel_psr_disable()
1675 struct intel_psr *psr = &intel_dp->psr; in intel_psr_pause() local
1680 mutex_lock(&psr->lock); in intel_psr_pause()
1682 if (!psr->enabled) { in intel_psr_pause()
1683 mutex_unlock(&psr->lock); in intel_psr_pause()
1688 drm_WARN_ON(&dev_priv->drm, psr->paused); in intel_psr_pause()
1692 psr->paused = true; in intel_psr_pause()
1694 mutex_unlock(&psr->lock); in intel_psr_pause()
1696 cancel_work_sync(&psr->work); in intel_psr_pause()
1697 cancel_delayed_work_sync(&psr->dc3co_work); in intel_psr_pause()
1708 struct intel_psr *psr = &intel_dp->psr; in intel_psr_resume() local
1713 mutex_lock(&psr->lock); in intel_psr_resume()
1715 if (!psr->paused) in intel_psr_resume()
1718 psr->paused = false; in intel_psr_resume()
1722 mutex_unlock(&psr->lock); in intel_psr_resume()
1755 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_force_hw_tracking_exit()
1757 if (intel_dp->psr.psr2_sel_fetch_enabled) in psr_force_hw_tracking_exit()
1778 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); in psr_force_hw_tracking_exit()
1869 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr2_program_trans_man_trk_ctl()
1870 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) in intel_psr2_program_trans_man_trk_ctl()
2168 struct intel_psr *psr = &intel_dp->psr; in intel_psr_pre_plane_update() local
2171 mutex_lock(&psr->lock); in intel_psr_pre_plane_update()
2183 needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled; in intel_psr_pre_plane_update()
2187 if (psr->enabled && needs_to_disable) in intel_psr_pre_plane_update()
2189 else if (psr->enabled && new_crtc_state->wm_level_disabled) in intel_psr_pre_plane_update()
2193 mutex_unlock(&psr->lock); in intel_psr_pre_plane_update()
2209 struct intel_psr *psr = &intel_dp->psr; in _intel_psr_post_plane_update() local
2212 mutex_lock(&psr->lock); in _intel_psr_post_plane_update()
2214 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes); in _intel_psr_post_plane_update()
2216 keep_disabled |= psr->sink_not_reliable; in _intel_psr_post_plane_update()
2223 if (!psr->enabled && !keep_disabled) in _intel_psr_post_plane_update()
2225 else if (psr->enabled && !crtc_state->wm_level_disabled) in _intel_psr_post_plane_update()
2230 if (crtc_state->crc_enabled && psr->enabled) in _intel_psr_post_plane_update()
2233 mutex_unlock(&psr->lock); in _intel_psr_post_plane_update()
2254 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr2_ready_for_pipe_update_locked()
2269 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr1_ready_for_pipe_update_locked()
2302 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_wait_for_idle_locked()
2304 if (!intel_dp->psr.enabled) in intel_psr_wait_for_idle_locked()
2307 if (intel_dp->psr.psr2_enabled) in intel_psr_wait_for_idle_locked()
2320 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in __psr_wait_for_idle_locked()
2325 if (!intel_dp->psr.enabled) in __psr_wait_for_idle_locked()
2328 if (intel_dp->psr.psr2_enabled) { in __psr_wait_for_idle_locked()
2336 mutex_unlock(&intel_dp->psr.lock); in __psr_wait_for_idle_locked()
2344 mutex_lock(&intel_dp->psr.lock); in __psr_wait_for_idle_locked()
2345 return err == 0 && intel_dp->psr.enabled; in __psr_wait_for_idle_locked()
2424 ret = mutex_lock_interruptible(&intel_dp->psr.lock); in intel_psr_debug_set()
2428 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; in intel_psr_debug_set()
2429 intel_dp->psr.debug = val; in intel_psr_debug_set()
2435 if (intel_dp->psr.enabled) in intel_psr_debug_set()
2438 mutex_unlock(&intel_dp->psr.lock); in intel_psr_debug_set()
2448 struct intel_psr *psr = &intel_dp->psr; in intel_psr_handle_irq() local
2451 psr->sink_not_reliable = true; in intel_psr_handle_irq()
2459 container_of(work, typeof(*intel_dp), psr.work); in intel_psr_work()
2461 mutex_lock(&intel_dp->psr.lock); in intel_psr_work()
2463 if (!intel_dp->psr.enabled) in intel_psr_work()
2466 if (READ_ONCE(intel_dp->psr.irq_aux_error)) in intel_psr_work()
2483 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) in intel_psr_work()
2488 mutex_unlock(&intel_dp->psr.lock); in intel_psr_work()
2494 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr_invalidate_handle()
2496 if (intel_dp->psr.psr2_sel_fetch_enabled) { in _psr_invalidate_handle()
2499 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { in _psr_invalidate_handle()
2501 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); in _psr_invalidate_handle()
2509 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); in _psr_invalidate_handle()
2510 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; in _psr_invalidate_handle()
2541 mutex_lock(&intel_dp->psr.lock); in intel_psr_invalidate()
2542 if (!intel_dp->psr.enabled) { in intel_psr_invalidate()
2543 mutex_unlock(&intel_dp->psr.lock); in intel_psr_invalidate()
2548 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); in intel_psr_invalidate()
2549 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; in intel_psr_invalidate()
2554 mutex_unlock(&intel_dp->psr.lock); in intel_psr_invalidate()
2569 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled || in tgl_dc3co_flush_locked()
2570 !intel_dp->psr.active) in tgl_dc3co_flush_locked()
2578 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) in tgl_dc3co_flush_locked()
2582 mod_delayed_work(i915->unordered_wq, &intel_dp->psr.dc3co_work, in tgl_dc3co_flush_locked()
2583 intel_dp->psr.dc3co_exit_delay); in tgl_dc3co_flush_locked()
2589 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr_flush_handle()
2591 if (intel_dp->psr.psr2_sel_fetch_enabled) { in _psr_flush_handle()
2592 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { in _psr_flush_handle()
2594 if (intel_dp->psr.busy_frontbuffer_bits == 0) { in _psr_flush_handle()
2608 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); in _psr_flush_handle()
2609 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; in _psr_flush_handle()
2621 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) in _psr_flush_handle()
2622 queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); in _psr_flush_handle()
2648 mutex_lock(&intel_dp->psr.lock); in intel_psr_flush()
2649 if (!intel_dp->psr.enabled) { in intel_psr_flush()
2650 mutex_unlock(&intel_dp->psr.lock); in intel_psr_flush()
2655 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); in intel_psr_flush()
2656 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; in intel_psr_flush()
2663 if (intel_dp->psr.paused) in intel_psr_flush()
2668 !intel_dp->psr.psr2_sel_fetch_enabled)) { in intel_psr_flush()
2679 mutex_unlock(&intel_dp->psr.lock); in intel_psr_flush()
2715 intel_dp->psr.source_support = true; in intel_psr_init()
2720 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; in intel_psr_init()
2722 INIT_WORK(&intel_dp->psr.work, intel_psr_work); in intel_psr_init()
2723 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); in intel_psr_init()
2724 mutex_init(&intel_dp->psr.lock); in intel_psr_init()
2750 struct intel_psr *psr = &intel_dp->psr; in psr_alpm_check() local
2754 if (!psr->psr2_enabled) in psr_alpm_check()
2765 psr->sink_not_reliable = true; in psr_alpm_check()
2777 struct intel_psr *psr = &intel_dp->psr; in psr_capability_changed_check() local
2789 psr->sink_not_reliable = true; in psr_capability_changed_check()
2801 struct intel_psr *psr = &intel_dp->psr; in intel_psr_short_pulse() local
2810 mutex_lock(&psr->lock); in intel_psr_short_pulse()
2812 if (!psr->enabled) in intel_psr_short_pulse()
2823 psr->sink_not_reliable = true; in intel_psr_short_pulse()
2850 mutex_unlock(&psr->lock); in intel_psr_short_pulse()
2860 mutex_lock(&intel_dp->psr.lock); in intel_psr_enabled()
2861 ret = intel_dp->psr.enabled; in intel_psr_enabled()
2862 mutex_unlock(&intel_dp->psr.lock); in intel_psr_enabled()
2887 mutex_lock(&intel_dp->psr.lock); in intel_psr_lock()
2910 mutex_unlock(&intel_dp->psr.lock); in intel_psr_unlock()
2919 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_source_status()
2923 if (intel_dp->psr.psr2_enabled) { in psr_source_status()
2964 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_status()
2965 struct intel_psr *psr = &intel_dp->psr; in intel_psr_status() local
2971 seq_printf(m, "Sink support: %s", str_yes_no(psr->sink_support)); in intel_psr_status()
2972 if (psr->sink_support) in intel_psr_status()
2976 if (!psr->sink_support) in intel_psr_status()
2980 mutex_lock(&psr->lock); in intel_psr_status()
2982 if (psr->enabled) in intel_psr_status()
2983 status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled"; in intel_psr_status()
2988 if (!psr->enabled) { in intel_psr_status()
2990 str_yes_no(psr->sink_not_reliable)); in intel_psr_status()
2995 if (psr->psr2_enabled) { in intel_psr_status()
3006 psr->busy_frontbuffer_bits); in intel_psr_status()
3015 if (psr->debug & I915_PSR_DEBUG_IRQ) { in intel_psr_status()
3017 psr->last_entry_attempt); in intel_psr_status()
3018 seq_printf(m, "Last exit at: %lld\n", psr->last_exit); in intel_psr_status()
3021 if (psr->psr2_enabled) { in intel_psr_status()
3046 str_enabled_disabled(psr->psr2_sel_fetch_enabled)); in intel_psr_status()
3050 mutex_unlock(&psr->lock); in intel_psr_status()
3118 *val = READ_ONCE(intel_dp->psr.debug); in i915_edp_psr_debug_get()