85 static bool assert_dsb_has_room(struct intel_dsb *dsb)  in assert_dsb_has_room()  argument
87 	struct intel_crtc *crtc = dsb->crtc;  in assert_dsb_has_room()
91 	return !drm_WARN(&i915->drm, dsb->free_pos > dsb->size - 2,  in assert_dsb_has_room()
93 			 crtc->base.base.id, crtc->base.name, dsb->id);  in assert_dsb_has_room()
102 static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)  in intel_dsb_emit()  argument
104 	u32 *buf = dsb->cmd_buf;  in intel_dsb_emit()
106 	if (!assert_dsb_has_room(dsb))  in intel_dsb_emit()
110 	dsb->free_pos = ALIGN(dsb->free_pos, 2);  in intel_dsb_emit()
112 	dsb->ins_start_offset = dsb->free_pos;  in intel_dsb_emit()
114 	buf[dsb->free_pos++] = ldw;  in intel_dsb_emit()
115 	buf[dsb->free_pos++] = udw;  in intel_dsb_emit()
118 static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb,  in intel_dsb_prev_ins_is_write()  argument
121 	const u32 *buf = dsb->cmd_buf;  in intel_dsb_prev_ins_is_write()
124 	prev_opcode = buf[dsb->ins_start_offset + 1] >> DSB_OPCODE_SHIFT;  in intel_dsb_prev_ins_is_write()
125 	prev_reg = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;  in intel_dsb_prev_ins_is_write()
130 static bool intel_dsb_prev_ins_is_mmio_write(struct intel_dsb *dsb, i915_reg_t reg)  in intel_dsb_prev_ins_is_mmio_write()  argument
132 	return intel_dsb_prev_ins_is_write(dsb, DSB_OPCODE_MMIO_WRITE, reg);  in intel_dsb_prev_ins_is_mmio_write()
135 static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg)  in intel_dsb_prev_ins_is_indexed_write()  argument
137 	return intel_dsb_prev_ins_is_write(dsb, DSB_OPCODE_INDEXED_WRITE, reg);  in intel_dsb_prev_ins_is_indexed_write()
149 void intel_dsb_reg_write(struct intel_dsb *dsb,  in intel_dsb_reg_write()  argument
168 	if (!intel_dsb_prev_ins_is_mmio_write(dsb, reg) &&  in intel_dsb_reg_write()
169 	    !intel_dsb_prev_ins_is_indexed_write(dsb, reg)) {  in intel_dsb_reg_write()
170 		intel_dsb_emit(dsb, val,  in intel_dsb_reg_write()
175 		u32 *buf = dsb->cmd_buf;  in intel_dsb_reg_write()
177 		if (!assert_dsb_has_room(dsb))  in intel_dsb_reg_write()
181 		if (intel_dsb_prev_ins_is_mmio_write(dsb, reg)) {  in intel_dsb_reg_write()
182 			u32 prev_val = buf[dsb->ins_start_offset + 0];  in intel_dsb_reg_write()
184 			buf[dsb->ins_start_offset + 0] = 1; /* count */  in intel_dsb_reg_write()
185 			buf[dsb->ins_start_offset + 1] =  in intel_dsb_reg_write()
188 			buf[dsb->ins_start_offset + 2] = prev_val;  in intel_dsb_reg_write()
190 			dsb->free_pos++;  in intel_dsb_reg_write()
193 		buf[dsb->free_pos++] = val;  in intel_dsb_reg_write()
195 		buf[dsb->ins_start_offset]++;  in intel_dsb_reg_write()
198 		if (dsb->free_pos & 0x1)  in intel_dsb_reg_write()
199 			buf[dsb->free_pos] = 0;  in intel_dsb_reg_write()
203 static void intel_dsb_align_tail(struct intel_dsb *dsb)  in intel_dsb_align_tail()  argument
207 	tail = dsb->free_pos * 4;  in intel_dsb_align_tail()
211 		memset(&dsb->cmd_buf[dsb->free_pos], 0,  in intel_dsb_align_tail()
214 	dsb->free_pos = aligned_tail / 4;  in intel_dsb_align_tail()
217 void intel_dsb_finish(struct intel_dsb *dsb)  in intel_dsb_finish()  argument
219 	intel_dsb_align_tail(dsb);  in intel_dsb_finish()
229 void intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank)  in intel_dsb_commit()  argument
231 	struct intel_crtc *crtc = dsb->crtc;  in intel_dsb_commit()
236 	tail = dsb->free_pos * 4;  in intel_dsb_commit()
240 	if (is_dsb_busy(dev_priv, pipe, dsb->id)) {  in intel_dsb_commit()
242 			crtc->base.base.id, crtc->base.name, dsb->id);  in intel_dsb_commit()
246 	intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id),  in intel_dsb_commit()
249 	intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id),  in intel_dsb_commit()
250 		       i915_ggtt_offset(dsb->vma));  in intel_dsb_commit()
251 	intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id),  in intel_dsb_commit()
252 		       i915_ggtt_offset(dsb->vma) + tail);  in intel_dsb_commit()
255 void intel_dsb_wait(struct intel_dsb *dsb)  in intel_dsb_wait()  argument
257 	struct intel_crtc *crtc = dsb->crtc;  in intel_dsb_wait()
261 	if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1))  in intel_dsb_wait()
264 			crtc->base.base.id, crtc->base.name, dsb->id);  in intel_dsb_wait()
267 	dsb->free_pos = 0;  in intel_dsb_wait()
268 	dsb->ins_start_offset = 0;  in intel_dsb_wait()
269 	intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), 0);  in intel_dsb_wait()
289 	struct intel_dsb *dsb;  in intel_dsb_prepare()  local
297 	dsb = kzalloc(sizeof(*dsb), GFP_KERNEL);  in intel_dsb_prepare()
298 	if (!dsb)  in intel_dsb_prepare()
324 	dsb->id = DSB1;  in intel_dsb_prepare()
325 	dsb->vma = vma;  in intel_dsb_prepare()
326 	dsb->crtc = crtc;  in intel_dsb_prepare()
327 	dsb->cmd_buf = buf;  in intel_dsb_prepare()
328 	dsb->size = size / 4; /* in dwords */  in intel_dsb_prepare()
329 	dsb->free_pos = 0;  in intel_dsb_prepare()
330 	dsb->ins_start_offset = 0;  in intel_dsb_prepare()
332 	return dsb;  in intel_dsb_prepare()
336 	kfree(dsb);  in intel_dsb_prepare()
352 void intel_dsb_cleanup(struct intel_dsb *dsb)  in intel_dsb_cleanup()  argument
354 	i915_vma_unpin_and_release(&dsb->vma, I915_VMA_RELEASE_MAP);  in intel_dsb_cleanup()
355 	kfree(dsb);  in intel_dsb_cleanup()