933 			refclk = dev_priv->display.dpll.ref_clks.nssc;  in hsw_ddi_wrpll_get_freq()
1168 		i915->display.dpll.ref_clks.nssc = 24000;  in hsw_update_dpll_ref_clks()
1170 		i915->display.dpll.ref_clks.nssc = 135000;  in hsw_update_dpll_ref_clks()
1634 	int ref_clock = i915->display.dpll.ref_clks.nssc;  in skl_ddi_wrpll_get_freq()
1717 				      i915->display.dpll.ref_clks.nssc, &wrpll_params);  in skl_ddi_hdmi_pll_dividers()
1873 	i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;  in skl_update_dpll_ref_clks()
2162 	chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div);  in bxt_ddi_dp_pll_dividers()
2250 	return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock);  in bxt_ddi_pll_get_freq()
2325 	i915->display.dpll.ref_clks.nssc = 100000;  in bxt_update_dpll_ref_clks()
2468 		 i915->display.dpll.ref_clks.nssc == 38400;  in ehl_combo_pll_div_frac_wa_needed()
2562 		dev_priv->display.dpll.ref_clks.nssc == 24000 ?  in icl_calc_dp_combo_pll()
2585 		switch (dev_priv->display.dpll.ref_clks.nssc) {  in icl_calc_tbt_pll()
2587 			MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc);  in icl_calc_tbt_pll()
2598 		switch (dev_priv->display.dpll.ref_clks.nssc) {  in icl_calc_tbt_pll()
2600 			MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc);  in icl_calc_tbt_pll()
2630 	int ref_clock = i915->display.dpll.ref_clks.nssc;  in icl_wrpll_ref_clock()
2857 	int refclk_khz = dev_priv->display.dpll.ref_clks.nssc;  in icl_calc_mg_pll_state()
3063 	ref_clock = dev_priv->display.dpll.ref_clks.nssc;  in icl_ddi_mg_pll_get_freq()
3445 	if (dev_priv->display.dpll.ref_clks.nssc == 38400) {  in mg_pll_get_hw_state()
3945 	i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;  in icl_update_dpll_ref_clks()