33 	} dot, vco, n, m, m1, m2, p, p1;  member
41 	.dot = { .min = 25000, .max = 350000 },
54 	.dot = { .min = 25000, .max = 350000 },
67 	.dot = { .min = 25000, .max = 350000 },
80 	.dot = { .min = 20000, .max = 400000 },
93 	.dot = { .min = 20000, .max = 400000 },
107 	.dot = { .min = 25000, .max = 270000 },
122 	.dot = { .min = 22000, .max = 400000 },
135 	.dot = { .min = 20000, .max = 115000 },
149 	.dot = { .min = 80000, .max = 224000 },
163 	.dot = { .min = 20000, .max = 400000},
178 	.dot = { .min = 20000, .max = 400000 },
196 	.dot = { .min = 25000, .max = 350000 },
209 	.dot = { .min = 25000, .max = 350000 },
222 	.dot = { .min = 25000, .max = 350000 },
236 	.dot = { .min = 25000, .max = 350000 },
249 	.dot = { .min = 25000, .max = 350000 },
268 	.dot = { .min = 25000, .max = 270000 },
284 	.dot = { .min = 25000, .max = 540000 },
294 	.dot = { .min = 25000, .max = 594000 },
320 	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);  in pnv_calc_dpll_params()
322 	return clock->dot;  in pnv_calc_dpll_params()
337 	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);  in i9xx_calc_dpll_params()
339 	return clock->dot;  in i9xx_calc_dpll_params()
349 	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);  in vlv_calc_dpll_params()
351 	return clock->dot;  in vlv_calc_dpll_params()
362 	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);  in chv_calc_dpll_params()
364 	return clock->dot;  in chv_calc_dpll_params()
400 	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)  in intel_pll_is_valid()
476 					this_err = abs(clock.dot - target);  in i9xx_find_best_dpll()
532 					this_err = abs(clock.dot - target);  in pnv_find_best_dpll()
590 					this_err = abs(clock.dot - target);  in g4x_find_best_dpll()
628 				abs(target_freq - calculated_clock->dot),  in vlv_PLL_is_optimal()
1189 	crtc_state->port_clock = crtc_state->dpll.dot;  in ilk_crtc_compute_clock()
1262 	crtc_state->port_clock = crtc_state->dpll.dot;  in chv_crtc_compute_clock()
1288 	crtc_state->port_clock = crtc_state->dpll.dot;  in vlv_crtc_compute_clock()
1333 	crtc_state->port_clock = crtc_state->dpll.dot;  in g4x_crtc_compute_clock()
1371 	crtc_state->port_clock = crtc_state->dpll.dot;  in pnv_crtc_compute_clock()
1407 	crtc_state->port_clock = crtc_state->dpll.dot;  in i9xx_crtc_compute_clock()
1447 	crtc_state->port_clock = crtc_state->dpll.dot;  in i8xx_crtc_compute_clock()