1603 	intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);  in i9xx_enable_pll()
1604 	intel_de_write(dev_priv, DPLL(pipe), dpll);  in i9xx_enable_pll()
1607 	intel_de_posting_read(dev_priv, DPLL(pipe));  in i9xx_enable_pll()
1619 		intel_de_write(dev_priv, DPLL(pipe), dpll);  in i9xx_enable_pll()
1624 		intel_de_write(dev_priv, DPLL(pipe), dpll);  in i9xx_enable_pll()
1625 		intel_de_posting_read(dev_priv, DPLL(pipe));  in i9xx_enable_pll()
1755 	intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll);  in _vlv_enable_pll()
1756 	intel_de_posting_read(dev_priv, DPLL(pipe));  in _vlv_enable_pll()
1759 	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))  in _vlv_enable_pll()
1775 	intel_de_write(dev_priv, DPLL(pipe),  in vlv_enable_pll()
1906 	intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll);  in _chv_enable_pll()
1909 	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))  in _chv_enable_pll()
1925 	intel_de_write(dev_priv, DPLL(pipe),  in chv_enable_pll()
1951 			    (intel_de_read(dev_priv, DPLL(PIPE_B)) &  in chv_enable_pll()
2010 	intel_de_write(dev_priv, DPLL(pipe), val);  in vlv_disable_pll()
2011 	intel_de_posting_read(dev_priv, DPLL(pipe));  in vlv_disable_pll()
2027 	intel_de_write(dev_priv, DPLL(pipe), val);  in chv_disable_pll()
2028 	intel_de_posting_read(dev_priv, DPLL(pipe));  in chv_disable_pll()
2053 	intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);  in i9xx_disable_pll()
2054 	intel_de_posting_read(dev_priv, DPLL(pipe));  in i9xx_disable_pll()
2080 	cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;  in assert_pll()