33 	} dot, vco, n, m, m1, m2, p, p1;  member
45 	.m1 = { .min = 18, .max = 26 },
58 	.m1 = { .min = 18, .max = 26 },
71 	.m1 = { .min = 18, .max = 26 },
84 	.m1 = { .min = 8, .max = 18 },
97 	.m1 = { .min = 8, .max = 18 },
111 	.m1 = { .min = 17, .max = 23 },
126 	.m1 = { .min = 16, .max = 23 },
139 	.m1 = { .min = 17, .max = 23 },
153 	.m1 = { .min = 17, .max = 23 },
169 	.m1 = { .min = 0, .max = 0 },
182 	.m1 = { .min = 0, .max = 0 },
192  * We calculate clock using (register_value + 2) for N/M1/M2, so here
200 	.m1 = { .min = 12, .max = 22 },
213 	.m1 = { .min = 12, .max = 22 },
226 	.m1 = { .min = 12, .max = 22 },
240 	.m1 = { .min = 12, .max = 22 },
253 	.m1 = { .min = 12, .max = 22 },
271 	.m1 = { .min = 2, .max = 3 },
287 	.m1 = { .min = 2, .max = 2 },
297 	.m1 = { .min = 2, .max = 2 },
312 /* m1 is reserved as 0 in Pineview, n is a ring counter */
327 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);  in i9xx_dpll_compute_m()
344 	clock->m = clock->m1 * clock->m2;  in vlv_calc_dpll_params()
356 	clock->m = clock->m1 * clock->m2;  in chv_calc_dpll_params()
381 	if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)  in intel_pll_is_valid()
385 		if (clock->m1 <= clock->m2)  in intel_pll_is_valid()
455 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;  in i9xx_find_best_dpll()
456 	     clock.m1++) {  in i9xx_find_best_dpll()
459 			if (clock.m2 >= clock.m1)  in i9xx_find_best_dpll()
513 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;  in pnv_find_best_dpll()
514 	     clock.m1++) {  in pnv_find_best_dpll()
575 		/* based on hardware requirement, prefere larger m1,m2 */  in g4x_find_best_dpll()
576 		for (clock.m1 = limit->m1.max;  in g4x_find_best_dpll()
577 		     clock.m1 >= limit->m1.min; clock.m1--) {  in g4x_find_best_dpll()
671 				/* based on hardware requirement, prefer bigger m1,m2 values */  in vlv_find_best_dpll()
672 				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {  in vlv_find_best_dpll()
676 								     refclk * clock.m1);  in vlv_find_best_dpll()
724 	 * Based on hardware doc, the n always set to 1, and m1 always  in chv_find_best_dpll()
729 	clock.m1 = 2;  in chv_find_best_dpll()
740 						   refclk * clock.m1);  in chv_find_best_dpll()
742 			if (m2 > INT_MAX/clock.m1)  in chv_find_best_dpll()
778 	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;  in i9xx_dpll_compute_fp()
1671 	bestm1 = crtc_state->dpll.m1;  in vlv_prepare_pll()
1820 	/* Feedback refclk divider - n and m1 */  in chv_prepare_pll()