2707 		if (crtc_state->dither && crtc_state->pipe_bpp != 30)  in i9xx_set_pipeconf()
2711 		switch (crtc_state->pipe_bpp) {  in i9xx_set_pipeconf()
2714 			MISSING_CASE(crtc_state->pipe_bpp);  in i9xx_set_pipeconf()
2919 			pipe_config->pipe_bpp = 18;  in i9xx_get_pipe_config()
2922 			pipe_config->pipe_bpp = 24;  in i9xx_get_pipe_config()
2925 			pipe_config->pipe_bpp = 30;  in i9xx_get_pipe_config()
3033 	switch (crtc_state->pipe_bpp) {  in ilk_set_pipeconf()
3036 		MISSING_CASE(crtc_state->pipe_bpp);  in ilk_set_pipeconf()
3119 	switch (crtc_state->pipe_bpp) {  in bdw_set_pipe_misc()
3135 		MISSING_CASE(crtc_state->pipe_bpp);  in bdw_set_pipe_misc()
3311 		pipe_config->pipe_bpp = 18;  in ilk_get_pipe_config()
3314 		pipe_config->pipe_bpp = 24;  in ilk_get_pipe_config()
3317 		pipe_config->pipe_bpp = 30;  in ilk_get_pipe_config()
3320 		pipe_config->pipe_bpp = 36;  in ilk_get_pipe_config()
3954 	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)  in intel_crtc_dotclock()
3956 					     pipe_config->pipe_bpp);  in intel_crtc_dotclock()
4372 	if (bpp < crtc_state->pipe_bpp) {  in compute_sink_pipe_bpp()
4379 			    crtc_state->pipe_bpp);  in compute_sink_pipe_bpp()
4381 		crtc_state->pipe_bpp = bpp;  in compute_sink_pipe_bpp()
4406 	crtc_state->pipe_bpp = bpp;  in compute_baseline_pipe_bpp()
4676 	base_bpp = crtc_state->pipe_bpp;  in intel_modeset_pipe_config()
4778 	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&  in intel_modeset_pipe_config()
4783 		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);  in intel_modeset_pipe_config()
5353 		PIPE_CONF_CHECK_I(pipe_bpp);  in intel_pipe_config_compare()