Lines Matching +full:ganged +full:- +full:mode
2 * Copyright © 2006-2007 Intel Corporation
27 #include <linux/dma-resv.h>
148 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock()
162 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
163 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
165 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
177 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
180 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", in intel_update_czclk()
181 dev_priv->czclk_freq); in intel_update_czclk()
186 return (crtc_state->active_planes & in is_hdr_mode()
225 return crtc_state->master_transcoder != INVALID_TRANSCODER; in is_trans_port_sync_slave()
231 return crtc_state->sync_mode_slaves_mask != 0; in is_trans_port_sync_master()
243 return ffs(crtc_state->bigjoiner_pipes) - 1; in bigjoiner_master_pipe()
248 if (crtc_state->bigjoiner_pipes) in intel_crtc_bigjoiner_slave_pipes()
249 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); in intel_crtc_bigjoiner_slave_pipes()
256 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_is_bigjoiner_slave()
258 return crtc_state->bigjoiner_pipes && in intel_crtc_is_bigjoiner_slave()
259 crtc->pipe != bigjoiner_master_pipe(crtc_state); in intel_crtc_is_bigjoiner_slave()
264 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_is_bigjoiner_master()
266 return crtc_state->bigjoiner_pipes && in intel_crtc_is_bigjoiner_master()
267 crtc->pipe == bigjoiner_master_pipe(crtc_state); in intel_crtc_is_bigjoiner_master()
272 return hweight8(crtc_state->bigjoiner_pipes); in intel_bigjoiner_num_pipes()
277 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in intel_master_crtc()
282 return to_intel_crtc(crtc_state->uapi.crtc); in intel_master_crtc()
288 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in intel_wait_for_pipe_off()
289 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_wait_for_pipe_off()
292 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; in intel_wait_for_pipe_off()
297 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); in intel_wait_for_pipe_off()
333 struct drm_i915_private *i915 = to_i915(plane->base.dev); in assert_plane()
337 cur_state = plane->get_hw_state(plane, &pipe); in assert_plane()
341 plane->base.name, str_on_off(state), in assert_plane()
350 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in assert_planes_disabled()
353 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) in assert_planes_disabled()
364 switch (dig_port->base.port) { in vlv_wait_port_ready()
366 MISSING_CASE(dig_port->base.port); in vlv_wait_port_ready()
385 drm_WARN(&dev_priv->drm, 1, in vlv_wait_port_ready()
387 dig_port->base.base.base.id, dig_port->base.base.name, in vlv_wait_port_ready()
394 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); in intel_enable_transcoder()
395 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_enable_transcoder()
396 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; in intel_enable_transcoder()
397 enum pipe pipe = crtc->pipe; in intel_enable_transcoder()
401 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); in intel_enable_transcoder()
416 if (new_crtc_state->has_pch_encoder) { in intel_enable_transcoder()
426 /* Wa_22012358565:adl-p */ in intel_enable_transcoder()
435 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); in intel_enable_transcoder()
455 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in intel_disable_transcoder()
456 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_disable_transcoder()
457 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; in intel_disable_transcoder()
458 enum pipe pipe = crtc->pipe; in intel_disable_transcoder()
462 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); in intel_disable_transcoder()
479 if (old_crtc_state->double_wide) in intel_disable_transcoder()
503 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) in intel_rotation_info_size()
504 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; in intel_rotation_info_size()
514 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { in intel_remapped_info_size()
517 if (rem_info->plane[i].linear) in intel_remapped_info_size()
518 plane_size = rem_info->plane[i].size; in intel_remapped_info_size()
520 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; in intel_remapped_info_size()
525 if (rem_info->plane_alignment) in intel_remapped_info_size()
526 size = ALIGN(size, rem_info->plane_alignment); in intel_remapped_info_size()
536 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_plane_uses_fence()
537 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in intel_plane_uses_fence()
540 (plane->fbc && in intel_plane_uses_fence()
541 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); in intel_plane_uses_fence()
547 * offset is only used with linear buffers on pre-hsw and tiled buffers
554 const struct drm_framebuffer *fb = state->hw.fb; in intel_fb_xy_to_linear()
555 unsigned int cpp = fb->format->cpp[color_plane]; in intel_fb_xy_to_linear()
556 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; in intel_fb_xy_to_linear()
562 * Add the x/y offsets derived from fb->offsets[] to the user
571 *x += state->view.color_plane[color_plane].x; in intel_add_fb_offsets()
572 *y += state->view.color_plane[color_plane].y; in intel_add_fb_offsets()
593 plane = to_intel_plane(crtc->base.primary); in intel_plane_fb_max_stride()
595 return plane->max_stride(plane, pixel_format, modifier, in intel_plane_fb_max_stride()
603 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_set_plane_visible()
605 plane_state->uapi.visible = visible; in intel_set_plane_visible()
608 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); in intel_set_plane_visible()
610 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); in intel_set_plane_visible()
615 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_plane_fixup_bitmasks()
623 crtc_state->enabled_planes = 0; in intel_plane_fixup_bitmasks()
624 crtc_state->active_planes = 0; in intel_plane_fixup_bitmasks()
626 drm_for_each_plane_mask(plane, &dev_priv->drm, in intel_plane_fixup_bitmasks()
627 crtc_state->uapi.plane_mask) { in intel_plane_fixup_bitmasks()
628 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); in intel_plane_fixup_bitmasks()
629 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); in intel_plane_fixup_bitmasks()
636 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_plane_disable_noatomic()
638 to_intel_crtc_state(crtc->base.state); in intel_plane_disable_noatomic()
640 to_intel_plane_state(plane->base.state); in intel_plane_disable_noatomic()
642 drm_dbg_kms(&dev_priv->drm, in intel_plane_disable_noatomic()
644 plane->base.base.id, plane->base.name, in intel_plane_disable_noatomic()
645 crtc->base.base.id, crtc->base.name); in intel_plane_disable_noatomic()
649 crtc_state->data_rate[plane->id] = 0; in intel_plane_disable_noatomic()
650 crtc_state->data_rate_y[plane->id] = 0; in intel_plane_disable_noatomic()
651 crtc_state->rel_data_rate[plane->id] = 0; in intel_plane_disable_noatomic()
652 crtc_state->rel_data_rate_y[plane->id] = 0; in intel_plane_disable_noatomic()
653 crtc_state->min_cdclk[plane->id] = 0; in intel_plane_disable_noatomic()
655 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && in intel_plane_disable_noatomic()
657 crtc_state->ips_enabled = false; in intel_plane_disable_noatomic()
663 * are blocked if the memory self-refresh mode is active at that in intel_plane_disable_noatomic()
665 * first the self-refresh mode. The self-refresh enable bit in turn in intel_plane_disable_noatomic()
668 * wait-for-vblank between disabling the plane and the pipe. in intel_plane_disable_noatomic()
678 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) in intel_plane_disable_noatomic()
679 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); in intel_plane_disable_noatomic()
691 plane_state->view.color_plane[0].offset, 0); in intel_plane_fence_y_offset()
698 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in icl_set_pipe_chicken()
699 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in icl_set_pipe_chicken()
700 enum pipe pipe = crtc->pipe; in icl_set_pipe_chicken()
708 * and rounding for per-pixel values 00 and 0xff in icl_set_pipe_chicken()
740 drm_for_each_crtc(crtc, &dev_priv->drm) { in intel_has_pending_fb_unpin()
742 spin_lock(&crtc->commit_lock); in intel_has_pending_fb_unpin()
743 commit = list_first_entry_or_null(&crtc->commit_list, in intel_has_pending_fb_unpin()
746 try_wait_for_completion(&commit->cleanup_done) : true; in intel_has_pending_fb_unpin()
747 spin_unlock(&crtc->commit_lock); in intel_has_pending_fb_unpin()
777 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { in intel_get_crtc_new_encoder()
778 if (connector_state->crtc != &master_crtc->base) in intel_get_crtc_new_encoder()
781 encoder = to_intel_encoder(connector_state->best_encoder); in intel_get_crtc_new_encoder()
785 drm_WARN(state->base.dev, num_encoders != 1, in intel_get_crtc_new_encoder()
787 num_encoders, pipe_name(master_crtc->pipe)); in intel_get_crtc_new_encoder()
794 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_pfit_enable()
795 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_pfit_enable()
796 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; in ilk_pfit_enable()
797 enum pipe pipe = crtc->pipe; in ilk_pfit_enable()
800 int x = dst->x1; in ilk_pfit_enable()
801 int y = dst->y1; in ilk_pfit_enable()
803 if (!crtc_state->pch_pfit.enabled) in ilk_pfit_enable()
806 /* Force use of hard-coded filter coefficients in ilk_pfit_enable()
807 * as some pre-programmed values are broken, in ilk_pfit_enable()
824 if (crtc->overlay) in intel_crtc_dpms_overlay_disable()
825 (void) intel_overlay_switch_off(crtc->overlay); in intel_crtc_dpms_overlay_disable()
834 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in needs_nv12_wa()
836 if (!crtc_state->nv12_planes) in needs_nv12_wa()
848 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in needs_scalerclk_wa()
851 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) in needs_scalerclk_wa()
859 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in needs_cursorclk_wa()
863 crtc_state->active_planes & BIT(PLANE_CURSOR) && in needs_cursorclk_wa()
891 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in needs_async_flip_vtd_wa()
893 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && in needs_async_flip_vtd_wa()
898 ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
899 (new_crtc_state)->feature)
901 ((old_crtc_state)->feature && \
902 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
934 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_post_plane_update()
939 enum pipe pipe = crtc->pipe; in intel_post_plane_update()
941 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); in intel_post_plane_update()
943 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) in intel_post_plane_update()
973 u8 update_planes = crtc_state->update_planes; in intel_crtc_enable_flip_done()
979 if (plane->pipe == crtc->pipe && in intel_crtc_enable_flip_done()
980 update_planes & BIT(plane->id)) in intel_crtc_enable_flip_done()
981 plane->enable_flip_done(plane); in intel_crtc_enable_flip_done()
990 u8 update_planes = crtc_state->update_planes; in intel_crtc_disable_flip_done()
996 if (plane->pipe == crtc->pipe && in intel_crtc_disable_flip_done()
997 update_planes & BIT(plane->id)) in intel_crtc_disable_flip_done()
998 plane->disable_flip_done(plane); in intel_crtc_disable_flip_done()
1009 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes & in intel_crtc_async_flip_disable_wa()
1010 ~new_crtc_state->async_flip_planes; in intel_crtc_async_flip_disable_wa()
1017 if (plane->need_async_flip_disable_wa && in intel_crtc_async_flip_disable_wa()
1018 plane->pipe == crtc->pipe && in intel_crtc_async_flip_disable_wa()
1019 disable_async_flip_planes & BIT(plane->id)) { in intel_crtc_async_flip_disable_wa()
1024 plane->async_flip(plane, old_crtc_state, in intel_crtc_async_flip_disable_wa()
1037 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_pre_plane_update()
1042 enum pipe pipe = crtc->pipe; in intel_pre_plane_update()
1080 * are blocked if the memory self-refresh mode is active at that in intel_pre_plane_update()
1082 * first the self-refresh mode. The self-refresh enable bit in turn in intel_pre_plane_update()
1085 * wait-for-vblank between disabling the plane and the pipe. in intel_pre_plane_update()
1087 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && in intel_pre_plane_update()
1088 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) in intel_pre_plane_update()
1093 * one frame before enabling scaling. LP watermarks can be re-enabled in intel_pre_plane_update()
1098 if (old_crtc_state->hw.active && in intel_pre_plane_update()
1099 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) in intel_pre_plane_update()
1104 * pre-vblank watermark programming here. in intel_pre_plane_update()
1109 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these in intel_pre_plane_update()
1110 * will be the intermediate values that are safe for both pre- and in intel_pre_plane_update()
1111 * post- vblank; when vblank happens, the 'active' values will be set in intel_pre_plane_update()
1122 if (new_crtc_state->update_wm_pre) in intel_pre_plane_update()
1141 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes) in intel_pre_plane_update()
1148 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_disable_planes()
1151 unsigned int update_mask = new_crtc_state->update_planes; in intel_crtc_disable_planes()
1160 if (crtc->pipe != plane->pipe || in intel_crtc_disable_planes()
1161 !(update_mask & BIT(plane->id))) in intel_crtc_disable_planes()
1166 if (old_plane_state->uapi.visible) in intel_crtc_disable_planes()
1167 fb_bits |= plane->frontbuffer_bit; in intel_crtc_disable_planes()
1175 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_encoders_update_prepare()
1181 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. in intel_encoders_update_prepare()
1182 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. in intel_encoders_update_prepare()
1184 if (i915->display.dpll.mgr) { in intel_encoders_update_prepare()
1189 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; in intel_encoders_update_prepare()
1190 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; in intel_encoders_update_prepare()
1204 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in intel_encoders_pre_pll_enable()
1206 to_intel_encoder(conn_state->best_encoder); in intel_encoders_pre_pll_enable()
1208 if (conn_state->crtc != &crtc->base) in intel_encoders_pre_pll_enable()
1211 if (encoder->pre_pll_enable) in intel_encoders_pre_pll_enable()
1212 encoder->pre_pll_enable(state, encoder, in intel_encoders_pre_pll_enable()
1226 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in intel_encoders_pre_enable()
1228 to_intel_encoder(conn_state->best_encoder); in intel_encoders_pre_enable()
1230 if (conn_state->crtc != &crtc->base) in intel_encoders_pre_enable()
1233 if (encoder->pre_enable) in intel_encoders_pre_enable()
1234 encoder->pre_enable(state, encoder, in intel_encoders_pre_enable()
1248 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in intel_encoders_enable()
1250 to_intel_encoder(conn_state->best_encoder); in intel_encoders_enable()
1252 if (conn_state->crtc != &crtc->base) in intel_encoders_enable()
1255 if (encoder->enable) in intel_encoders_enable()
1256 encoder->enable(state, encoder, in intel_encoders_enable()
1271 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { in intel_encoders_disable()
1273 to_intel_encoder(old_conn_state->best_encoder); in intel_encoders_disable()
1275 if (old_conn_state->crtc != &crtc->base) in intel_encoders_disable()
1279 if (encoder->disable) in intel_encoders_disable()
1280 encoder->disable(state, encoder, in intel_encoders_disable()
1294 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { in intel_encoders_post_disable()
1296 to_intel_encoder(old_conn_state->best_encoder); in intel_encoders_post_disable()
1298 if (old_conn_state->crtc != &crtc->base) in intel_encoders_post_disable()
1301 if (encoder->post_disable) in intel_encoders_post_disable()
1302 encoder->post_disable(state, encoder, in intel_encoders_post_disable()
1316 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { in intel_encoders_post_pll_disable()
1318 to_intel_encoder(old_conn_state->best_encoder); in intel_encoders_post_pll_disable()
1320 if (old_conn_state->crtc != &crtc->base) in intel_encoders_post_pll_disable()
1323 if (encoder->post_pll_disable) in intel_encoders_post_pll_disable()
1324 encoder->post_pll_disable(state, encoder, in intel_encoders_post_pll_disable()
1338 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in intel_encoders_update_pipe()
1340 to_intel_encoder(conn_state->best_encoder); in intel_encoders_update_pipe()
1342 if (conn_state->crtc != &crtc->base) in intel_encoders_update_pipe()
1345 if (encoder->update_pipe) in intel_encoders_update_pipe()
1346 encoder->update_pipe(state, encoder, in intel_encoders_update_pipe()
1353 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_disable_primary_plane()
1354 struct intel_plane *plane = to_intel_plane(crtc->base.primary); in intel_disable_primary_plane()
1356 plane->disable_arm(plane, crtc_state); in intel_disable_primary_plane()
1361 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_configure_cpu_transcoder()
1362 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in ilk_configure_cpu_transcoder()
1364 if (crtc_state->has_pch_encoder) { in ilk_configure_cpu_transcoder()
1366 &crtc_state->fdi_m_n); in ilk_configure_cpu_transcoder()
1369 &crtc_state->dp_m_n); in ilk_configure_cpu_transcoder()
1371 &crtc_state->dp_m2_n2); in ilk_configure_cpu_transcoder()
1384 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_crtc_enable()
1385 enum pipe pipe = crtc->pipe; in ilk_crtc_enable()
1387 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) in ilk_crtc_enable()
1407 crtc->active = true; in ilk_crtc_enable()
1411 if (new_crtc_state->has_pch_encoder) { in ilk_crtc_enable()
1433 if (new_crtc_state->has_pch_encoder) in ilk_crtc_enable()
1449 if (new_crtc_state->has_pch_encoder) { in ilk_crtc_enable()
1473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_set_linetime_wm()
1474 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_set_linetime_wm()
1476 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), in hsw_set_linetime_wm()
1477 HSW_LINETIME(crtc_state->linetime) | in hsw_set_linetime_wm()
1478 HSW_IPS_LINETIME(crtc_state->ips_linetime)); in hsw_set_linetime_wm()
1483 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_set_frame_start_delay()
1484 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_set_frame_start_delay()
1485 enum transcoder transcoder = crtc_state->cpu_transcoder; in hsw_set_frame_start_delay()
1491 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); in hsw_set_frame_start_delay()
1500 * Enable sequence steps 1-7 on bigjoiner master in icl_ddi_bigjoiner_pre_enable()
1505 if (crtc_state->shared_dpll) in icl_ddi_bigjoiner_pre_enable()
1514 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_configure_cpu_transcoder()
1515 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_configure_cpu_transcoder()
1516 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in hsw_configure_cpu_transcoder()
1518 if (crtc_state->has_pch_encoder) { in hsw_configure_cpu_transcoder()
1520 &crtc_state->fdi_m_n); in hsw_configure_cpu_transcoder()
1523 &crtc_state->dp_m_n); in hsw_configure_cpu_transcoder()
1525 &crtc_state->dp_m2_n2); in hsw_configure_cpu_transcoder()
1534 crtc_state->pixel_multiplier - 1); in hsw_configure_cpu_transcoder()
1546 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_crtc_enable()
1547 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; in hsw_crtc_enable()
1548 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; in hsw_crtc_enable()
1551 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) in hsw_crtc_enable()
1554 intel_dmc_enable_pipe(dev_priv, crtc->pipe); in hsw_crtc_enable()
1556 if (!new_crtc_state->bigjoiner_pipes) { in hsw_crtc_enable()
1559 if (new_crtc_state->shared_dpll) in hsw_crtc_enable()
1580 crtc->active = true; in hsw_crtc_enable()
1584 new_crtc_state->pch_pfit.enabled; in hsw_crtc_enable()
1623 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; in hsw_crtc_enable()
1636 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in ilk_pfit_disable()
1637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_pfit_disable()
1638 enum pipe pipe = crtc->pipe; in ilk_pfit_disable()
1642 if (!old_crtc_state->pch_pfit.enabled) in ilk_pfit_disable()
1655 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_crtc_disable()
1656 enum pipe pipe = crtc->pipe; in ilk_crtc_disable()
1674 if (old_crtc_state->has_pch_encoder) in ilk_crtc_disable()
1679 if (old_crtc_state->has_pch_encoder) in ilk_crtc_disable()
1693 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in hsw_crtc_disable()
1697 * Need care with mst->ddi interactions. in hsw_crtc_disable()
1711 intel_dmc_disable_pipe(i915, crtc->pipe); in hsw_crtc_disable()
1713 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, in hsw_crtc_disable()
1715 intel_dmc_disable_pipe(i915, slave_crtc->pipe); in hsw_crtc_disable()
1721 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_pfit_enable()
1722 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_pfit_enable()
1724 if (!crtc_state->gmch_pfit.control) in i9xx_pfit_enable()
1731 drm_WARN_ON(&dev_priv->drm, in i9xx_pfit_enable()
1733 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_pfit_enable()
1736 crtc_state->gmch_pfit.pgm_ratios); in i9xx_pfit_enable()
1737 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); in i9xx_pfit_enable()
1741 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); in i9xx_pfit_enable()
1797 return PHY_D + port - PORT_D_XELPD; in intel_port_to_phy()
1799 return PHY_F + port - PORT_TC1; in intel_port_to_phy()
1801 return PHY_B + port - PORT_TC1; in intel_port_to_phy()
1803 return PHY_C + port - PORT_TC1; in intel_port_to_phy()
1808 return PHY_A + port - PORT_A; in intel_port_to_phy()
1817 return TC_PORT_1 + port - PORT_TC1; in intel_port_to_tc()
1819 return TC_PORT_1 + port - PORT_C; in intel_port_to_tc()
1825 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_aux_power_domain()
1828 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); in intel_aux_power_domain()
1830 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); in intel_aux_power_domain()
1836 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in get_crtc_power_domains()
1837 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in get_crtc_power_domains()
1838 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in get_crtc_power_domains()
1840 enum pipe pipe = crtc->pipe; in get_crtc_power_domains()
1842 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); in get_crtc_power_domains()
1844 if (!crtc_state->hw.active) in get_crtc_power_domains()
1847 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); in get_crtc_power_domains()
1848 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); in get_crtc_power_domains()
1849 if (crtc_state->pch_pfit.enabled || in get_crtc_power_domains()
1850 crtc_state->pch_pfit.force_thru) in get_crtc_power_domains()
1851 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); in get_crtc_power_domains()
1853 drm_for_each_encoder_mask(encoder, &dev_priv->drm, in get_crtc_power_domains()
1854 crtc_state->uapi.encoder_mask) { in get_crtc_power_domains()
1857 set_bit(intel_encoder->power_domain, mask->bits); in get_crtc_power_domains()
1860 if (HAS_DDI(dev_priv) && crtc_state->has_audio) in get_crtc_power_domains()
1861 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); in get_crtc_power_domains()
1863 if (crtc_state->shared_dpll) in get_crtc_power_domains()
1864 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); in get_crtc_power_domains()
1866 if (crtc_state->dsc.compression_enable) in get_crtc_power_domains()
1867 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); in get_crtc_power_domains()
1873 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_modeset_get_crtc_power_domains()
1874 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_modeset_get_crtc_power_domains()
1882 crtc->enabled_power_domains.mask.bits, in intel_modeset_get_crtc_power_domains()
1884 bitmap_andnot(old_domains->bits, in intel_modeset_get_crtc_power_domains()
1885 crtc->enabled_power_domains.mask.bits, in intel_modeset_get_crtc_power_domains()
1891 &crtc->enabled_power_domains, in intel_modeset_get_crtc_power_domains()
1898 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), in intel_modeset_put_crtc_power_domains()
1899 &crtc->enabled_power_domains, in intel_modeset_put_crtc_power_domains()
1905 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_configure_cpu_transcoder()
1906 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in i9xx_configure_cpu_transcoder()
1910 &crtc_state->dp_m_n); in i9xx_configure_cpu_transcoder()
1912 &crtc_state->dp_m2_n2); in i9xx_configure_cpu_transcoder()
1925 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in valleyview_crtc_enable()
1926 enum pipe pipe = crtc->pipe; in valleyview_crtc_enable()
1928 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) in valleyview_crtc_enable()
1942 crtc->active = true; in valleyview_crtc_enable()
1976 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_crtc_enable()
1977 enum pipe pipe = crtc->pipe; in i9xx_crtc_enable()
1979 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) in i9xx_crtc_enable()
1986 crtc->active = true; in i9xx_crtc_enable()
2018 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in i9xx_pfit_disable()
2019 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_pfit_disable()
2021 if (!old_crtc_state->gmch_pfit.control) in i9xx_pfit_disable()
2024 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); in i9xx_pfit_disable()
2026 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", in i9xx_pfit_disable()
2036 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_crtc_disable()
2037 enum pipe pipe = crtc->pipe; in i9xx_crtc_disable()
2070 if (!dev_priv->display.funcs.wm->initial_watermarks) in i9xx_crtc_disable()
2088 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_supports_double_wide()
2092 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); in intel_crtc_supports_double_wide()
2097 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; in ilk_pipe_pixel_rate()
2101 * We only use IF-ID interlacing. If we ever use in ilk_pipe_pixel_rate()
2102 * PF-ID we'll need to adjust the pixel_rate here. in ilk_pipe_pixel_rate()
2105 if (!crtc_state->pch_pfit.enabled) in ilk_pipe_pixel_rate()
2109 drm_rect_width(&crtc_state->pipe_src) << 16, in ilk_pipe_pixel_rate()
2110 drm_rect_height(&crtc_state->pipe_src) << 16); in ilk_pipe_pixel_rate()
2112 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, in ilk_pipe_pixel_rate()
2116 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, in intel_mode_from_crtc_timings() argument
2119 mode->hdisplay = timings->crtc_hdisplay; in intel_mode_from_crtc_timings()
2120 mode->htotal = timings->crtc_htotal; in intel_mode_from_crtc_timings()
2121 mode->hsync_start = timings->crtc_hsync_start; in intel_mode_from_crtc_timings()
2122 mode->hsync_end = timings->crtc_hsync_end; in intel_mode_from_crtc_timings()
2124 mode->vdisplay = timings->crtc_vdisplay; in intel_mode_from_crtc_timings()
2125 mode->vtotal = timings->crtc_vtotal; in intel_mode_from_crtc_timings()
2126 mode->vsync_start = timings->crtc_vsync_start; in intel_mode_from_crtc_timings()
2127 mode->vsync_end = timings->crtc_vsync_end; in intel_mode_from_crtc_timings()
2129 mode->flags = timings->flags; in intel_mode_from_crtc_timings()
2130 mode->type = DRM_MODE_TYPE_DRIVER; in intel_mode_from_crtc_timings()
2132 mode->clock = timings->crtc_clock; in intel_mode_from_crtc_timings()
2134 drm_mode_set_name(mode); in intel_mode_from_crtc_timings()
2139 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_crtc_compute_pixel_rate()
2143 crtc_state->pixel_rate = in intel_crtc_compute_pixel_rate()
2144 crtc_state->hw.pipe_mode.crtc_clock; in intel_crtc_compute_pixel_rate()
2146 crtc_state->pixel_rate = in intel_crtc_compute_pixel_rate()
2151 struct drm_display_mode *mode) in intel_bigjoiner_adjust_timings() argument
2158 mode->crtc_clock /= num_pipes; in intel_bigjoiner_adjust_timings()
2159 mode->crtc_hdisplay /= num_pipes; in intel_bigjoiner_adjust_timings()
2160 mode->crtc_hblank_start /= num_pipes; in intel_bigjoiner_adjust_timings()
2161 mode->crtc_hblank_end /= num_pipes; in intel_bigjoiner_adjust_timings()
2162 mode->crtc_hsync_start /= num_pipes; in intel_bigjoiner_adjust_timings()
2163 mode->crtc_hsync_end /= num_pipes; in intel_bigjoiner_adjust_timings()
2164 mode->crtc_htotal /= num_pipes; in intel_bigjoiner_adjust_timings()
2168 struct drm_display_mode *mode) in intel_splitter_adjust_timings() argument
2170 int overlap = crtc_state->splitter.pixel_overlap; in intel_splitter_adjust_timings()
2171 int n = crtc_state->splitter.link_count; in intel_splitter_adjust_timings()
2173 if (!crtc_state->splitter.enable) in intel_splitter_adjust_timings()
2178 * timings, but full mode for everything else. in intel_splitter_adjust_timings()
2180 * h_full = (h_segment - pixel_overlap) * link_count in intel_splitter_adjust_timings()
2182 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; in intel_splitter_adjust_timings()
2183 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; in intel_splitter_adjust_timings()
2184 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; in intel_splitter_adjust_timings()
2185 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; in intel_splitter_adjust_timings()
2186 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; in intel_splitter_adjust_timings()
2187 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; in intel_splitter_adjust_timings()
2188 mode->crtc_clock *= n; in intel_splitter_adjust_timings()
2193 struct drm_display_mode *mode = &crtc_state->hw.mode; in intel_crtc_readout_derived_state() local
2194 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; in intel_crtc_readout_derived_state()
2195 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_crtc_readout_derived_state()
2203 /* Expand MSO per-segment transcoder timings to full */ in intel_crtc_readout_derived_state()
2213 /* Populate the "user" mode with full numbers */ in intel_crtc_readout_derived_state()
2214 drm_mode_copy(mode, pipe_mode); in intel_crtc_readout_derived_state()
2215 intel_mode_from_crtc_timings(mode, mode); in intel_crtc_readout_derived_state()
2216 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * in intel_crtc_readout_derived_state()
2218 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); in intel_crtc_readout_derived_state()
2220 /* Derive per-pipe timings in case bigjoiner is used */ in intel_crtc_readout_derived_state()
2230 encoder->get_config(encoder, crtc_state); in intel_encoder_get_config()
2243 width = drm_rect_width(&crtc_state->pipe_src); in intel_bigjoiner_compute_pipe_src()
2244 height = drm_rect_height(&crtc_state->pipe_src); in intel_bigjoiner_compute_pipe_src()
2246 drm_rect_init(&crtc_state->pipe_src, 0, 0, in intel_bigjoiner_compute_pipe_src()
2252 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_compute_pipe_src()
2253 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_crtc_compute_pipe_src()
2259 * - DVO ganged mode in intel_crtc_compute_pipe_src()
2260 * - LVDS dual channel mode in intel_crtc_compute_pipe_src()
2261 * - Double wide pipe in intel_crtc_compute_pipe_src()
2263 if (drm_rect_width(&crtc_state->pipe_src) & 1) { in intel_crtc_compute_pipe_src()
2264 if (crtc_state->double_wide) { in intel_crtc_compute_pipe_src()
2265 drm_dbg_kms(&i915->drm, in intel_crtc_compute_pipe_src()
2267 crtc->base.base.id, crtc->base.name); in intel_crtc_compute_pipe_src()
2268 return -EINVAL; in intel_crtc_compute_pipe_src()
2273 drm_dbg_kms(&i915->drm, in intel_crtc_compute_pipe_src()
2275 crtc->base.base.id, crtc->base.name); in intel_crtc_compute_pipe_src()
2276 return -EINVAL; in intel_crtc_compute_pipe_src()
2285 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_compute_pipe_mode()
2286 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_crtc_compute_pipe_mode()
2287 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_crtc_compute_pipe_mode()
2288 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; in intel_crtc_compute_pipe_mode()
2289 int clock_limit = i915->max_dotclk_freq; in intel_crtc_compute_pipe_mode()
2297 /* Expand MSO per-segment transcoder timings to full */ in intel_crtc_compute_pipe_mode()
2300 /* Derive per-pipe timings in case bigjoiner is used */ in intel_crtc_compute_pipe_mode()
2305 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; in intel_crtc_compute_pipe_mode()
2308 * Enable double wide mode when the dot clock in intel_crtc_compute_pipe_mode()
2312 pipe_mode->crtc_clock > clock_limit) { in intel_crtc_compute_pipe_mode()
2313 clock_limit = i915->max_dotclk_freq; in intel_crtc_compute_pipe_mode()
2314 crtc_state->double_wide = true; in intel_crtc_compute_pipe_mode()
2318 if (pipe_mode->crtc_clock > clock_limit) { in intel_crtc_compute_pipe_mode()
2319 drm_dbg_kms(&i915->drm, in intel_crtc_compute_pipe_mode()
2321 crtc->base.base.id, crtc->base.name, in intel_crtc_compute_pipe_mode()
2322 pipe_mode->crtc_clock, clock_limit, in intel_crtc_compute_pipe_mode()
2323 str_yes_no(crtc_state->double_wide)); in intel_crtc_compute_pipe_mode()
2324 return -EINVAL; in intel_crtc_compute_pipe_mode()
2351 if (crtc_state->has_pch_encoder) in intel_crtc_compute_config()
2397 m_n->tu = 64; in intel_link_compute_m_n()
2398 compute_m_n(&m_n->data_m, &m_n->data_n, in intel_link_compute_m_n()
2402 compute_m_n(&m_n->link_m, &m_n->link_n, in intel_link_compute_m_n()
2420 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) { in intel_panel_sanitize_ssc()
2421 drm_dbg_kms(&dev_priv->drm, in intel_panel_sanitize_ssc()
2424 str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc)); in intel_panel_sanitize_ssc()
2425 dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc; in intel_panel_sanitize_ssc()
2434 m_n->tu = 1; in intel_zero_m_n()
2442 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); in intel_set_m_n()
2443 intel_de_write(i915, data_n_reg, m_n->data_n); in intel_set_m_n()
2444 intel_de_write(i915, link_m_reg, m_n->link_m); in intel_set_m_n()
2449 intel_de_write(i915, link_n_reg, m_n->link_n); in intel_set_m_n()
2465 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_cpu_transcoder_set_m1_n1()
2466 enum pipe pipe = crtc->pipe; in intel_cpu_transcoder_set_m1_n1()
2482 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_cpu_transcoder_set_m2_n2()
2494 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_set_transcoder_timings()
2495 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_set_transcoder_timings()
2496 enum pipe pipe = crtc->pipe; in intel_set_transcoder_timings()
2497 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_set_transcoder_timings()
2498 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_set_transcoder_timings()
2502 /* We need to be careful not to changed the adjusted mode, for otherwise in intel_set_transcoder_timings()
2504 crtc_vdisplay = adjusted_mode->crtc_vdisplay; in intel_set_transcoder_timings()
2505 crtc_vtotal = adjusted_mode->crtc_vtotal; in intel_set_transcoder_timings()
2506 crtc_vblank_start = adjusted_mode->crtc_vblank_start; in intel_set_transcoder_timings()
2507 crtc_vblank_end = adjusted_mode->crtc_vblank_end; in intel_set_transcoder_timings()
2509 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { in intel_set_transcoder_timings()
2511 crtc_vtotal -= 1; in intel_set_transcoder_timings()
2512 crtc_vblank_end -= 1; in intel_set_transcoder_timings()
2515 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; in intel_set_transcoder_timings()
2517 vsyncshift = adjusted_mode->crtc_hsync_start - in intel_set_transcoder_timings()
2518 adjusted_mode->crtc_htotal / 2; in intel_set_transcoder_timings()
2520 vsyncshift += adjusted_mode->crtc_htotal; in intel_set_transcoder_timings()
2529 crtc_vblank_start - crtc_vdisplay); in intel_set_transcoder_timings()
2543 HACTIVE(adjusted_mode->crtc_hdisplay - 1) | in intel_set_transcoder_timings()
2544 HTOTAL(adjusted_mode->crtc_htotal - 1)); in intel_set_transcoder_timings()
2546 HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | in intel_set_transcoder_timings()
2547 HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); in intel_set_transcoder_timings()
2549 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | in intel_set_transcoder_timings()
2550 HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); in intel_set_transcoder_timings()
2553 VACTIVE(crtc_vdisplay - 1) | in intel_set_transcoder_timings()
2554 VTOTAL(crtc_vtotal - 1)); in intel_set_transcoder_timings()
2556 VBLANK_START(crtc_vblank_start - 1) | in intel_set_transcoder_timings()
2557 VBLANK_END(crtc_vblank_end - 1)); in intel_set_transcoder_timings()
2559 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | in intel_set_transcoder_timings()
2560 VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); in intel_set_transcoder_timings()
2569 VACTIVE(crtc_vdisplay - 1) | in intel_set_transcoder_timings()
2570 VTOTAL(crtc_vtotal - 1)); in intel_set_transcoder_timings()
2575 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_set_pipe_src_size()
2576 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_set_pipe_src_size()
2577 int width = drm_rect_width(&crtc_state->pipe_src); in intel_set_pipe_src_size()
2578 int height = drm_rect_height(&crtc_state->pipe_src); in intel_set_pipe_src_size()
2579 enum pipe pipe = crtc->pipe; in intel_set_pipe_src_size()
2585 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); in intel_set_pipe_src_size()
2590 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_pipe_is_interlaced()
2591 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_pipe_is_interlaced()
2606 struct drm_device *dev = crtc->base.dev; in intel_get_transcoder_timings()
2608 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_get_transcoder_timings()
2609 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_get_transcoder_timings()
2613 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; in intel_get_transcoder_timings()
2614 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; in intel_get_transcoder_timings()
2618 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; in intel_get_transcoder_timings()
2619 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; in intel_get_transcoder_timings()
2623 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; in intel_get_transcoder_timings()
2624 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; in intel_get_transcoder_timings()
2627 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; in intel_get_transcoder_timings()
2628 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; in intel_get_transcoder_timings()
2633 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; in intel_get_transcoder_timings()
2634 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; in intel_get_transcoder_timings()
2637 adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; in intel_get_transcoder_timings()
2638 adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; in intel_get_transcoder_timings()
2641 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; in intel_get_transcoder_timings()
2642 adjusted_mode->crtc_vtotal += 1; in intel_get_transcoder_timings()
2643 adjusted_mode->crtc_vblank_end += 1; in intel_get_transcoder_timings()
2647 adjusted_mode->crtc_vblank_start = in intel_get_transcoder_timings()
2648 adjusted_mode->crtc_vdisplay + in intel_get_transcoder_timings()
2654 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_bigjoiner_adjust_pipe_src()
2656 enum pipe master_pipe, pipe = crtc->pipe; in intel_bigjoiner_adjust_pipe_src()
2663 width = drm_rect_width(&crtc_state->pipe_src); in intel_bigjoiner_adjust_pipe_src()
2665 drm_rect_translate_to(&crtc_state->pipe_src, in intel_bigjoiner_adjust_pipe_src()
2666 (pipe - master_pipe) * width, 0); in intel_bigjoiner_adjust_pipe_src()
2672 struct drm_device *dev = crtc->base.dev; in intel_get_pipe_src_size()
2676 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); in intel_get_pipe_src_size()
2678 drm_rect_init(&pipe_config->pipe_src, 0, 0, in intel_get_pipe_src_size()
2687 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_set_pipeconf()
2688 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_set_pipeconf()
2689 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in i9xx_set_pipeconf()
2693 * - We keep both pipes enabled on 830 in i9xx_set_pipeconf()
2694 * - During modeset the pipe is still disabled and must remain so in i9xx_set_pipeconf()
2695 * - During fastset the pipe is already enabled and must remain so in i9xx_set_pipeconf()
2700 if (crtc_state->double_wide) in i9xx_set_pipeconf()
2707 if (crtc_state->dither && crtc_state->pipe_bpp != 30) in i9xx_set_pipeconf()
2711 switch (crtc_state->pipe_bpp) { in i9xx_set_pipeconf()
2714 MISSING_CASE(crtc_state->pipe_bpp); in i9xx_set_pipeconf()
2728 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { in i9xx_set_pipeconf()
2739 crtc_state->limited_color_range) in i9xx_set_pipeconf()
2742 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); in i9xx_set_pipeconf()
2744 if (crtc_state->wgc_enable) in i9xx_set_pipeconf()
2747 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); in i9xx_set_pipeconf()
2764 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_get_pfit_config()
2765 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_get_pfit_config()
2782 if (pipe != crtc->pipe) in i9xx_get_pfit_config()
2785 crtc_state->gmch_pfit.control = tmp; in i9xx_get_pfit_config()
2786 crtc_state->gmch_pfit.pgm_ratios = in i9xx_get_pfit_config()
2793 struct drm_device *dev = crtc->base.dev; in vlv_crtc_clock_get()
2795 enum pipe pipe = crtc->pipe; in vlv_crtc_clock_get()
2801 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
2814 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); in vlv_crtc_clock_get()
2820 struct drm_device *dev = crtc->base.dev; in chv_crtc_clock_get()
2822 enum pipe pipe = crtc->pipe; in chv_crtc_clock_get()
2829 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
2848 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); in chv_crtc_clock_get()
2854 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in bdw_get_pipe_misc_output_format()
2857 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); in bdw_get_pipe_misc_output_format()
2860 /* We support 4:2:0 in full blend mode only */ in bdw_get_pipe_misc_output_format()
2861 drm_WARN_ON(&dev_priv->drm, in bdw_get_pipe_misc_output_format()
2874 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_get_pipe_color_config()
2875 struct intel_plane *plane = to_intel_plane(crtc->base.primary); in i9xx_get_pipe_color_config()
2876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_get_pipe_color_config()
2877 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_get_pipe_color_config()
2883 crtc_state->gamma_enable = true; in i9xx_get_pipe_color_config()
2887 crtc_state->csc_enable = true; in i9xx_get_pipe_color_config()
2893 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_get_pipe_config()
2899 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); in i9xx_get_pipe_config()
2904 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in i9xx_get_pipe_config()
2905 pipe_config->sink_format = pipe_config->output_format; in i9xx_get_pipe_config()
2906 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in i9xx_get_pipe_config()
2907 pipe_config->shared_dpll = NULL; in i9xx_get_pipe_config()
2911 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); in i9xx_get_pipe_config()
2919 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
2922 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
2925 pipe_config->pipe_bpp = 30; in i9xx_get_pipe_config()
2935 pipe_config->limited_color_range = true; in i9xx_get_pipe_config()
2937 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp); in i9xx_get_pipe_config()
2939 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; in i9xx_get_pipe_config()
2943 pipe_config->wgc_enable = true; in i9xx_get_pipe_config()
2946 pipe_config->cgm_mode = intel_de_read(dev_priv, in i9xx_get_pipe_config()
2947 CGM_PIPE_MODE(crtc->pipe)); in i9xx_get_pipe_config()
2953 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; in i9xx_get_pipe_config()
2962 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) in i9xx_get_pipe_config()
2963 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; in i9xx_get_pipe_config()
2965 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); in i9xx_get_pipe_config()
2966 pipe_config->pixel_multiplier = in i9xx_get_pipe_config()
2969 pipe_config->dpll_hw_state.dpll_md = tmp; in i9xx_get_pipe_config()
2972 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); in i9xx_get_pipe_config()
2973 pipe_config->pixel_multiplier = in i9xx_get_pipe_config()
2978 * port and will be fixed up in the encoder->get_config in i9xx_get_pipe_config()
2980 pipe_config->pixel_multiplier = 1; in i9xx_get_pipe_config()
2982 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, in i9xx_get_pipe_config()
2983 DPLL(crtc->pipe)); in i9xx_get_pipe_config()
2985 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, in i9xx_get_pipe_config()
2986 FP0(crtc->pipe)); in i9xx_get_pipe_config()
2987 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, in i9xx_get_pipe_config()
2988 FP1(crtc->pipe)); in i9xx_get_pipe_config()
2990 /* Mask out read-only status bits. */ in i9xx_get_pipe_config()
2991 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | in i9xx_get_pipe_config()
3008 pipe_config->hw.adjusted_mode.crtc_clock = in i9xx_get_pipe_config()
3009 pipe_config->port_clock / pipe_config->pixel_multiplier; in i9xx_get_pipe_config()
3021 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_set_pipeconf()
3022 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_set_pipeconf()
3023 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in ilk_set_pipeconf()
3027 * - During modeset the pipe is still disabled and must remain so in ilk_set_pipeconf()
3028 * - During fastset the pipe is already enabled and must remain so in ilk_set_pipeconf()
3033 switch (crtc_state->pipe_bpp) { in ilk_set_pipeconf()
3036 MISSING_CASE(crtc_state->pipe_bpp); in ilk_set_pipeconf()
3052 if (crtc_state->dither) in ilk_set_pipeconf()
3055 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in ilk_set_pipeconf()
3064 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && in ilk_set_pipeconf()
3065 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); in ilk_set_pipeconf()
3067 if (crtc_state->limited_color_range && in ilk_set_pipeconf()
3071 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) in ilk_set_pipeconf()
3074 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); in ilk_set_pipeconf()
3076 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); in ilk_set_pipeconf()
3077 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); in ilk_set_pipeconf()
3085 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_set_transconf()
3086 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_set_transconf()
3087 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in hsw_set_transconf()
3091 * - During modeset the pipe is still disabled and must remain so in hsw_set_transconf()
3092 * - During fastset the pipe is already enabled and must remain so in hsw_set_transconf()
3097 if (IS_HASWELL(dev_priv) && crtc_state->dither) in hsw_set_transconf()
3100 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in hsw_set_transconf()
3106 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) in hsw_set_transconf()
3115 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in bdw_set_pipe_misc()
3116 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in bdw_set_pipe_misc()
3119 switch (crtc_state->pipe_bpp) { in bdw_set_pipe_misc()
3135 MISSING_CASE(crtc_state->pipe_bpp); in bdw_set_pipe_misc()
3139 if (crtc_state->dither) in bdw_set_pipe_misc()
3142 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || in bdw_set_pipe_misc()
3143 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) in bdw_set_pipe_misc()
3146 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) in bdw_set_pipe_misc()
3160 intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val); in bdw_set_pipe_misc()
3165 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in bdw_get_pipe_misc_bpp()
3168 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); in bdw_get_pipe_misc_bpp()
3213 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; in intel_get_m_n()
3214 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; in intel_get_m_n()
3215 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; in intel_get_m_n()
3216 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; in intel_get_m_n()
3217 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; in intel_get_m_n()
3224 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_cpu_transcoder_get_m1_n1()
3225 enum pipe pipe = crtc->pipe; in intel_cpu_transcoder_get_m1_n1()
3241 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_cpu_transcoder_get_m2_n2()
3253 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_get_pfit_config()
3254 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_get_pfit_config()
3258 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); in ilk_get_pfit_config()
3265 pipe = crtc->pipe; in ilk_get_pfit_config()
3267 crtc_state->pch_pfit.enabled = true; in ilk_get_pfit_config()
3269 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); in ilk_get_pfit_config()
3270 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); in ilk_get_pfit_config()
3272 drm_rect_init(&crtc_state->pch_pfit.dst, in ilk_get_pfit_config()
3283 drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe); in ilk_get_pfit_config()
3289 struct drm_device *dev = crtc->base.dev; in ilk_get_pipe_config()
3296 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); in ilk_get_pipe_config()
3301 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in ilk_get_pipe_config()
3302 pipe_config->shared_dpll = NULL; in ilk_get_pipe_config()
3305 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); in ilk_get_pipe_config()
3311 pipe_config->pipe_bpp = 18; in ilk_get_pipe_config()
3314 pipe_config->pipe_bpp = 24; in ilk_get_pipe_config()
3317 pipe_config->pipe_bpp = 30; in ilk_get_pipe_config()
3320 pipe_config->pipe_bpp = 36; in ilk_get_pipe_config()
3327 pipe_config->limited_color_range = true; in ilk_get_pipe_config()
3332 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; in ilk_get_pipe_config()
3335 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in ilk_get_pipe_config()
3339 pipe_config->sink_format = pipe_config->output_format; in ilk_get_pipe_config()
3341 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp); in ilk_get_pipe_config()
3343 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; in ilk_get_pipe_config()
3345 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp); in ilk_get_pipe_config()
3347 pipe_config->csc_mode = intel_de_read(dev_priv, in ilk_get_pipe_config()
3348 PIPE_CSC_MODE(crtc->pipe)); in ilk_get_pipe_config()
3353 pipe_config->pixel_multiplier = 1; in ilk_get_pipe_config()
3381 return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask; in bigjoiner_pipes()
3407 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, in enabled_bigjoiner_pipes()
3410 enum pipe pipe = crtc->pipe; in enabled_bigjoiner_pipes()
3441 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, in enabled_bigjoiner_pipes()
3455 return fls(master_pipes) - 1; in get_bigjoiner_master_pipe()
3472 next_master_pipe = ffs(master_pipes) - 1; in get_bigjoiner_slave_pipes()
3474 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); in get_bigjoiner_slave_pipes()
3489 struct drm_device *dev = crtc->base.dev; in hsw_enabled_transcoders()
3535 if (trans_pipe == crtc->pipe) in hsw_enabled_transcoders()
3540 cpu_transcoder = (enum transcoder) crtc->pipe; in hsw_enabled_transcoders()
3544 /* bigjoiner slave -> consider the master pipe's transcoder as well */ in hsw_enabled_transcoders()
3546 if (slave_pipes & BIT(crtc->pipe)) { in hsw_enabled_transcoders()
3548 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); in hsw_enabled_transcoders()
3578 drm_WARN_ON(&i915->drm, in assert_enabled_transcoders()
3583 /* Only DSI transcoders can be ganged */ in assert_enabled_transcoders()
3584 drm_WARN_ON(&i915->drm, in assert_enabled_transcoders()
3593 struct drm_device *dev = crtc->base.dev; in hsw_get_transcoder_state()
3609 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; in hsw_get_transcoder_state()
3612 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) in hsw_get_transcoder_state()
3615 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { in hsw_get_transcoder_state()
3616 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); in hsw_get_transcoder_state()
3619 pipe_config->pch_pfit.force_thru = true; in hsw_get_transcoder_state()
3622 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); in hsw_get_transcoder_state()
3631 struct drm_device *dev = crtc->base.dev; in bxt_get_dsi_transcoder_state()
3657 /* XXX: this works for video mode only */ in bxt_get_dsi_transcoder_state()
3663 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) in bxt_get_dsi_transcoder_state()
3666 pipe_config->cpu_transcoder = cpu_transcoder; in bxt_get_dsi_transcoder_state()
3670 return transcoder_is_dsi(pipe_config->cpu_transcoder); in bxt_get_dsi_transcoder_state()
3675 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_bigjoiner_get_config()
3676 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_bigjoiner_get_config()
3678 enum pipe pipe = crtc->pipe; in intel_bigjoiner_get_config()
3685 crtc_state->bigjoiner_pipes = in intel_bigjoiner_get_config()
3693 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_get_pipe_config()
3697 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, in hsw_get_pipe_config()
3698 POWER_DOMAIN_PIPE(crtc->pipe))) in hsw_get_pipe_config()
3701 pipe_config->shared_dpll = NULL; in hsw_get_pipe_config()
3703 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); in hsw_get_pipe_config()
3706 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { in hsw_get_pipe_config()
3707 drm_WARN_ON(&dev_priv->drm, active); in hsw_get_pipe_config()
3717 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || in hsw_get_pipe_config()
3721 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) in hsw_get_pipe_config()
3728 TRANSCONF(pipe_config->cpu_transcoder)); in hsw_get_pipe_config()
3731 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; in hsw_get_pipe_config()
3733 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in hsw_get_pipe_config()
3735 pipe_config->output_format = in hsw_get_pipe_config()
3739 pipe_config->sink_format = pipe_config->output_format; in hsw_get_pipe_config()
3741 pipe_config->gamma_mode = intel_de_read(dev_priv, in hsw_get_pipe_config()
3742 GAMMA_MODE(crtc->pipe)); in hsw_get_pipe_config()
3744 pipe_config->csc_mode = intel_de_read(dev_priv, in hsw_get_pipe_config()
3745 PIPE_CSC_MODE(crtc->pipe)); in hsw_get_pipe_config()
3748 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); in hsw_get_pipe_config()
3751 pipe_config->gamma_enable = true; in hsw_get_pipe_config()
3754 pipe_config->csc_enable = true; in hsw_get_pipe_config()
3761 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); in hsw_get_pipe_config()
3762 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); in hsw_get_pipe_config()
3764 pipe_config->ips_linetime = in hsw_get_pipe_config()
3767 if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, in hsw_get_pipe_config()
3768 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { in hsw_get_pipe_config()
3777 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && in hsw_get_pipe_config()
3778 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { in hsw_get_pipe_config()
3779 pipe_config->pixel_multiplier = in hsw_get_pipe_config()
3781 TRANS_MULT(pipe_config->cpu_transcoder)) + 1; in hsw_get_pipe_config()
3783 pipe_config->pixel_multiplier = 1; in hsw_get_pipe_config()
3786 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { in hsw_get_pipe_config()
3788 MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) : in hsw_get_pipe_config()
3789 CHICKEN_TRANS(pipe_config->cpu_transcoder)); in hsw_get_pipe_config()
3791 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; in hsw_get_pipe_config()
3794 pipe_config->framestart_delay = 1; in hsw_get_pipe_config()
3798 intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains); in hsw_get_pipe_config()
3805 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_get_pipe_config()
3806 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_crtc_get_pipe_config()
3808 if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state)) in intel_crtc_get_pipe_config()
3811 crtc_state->hw.active = true; in intel_crtc_get_pipe_config()
3822 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk()
3825 return dev_priv->display.vbt.lvds_ssc_freq; in i9xx_pll_refclk()
3834 /* Returns the clock of the currently programmed mode of the given pipe. */
3838 struct drm_device *dev = crtc->base.dev; in i9xx_crtc_clock_get()
3840 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_crtc_clock_get()
3847 fp = pipe_config->dpll_hw_state.fp0; in i9xx_crtc_clock_get()
3849 fp = pipe_config->dpll_hw_state.fp1; in i9xx_crtc_clock_get()
3853 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; in i9xx_crtc_clock_get()
3878 drm_dbg_kms(&dev_priv->drm, in i9xx_crtc_clock_get()
3879 "Unknown DPLL mode %08x in programmed " in i9xx_crtc_clock_get()
3880 "mode\n", (int)(dpll & DPLL_MODE_MASK)); in i9xx_crtc_clock_get()
3893 lvds_pipe == crtc->pipe) { in i9xx_crtc_clock_get()
3924 pipe_config->port_clock = port_clock; in i9xx_crtc_clock_get()
3940 if (!m_n->link_n) in intel_dotclock_calculate()
3943 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq), in intel_dotclock_calculate()
3944 m_n->link_n); in intel_dotclock_calculate()
3952 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in intel_crtc_dotclock()
3953 &pipe_config->dp_m_n); in intel_crtc_dotclock()
3954 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) in intel_crtc_dotclock()
3955 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, in intel_crtc_dotclock()
3956 pipe_config->pipe_bpp); in intel_crtc_dotclock()
3958 dotclock = pipe_config->port_clock; in intel_crtc_dotclock()
3960 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && in intel_crtc_dotclock()
3964 if (pipe_config->pixel_multiplier) in intel_crtc_dotclock()
3965 dotclock /= pipe_config->pixel_multiplier; in intel_crtc_dotclock()
3970 /* Returns the currently programmed mode of the given encoder. */
3974 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_encoder_current_mode()
3976 struct drm_display_mode *mode; in intel_encoder_current_mode() local
3980 if (!encoder->get_hw_state(encoder, &pipe)) in intel_encoder_current_mode()
3985 mode = kzalloc(sizeof(*mode), GFP_KERNEL); in intel_encoder_current_mode()
3986 if (!mode) in intel_encoder_current_mode()
3991 kfree(mode); in intel_encoder_current_mode()
3997 kfree(mode); in intel_encoder_current_mode()
4003 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); in intel_encoder_current_mode()
4007 return mode; in intel_encoder_current_mode()
4014 return a == b || (a->cloneable & BIT(b->type) && in encoders_cloneable()
4015 b->cloneable & BIT(a->type)); in encoders_cloneable()
4027 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { in check_single_encoder_cloning()
4028 if (connector_state->crtc != &crtc->base) in check_single_encoder_cloning()
4032 to_intel_encoder(connector_state->best_encoder); in check_single_encoder_cloning()
4047 linked = plane_state->planar_linked_plane; in icl_add_linked_planes()
4056 drm_WARN_ON(state->base.dev, in icl_add_linked_planes()
4057 linked_plane_state->planar_linked_plane != plane); in icl_add_linked_planes()
4058 drm_WARN_ON(state->base.dev, in icl_add_linked_planes()
4059 linked_plane_state->planar_slave == plane_state->planar_slave); in icl_add_linked_planes()
4067 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in icl_check_nv12_planes()
4068 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in icl_check_nv12_planes()
4069 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); in icl_check_nv12_planes()
4079 * in the crtc_state->active_planes mask. in icl_check_nv12_planes()
4082 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) in icl_check_nv12_planes()
4085 plane_state->planar_linked_plane = NULL; in icl_check_nv12_planes()
4086 if (plane_state->planar_slave && !plane_state->uapi.visible) { in icl_check_nv12_planes()
4087 crtc_state->enabled_planes &= ~BIT(plane->id); in icl_check_nv12_planes()
4088 crtc_state->active_planes &= ~BIT(plane->id); in icl_check_nv12_planes()
4089 crtc_state->update_planes |= BIT(plane->id); in icl_check_nv12_planes()
4090 crtc_state->data_rate[plane->id] = 0; in icl_check_nv12_planes()
4091 crtc_state->rel_data_rate[plane->id] = 0; in icl_check_nv12_planes()
4094 plane_state->planar_slave = false; in icl_check_nv12_planes()
4097 if (!crtc_state->nv12_planes) in icl_check_nv12_planes()
4103 if (plane->pipe != crtc->pipe || in icl_check_nv12_planes()
4104 !(crtc_state->nv12_planes & BIT(plane->id))) in icl_check_nv12_planes()
4107 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { in icl_check_nv12_planes()
4108 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) in icl_check_nv12_planes()
4111 if (crtc_state->active_planes & BIT(linked->id)) in icl_check_nv12_planes()
4122 drm_dbg_kms(&dev_priv->drm, in icl_check_nv12_planes()
4124 hweight8(crtc_state->nv12_planes)); in icl_check_nv12_planes()
4126 return -EINVAL; in icl_check_nv12_planes()
4129 plane_state->planar_linked_plane = linked; in icl_check_nv12_planes()
4131 linked_state->planar_slave = true; in icl_check_nv12_planes()
4132 linked_state->planar_linked_plane = plane; in icl_check_nv12_planes()
4133 crtc_state->enabled_planes |= BIT(linked->id); in icl_check_nv12_planes()
4134 crtc_state->active_planes |= BIT(linked->id); in icl_check_nv12_planes()
4135 crtc_state->update_planes |= BIT(linked->id); in icl_check_nv12_planes()
4136 crtc_state->data_rate[linked->id] = in icl_check_nv12_planes()
4137 crtc_state->data_rate_y[plane->id]; in icl_check_nv12_planes()
4138 crtc_state->rel_data_rate[linked->id] = in icl_check_nv12_planes()
4139 crtc_state->rel_data_rate_y[plane->id]; in icl_check_nv12_planes()
4140 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", in icl_check_nv12_planes()
4141 linked->base.name, plane->base.name); in icl_check_nv12_planes()
4144 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; in icl_check_nv12_planes()
4145 linked_state->color_ctl = plane_state->color_ctl; in icl_check_nv12_planes()
4146 linked_state->view = plane_state->view; in icl_check_nv12_planes()
4147 linked_state->decrypt = plane_state->decrypt; in icl_check_nv12_planes()
4150 linked_state->uapi.src = plane_state->uapi.src; in icl_check_nv12_planes()
4151 linked_state->uapi.dst = plane_state->uapi.dst; in icl_check_nv12_planes()
4153 if (icl_is_hdr_plane(dev_priv, plane->id)) { in icl_check_nv12_planes()
4154 if (linked->id == PLANE_SPRITE5) in icl_check_nv12_planes()
4155 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; in icl_check_nv12_planes()
4156 else if (linked->id == PLANE_SPRITE4) in icl_check_nv12_planes()
4157 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; in icl_check_nv12_planes()
4158 else if (linked->id == PLANE_SPRITE3) in icl_check_nv12_planes()
4159 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; in icl_check_nv12_planes()
4160 else if (linked->id == PLANE_SPRITE2) in icl_check_nv12_planes()
4161 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; in icl_check_nv12_planes()
4163 MISSING_CASE(linked->id); in icl_check_nv12_planes()
4172 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); in c8_planes_changed()
4174 to_intel_atomic_state(new_crtc_state->uapi.state); in c8_planes_changed()
4178 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; in c8_planes_changed()
4184 &crtc_state->hw.pipe_mode; in hsw_linetime_wm()
4187 if (!crtc_state->hw.enable) in hsw_linetime_wm()
4190 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, in hsw_linetime_wm()
4191 pipe_mode->crtc_clock); in hsw_linetime_wm()
4200 &crtc_state->hw.pipe_mode; in hsw_ips_linetime_wm()
4203 if (!crtc_state->hw.enable) in hsw_ips_linetime_wm()
4206 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, in hsw_ips_linetime_wm()
4207 cdclk_state->logical.cdclk); in hsw_ips_linetime_wm()
4214 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in skl_linetime_wm()
4215 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in skl_linetime_wm()
4217 &crtc_state->hw.pipe_mode; in skl_linetime_wm()
4220 if (!crtc_state->hw.enable) in skl_linetime_wm()
4223 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, in skl_linetime_wm()
4224 crtc_state->pixel_rate); in skl_linetime_wm()
4237 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_compute_linetime_wm()
4243 crtc_state->linetime = skl_linetime_wm(crtc_state); in hsw_compute_linetime_wm()
4245 crtc_state->linetime = hsw_linetime_wm(crtc_state); in hsw_compute_linetime_wm()
4254 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, in hsw_compute_linetime_wm()
4263 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_atomic_check()
4270 !crtc_state->hw.active) in intel_crtc_atomic_check()
4271 crtc_state->update_wm_post = true; in intel_crtc_atomic_check()
4284 crtc_state->uapi.color_mgmt_changed = true; in intel_crtc_atomic_check()
4294 drm_dbg_kms(&dev_priv->drm, in intel_crtc_atomic_check()
4306 drm_dbg_kms(&dev_priv->drm, in intel_crtc_atomic_check()
4349 struct drm_connector *connector = conn_state->connector; in compute_sink_pipe_bpp()
4350 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in compute_sink_pipe_bpp()
4351 const struct drm_display_info *info = &connector->display_info; in compute_sink_pipe_bpp()
4354 switch (conn_state->max_bpc) { in compute_sink_pipe_bpp()
4368 MISSING_CASE(conn_state->max_bpc); in compute_sink_pipe_bpp()
4369 return -EINVAL; in compute_sink_pipe_bpp()
4372 if (bpp < crtc_state->pipe_bpp) { in compute_sink_pipe_bpp()
4373 drm_dbg_kms(&i915->drm, in compute_sink_pipe_bpp()
4376 connector->base.id, connector->name, in compute_sink_pipe_bpp()
4377 bpp, 3 * info->bpc, in compute_sink_pipe_bpp()
4378 3 * conn_state->max_requested_bpc, in compute_sink_pipe_bpp()
4379 crtc_state->pipe_bpp); in compute_sink_pipe_bpp()
4381 crtc_state->pipe_bpp = bpp; in compute_sink_pipe_bpp()
4391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in compute_baseline_pipe_bpp()
4406 crtc_state->pipe_bpp = bpp; in compute_baseline_pipe_bpp()
4409 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { in compute_baseline_pipe_bpp()
4412 if (connector_state->crtc != &crtc->base) in compute_baseline_pipe_bpp()
4425 struct drm_device *dev = state->base.dev; in check_digital_port_conflicts()
4433 * We're going to peek into connector->state, in check_digital_port_conflicts()
4436 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); in check_digital_port_conflicts()
4449 drm_atomic_get_new_connector_state(&state->base, in check_digital_port_conflicts()
4452 connector_state = connector->state; in check_digital_port_conflicts()
4454 if (!connector_state->best_encoder) in check_digital_port_conflicts()
4457 encoder = to_intel_encoder(connector_state->best_encoder); in check_digital_port_conflicts()
4459 drm_WARN_ON(dev, !connector_state->crtc); in check_digital_port_conflicts()
4461 switch (encoder->type) { in check_digital_port_conflicts()
4470 if (used_ports & BIT(encoder->port)) in check_digital_port_conflicts()
4473 used_ports |= BIT(encoder->port); in check_digital_port_conflicts()
4477 1 << encoder->port; in check_digital_port_conflicts()
4501 drm_property_replace_blob(&crtc_state->hw.degamma_lut, in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4502 crtc_state->uapi.degamma_lut); in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4503 drm_property_replace_blob(&crtc_state->hw.gamma_lut, in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4504 crtc_state->uapi.gamma_lut); in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4505 drm_property_replace_blob(&crtc_state->hw.ctm, in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4506 crtc_state->uapi.ctm); in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4518 crtc_state->hw.enable = crtc_state->uapi.enable; in intel_crtc_copy_uapi_to_hw_state_modeset()
4519 crtc_state->hw.active = crtc_state->uapi.active; in intel_crtc_copy_uapi_to_hw_state_modeset()
4520 drm_mode_copy(&crtc_state->hw.mode, in intel_crtc_copy_uapi_to_hw_state_modeset()
4521 &crtc_state->uapi.mode); in intel_crtc_copy_uapi_to_hw_state_modeset()
4522 drm_mode_copy(&crtc_state->hw.adjusted_mode, in intel_crtc_copy_uapi_to_hw_state_modeset()
4523 &crtc_state->uapi.adjusted_mode); in intel_crtc_copy_uapi_to_hw_state_modeset()
4524 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; in intel_crtc_copy_uapi_to_hw_state_modeset()
4539 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, in copy_bigjoiner_crtc_state_nomodeset()
4540 master_crtc_state->hw.degamma_lut); in copy_bigjoiner_crtc_state_nomodeset()
4541 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, in copy_bigjoiner_crtc_state_nomodeset()
4542 master_crtc_state->hw.gamma_lut); in copy_bigjoiner_crtc_state_nomodeset()
4543 drm_property_replace_blob(&slave_crtc_state->hw.ctm, in copy_bigjoiner_crtc_state_nomodeset()
4544 master_crtc_state->hw.ctm); in copy_bigjoiner_crtc_state_nomodeset()
4546 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; in copy_bigjoiner_crtc_state_nomodeset()
4560 WARN_ON(master_crtc_state->bigjoiner_pipes != in copy_bigjoiner_crtc_state_modeset()
4561 slave_crtc_state->bigjoiner_pipes); in copy_bigjoiner_crtc_state_modeset()
4565 return -ENOMEM; in copy_bigjoiner_crtc_state_modeset()
4568 saved_state->uapi = slave_crtc_state->uapi; in copy_bigjoiner_crtc_state_modeset()
4569 saved_state->scaler_state = slave_crtc_state->scaler_state; in copy_bigjoiner_crtc_state_modeset()
4570 saved_state->shared_dpll = slave_crtc_state->shared_dpll; in copy_bigjoiner_crtc_state_modeset()
4571 saved_state->crc_enabled = slave_crtc_state->crc_enabled; in copy_bigjoiner_crtc_state_modeset()
4577 /* Re-init hw state */ in copy_bigjoiner_crtc_state_modeset()
4578 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); in copy_bigjoiner_crtc_state_modeset()
4579 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; in copy_bigjoiner_crtc_state_modeset()
4580 slave_crtc_state->hw.active = master_crtc_state->hw.active; in copy_bigjoiner_crtc_state_modeset()
4581 drm_mode_copy(&slave_crtc_state->hw.mode, in copy_bigjoiner_crtc_state_modeset()
4582 &master_crtc_state->hw.mode); in copy_bigjoiner_crtc_state_modeset()
4583 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, in copy_bigjoiner_crtc_state_modeset()
4584 &master_crtc_state->hw.pipe_mode); in copy_bigjoiner_crtc_state_modeset()
4585 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, in copy_bigjoiner_crtc_state_modeset()
4586 &master_crtc_state->hw.adjusted_mode); in copy_bigjoiner_crtc_state_modeset()
4587 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; in copy_bigjoiner_crtc_state_modeset()
4591 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; in copy_bigjoiner_crtc_state_modeset()
4592 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; in copy_bigjoiner_crtc_state_modeset()
4593 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; in copy_bigjoiner_crtc_state_modeset()
4595 WARN_ON(master_crtc_state->bigjoiner_pipes != in copy_bigjoiner_crtc_state_modeset()
4596 slave_crtc_state->bigjoiner_pipes); in copy_bigjoiner_crtc_state_modeset()
4607 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_prepare_cleared_state()
4612 return -ENOMEM; in intel_crtc_prepare_cleared_state()
4614 /* free the old crtc_state->hw members */ in intel_crtc_prepare_cleared_state()
4622 saved_state->uapi = crtc_state->uapi; in intel_crtc_prepare_cleared_state()
4623 saved_state->inherited = crtc_state->inherited; in intel_crtc_prepare_cleared_state()
4624 saved_state->scaler_state = crtc_state->scaler_state; in intel_crtc_prepare_cleared_state()
4625 saved_state->shared_dpll = crtc_state->shared_dpll; in intel_crtc_prepare_cleared_state()
4626 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; in intel_crtc_prepare_cleared_state()
4627 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, in intel_crtc_prepare_cleared_state()
4628 sizeof(saved_state->icl_port_dplls)); in intel_crtc_prepare_cleared_state()
4629 saved_state->crc_enabled = crtc_state->crc_enabled; in intel_crtc_prepare_cleared_state()
4632 saved_state->wm = crtc_state->wm; in intel_crtc_prepare_cleared_state()
4646 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_modeset_pipe_config()
4655 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; in intel_modeset_pipe_config()
4657 crtc_state->framestart_delay = 1; in intel_modeset_pipe_config()
4664 if (!(crtc_state->hw.adjusted_mode.flags & in intel_modeset_pipe_config()
4666 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; in intel_modeset_pipe_config()
4668 if (!(crtc_state->hw.adjusted_mode.flags & in intel_modeset_pipe_config()
4670 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; in intel_modeset_pipe_config()
4676 base_bpp = crtc_state->pipe_bpp; in intel_modeset_pipe_config()
4682 * is stored in the crtc timings. We use the requested mode to do this in intel_modeset_pipe_config()
4683 * computation to clearly distinguish it from the adjusted mode, which in intel_modeset_pipe_config()
4686 drm_mode_get_hv_timing(&crtc_state->hw.mode, in intel_modeset_pipe_config()
4688 drm_rect_init(&crtc_state->pipe_src, 0, 0, in intel_modeset_pipe_config()
4691 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { in intel_modeset_pipe_config()
4693 to_intel_encoder(connector_state->best_encoder); in intel_modeset_pipe_config()
4695 if (connector_state->crtc != &crtc->base) in intel_modeset_pipe_config()
4699 drm_dbg_kms(&i915->drm, in intel_modeset_pipe_config()
4701 encoder->base.base.id, encoder->base.name); in intel_modeset_pipe_config()
4702 return -EINVAL; in intel_modeset_pipe_config()
4709 if (encoder->compute_output_type) in intel_modeset_pipe_config()
4710 crtc_state->output_types |= in intel_modeset_pipe_config()
4711 BIT(encoder->compute_output_type(encoder, crtc_state, in intel_modeset_pipe_config()
4714 crtc_state->output_types |= BIT(encoder->type); in intel_modeset_pipe_config()
4719 crtc_state->port_clock = 0; in intel_modeset_pipe_config()
4720 crtc_state->pixel_multiplier = 1; in intel_modeset_pipe_config()
4723 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, in intel_modeset_pipe_config()
4726 /* Pass our mode to the connectors and the CRTC to give them a chance to in intel_modeset_pipe_config()
4728 * a chance to reject the mode entirely. in intel_modeset_pipe_config()
4730 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { in intel_modeset_pipe_config()
4732 to_intel_encoder(connector_state->best_encoder); in intel_modeset_pipe_config()
4734 if (connector_state->crtc != &crtc->base) in intel_modeset_pipe_config()
4737 ret = encoder->compute_config(encoder, crtc_state, in intel_modeset_pipe_config()
4739 if (ret == -EDEADLK) in intel_modeset_pipe_config()
4742 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", in intel_modeset_pipe_config()
4743 encoder->base.base.id, encoder->base.name, ret); in intel_modeset_pipe_config()
4749 * done afterwards in case the encoder adjusts the mode. */ in intel_modeset_pipe_config()
4750 if (!crtc_state->port_clock) in intel_modeset_pipe_config()
4751 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock in intel_modeset_pipe_config()
4752 * crtc_state->pixel_multiplier; in intel_modeset_pipe_config()
4755 if (ret == -EDEADLK) in intel_modeset_pipe_config()
4757 if (ret == -EAGAIN) { in intel_modeset_pipe_config()
4758 if (drm_WARN(&i915->drm, !retry, in intel_modeset_pipe_config()
4760 crtc->base.base.id, crtc->base.name)) in intel_modeset_pipe_config()
4761 return -EINVAL; in intel_modeset_pipe_config()
4763 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", in intel_modeset_pipe_config()
4764 crtc->base.base.id, crtc->base.name); in intel_modeset_pipe_config()
4769 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", in intel_modeset_pipe_config()
4770 crtc->base.base.id, crtc->base.name, ret); in intel_modeset_pipe_config()
4774 /* Dithering seems to not pass-through bits correctly when it should, so in intel_modeset_pipe_config()
4778 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && in intel_modeset_pipe_config()
4779 !crtc_state->dither_force_disable; in intel_modeset_pipe_config()
4780 drm_dbg_kms(&i915->drm, in intel_modeset_pipe_config()
4782 crtc->base.base.id, crtc->base.name, in intel_modeset_pipe_config()
4783 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); in intel_modeset_pipe_config()
4800 for_each_new_connector_in_state(&state->base, connector, in intel_modeset_pipe_config_late()
4803 to_intel_encoder(conn_state->best_encoder); in intel_modeset_pipe_config_late()
4806 if (conn_state->crtc != &crtc->base || in intel_modeset_pipe_config_late()
4807 !encoder->compute_config_late) in intel_modeset_pipe_config_late()
4810 ret = encoder->compute_config_late(encoder, crtc_state, in intel_modeset_pipe_config_late()
4829 diff = abs(clock1 - clock2); in intel_fuzzy_clock_check()
4841 return m_n->tu == m2_n2->tu && in intel_compare_link_m_n()
4842 m_n->data_m == m2_n2->data_m && in intel_compare_link_m_n()
4843 m_n->data_n == m2_n2->data_n && in intel_compare_link_m_n()
4844 m_n->link_m == m2_n2->link_m && in intel_compare_link_m_n()
4845 m_n->link_n == m2_n2->link_n; in intel_compare_link_m_n()
4878 drm_dbg_kms(&dev_priv->drm, in pipe_config_infoframe_mismatch()
4880 drm_dbg_kms(&dev_priv->drm, "expected:\n"); in pipe_config_infoframe_mismatch()
4881 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); in pipe_config_infoframe_mismatch()
4882 drm_dbg_kms(&dev_priv->drm, "found:\n"); in pipe_config_infoframe_mismatch()
4883 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); in pipe_config_infoframe_mismatch()
4885 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); in pipe_config_infoframe_mismatch()
4886 drm_err(&dev_priv->drm, "expected:\n"); in pipe_config_infoframe_mismatch()
4887 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); in pipe_config_infoframe_mismatch()
4888 drm_err(&dev_priv->drm, "found:\n"); in pipe_config_infoframe_mismatch()
4889 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); in pipe_config_infoframe_mismatch()
4903 drm_dbg_kms(&dev_priv->drm, in pipe_config_dp_vsc_sdp_mismatch()
4905 drm_dbg_kms(&dev_priv->drm, "expected:\n"); in pipe_config_dp_vsc_sdp_mismatch()
4906 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); in pipe_config_dp_vsc_sdp_mismatch()
4907 drm_dbg_kms(&dev_priv->drm, "found:\n"); in pipe_config_dp_vsc_sdp_mismatch()
4908 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); in pipe_config_dp_vsc_sdp_mismatch()
4910 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); in pipe_config_dp_vsc_sdp_mismatch()
4911 drm_err(&dev_priv->drm, "expected:\n"); in pipe_config_dp_vsc_sdp_mismatch()
4912 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); in pipe_config_dp_vsc_sdp_mismatch()
4913 drm_err(&dev_priv->drm, "found:\n"); in pipe_config_dp_vsc_sdp_mismatch()
4914 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); in pipe_config_dp_vsc_sdp_mismatch()
4924 for (i = len - 1; i >= 0; i--) { in memcmp_diff_len()
4944 drm_dbg_kms(&dev_priv->drm, in pipe_config_buffer_mismatch()
4954 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name); in pipe_config_buffer_mismatch()
4966 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in pipe_config_mismatch()
4975 drm_dbg_kms(&i915->drm, in pipe_config_mismatch()
4977 crtc->base.base.id, crtc->base.name, name, &vaf); in pipe_config_mismatch()
4979 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", in pipe_config_mismatch()
4980 crtc->base.base.id, crtc->base.name, name, &vaf); in pipe_config_mismatch()
4987 if (dev_priv->params.fastboot != -1) in fastboot_enabled()
4988 return dev_priv->params.fastboot; in fastboot_enabled()
5007 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); in intel_pipe_config_compare()
5008 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_pipe_config_compare()
5011 current_config->inherited && !pipe_config->inherited; in intel_pipe_config_compare()
5014 drm_dbg_kms(&dev_priv->drm, in intel_pipe_config_compare()
5020 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
5023 current_config->name, \ in intel_pipe_config_compare()
5024 pipe_config->name); \ in intel_pipe_config_compare()
5030 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ in intel_pipe_config_compare()
5033 current_config->name & (mask), \ in intel_pipe_config_compare()
5034 pipe_config->name & (mask)); \ in intel_pipe_config_compare()
5040 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
5043 current_config->name, \ in intel_pipe_config_compare()
5044 pipe_config->name); \ in intel_pipe_config_compare()
5050 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
5053 str_yes_no(current_config->name), \ in intel_pipe_config_compare()
5054 str_yes_no(pipe_config->name)); \ in intel_pipe_config_compare()
5065 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ in intel_pipe_config_compare()
5070 str_yes_no(current_config->name), \ in intel_pipe_config_compare()
5071 str_yes_no(pipe_config->name)); \ in intel_pipe_config_compare()
5077 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
5080 current_config->name, \ in intel_pipe_config_compare()
5081 pipe_config->name); \ in intel_pipe_config_compare()
5087 if (!intel_compare_link_m_n(¤t_config->name, \ in intel_pipe_config_compare()
5088 &pipe_config->name)) { \ in intel_pipe_config_compare()
5092 current_config->name.tu, \ in intel_pipe_config_compare()
5093 current_config->name.data_m, \ in intel_pipe_config_compare()
5094 current_config->name.data_n, \ in intel_pipe_config_compare()
5095 current_config->name.link_m, \ in intel_pipe_config_compare()
5096 current_config->name.link_n, \ in intel_pipe_config_compare()
5097 pipe_config->name.tu, \ in intel_pipe_config_compare()
5098 pipe_config->name.data_m, \ in intel_pipe_config_compare()
5099 pipe_config->name.data_n, \ in intel_pipe_config_compare()
5100 pipe_config->name.link_m, \ in intel_pipe_config_compare()
5101 pipe_config->name.link_n); \ in intel_pipe_config_compare()
5129 if ((current_config->name ^ pipe_config->name) & (mask)) { \ in intel_pipe_config_compare()
5133 current_config->name & (mask), \ in intel_pipe_config_compare()
5134 pipe_config->name & (mask)); \ in intel_pipe_config_compare()
5140 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ in intel_pipe_config_compare()
5141 &pipe_config->infoframes.name)) { \ in intel_pipe_config_compare()
5143 ¤t_config->infoframes.name, \ in intel_pipe_config_compare()
5144 &pipe_config->infoframes.name); \ in intel_pipe_config_compare()
5150 if (!current_config->has_psr && !pipe_config->has_psr && \ in intel_pipe_config_compare()
5151 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ in intel_pipe_config_compare()
5152 &pipe_config->infoframes.name)) { \ in intel_pipe_config_compare()
5154 ¤t_config->infoframes.name, \ in intel_pipe_config_compare()
5155 &pipe_config->infoframes.name); \ in intel_pipe_config_compare()
5161 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ in intel_pipe_config_compare()
5162 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ in intel_pipe_config_compare()
5163 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \ in intel_pipe_config_compare()
5165 current_config->name, \ in intel_pipe_config_compare()
5166 pipe_config->name, \ in intel_pipe_config_compare()
5173 if (current_config->gamma_mode == pipe_config->gamma_mode && \ in intel_pipe_config_compare()
5175 current_config->lut, pipe_config->lut, \ in intel_pipe_config_compare()
5202 ((current_config->quirks | pipe_config->quirks) & (quirk)) in intel_pipe_config_compare()
5218 if (!fastset || !pipe_config->seamless_m_n) in intel_pipe_config_compare()
5302 if (current_config->active_planes) { in intel_pipe_config_compare()
5312 if (dev_priv->display.dpll.mgr) { in intel_pipe_config_compare()
5355 if (!fastset || !pipe_config->seamless_m_n) { in intel_pipe_config_compare()
5363 if (current_config->has_psr || pipe_config->has_psr) in intel_pipe_config_compare()
5419 assert_plane(plane, plane_state->planar_slave || in intel_verify_planes()
5420 plane_state->uapi.visible); in intel_verify_planes()
5426 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_all_pipes()
5433 for_each_intel_crtc(&dev_priv->drm, crtc) { in intel_modeset_all_pipes()
5437 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in intel_modeset_all_pipes()
5441 if (!crtc_state->hw.active || in intel_modeset_all_pipes()
5445 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n", in intel_modeset_all_pipes()
5446 crtc->base.base.id, crtc->base.name, reason); in intel_modeset_all_pipes()
5448 crtc_state->uapi.mode_changed = true; in intel_modeset_all_pipes()
5449 crtc_state->update_pipe = false; in intel_modeset_all_pipes()
5451 ret = drm_atomic_add_affected_connectors(&state->base, in intel_modeset_all_pipes()
5452 &crtc->base); in intel_modeset_all_pipes()
5464 crtc_state->update_planes |= crtc_state->active_planes; in intel_modeset_all_pipes()
5465 crtc_state->async_flip_planes = 0; in intel_modeset_all_pipes()
5466 crtc_state->do_async_flip = false; in intel_modeset_all_pipes()
5473 * This implements the workaround described in the "notes" section of the mode
5489 if (!crtc_state->hw.active || in hsw_mode_set_planes_workaround()
5498 first_pipe = crtc->pipe; in hsw_mode_set_planes_workaround()
5507 for_each_intel_crtc(state->base.dev, crtc) { in hsw_mode_set_planes_workaround()
5508 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in hsw_mode_set_planes_workaround()
5512 crtc_state->hsw_workaround_pipe = INVALID_PIPE; in hsw_mode_set_planes_workaround()
5514 if (!crtc_state->hw.active || in hsw_mode_set_planes_workaround()
5522 enabled_pipe = crtc->pipe; in hsw_mode_set_planes_workaround()
5526 first_crtc_state->hsw_workaround_pipe = enabled_pipe; in hsw_mode_set_planes_workaround()
5528 other_crtc_state->hsw_workaround_pipe = first_pipe; in hsw_mode_set_planes_workaround()
5541 if (crtc_state->hw.active) in intel_calc_active_pipes()
5542 active_pipes |= BIT(crtc->pipe); in intel_calc_active_pipes()
5544 active_pipes &= ~BIT(crtc->pipe); in intel_calc_active_pipes()
5552 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_checks()
5554 state->modeset = true; in intel_modeset_checks()
5565 struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev); in intel_crtc_check_fastset()
5568 drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n"); in intel_crtc_check_fastset()
5573 new_crtc_state->uapi.mode_changed = false; in intel_crtc_check_fastset()
5575 new_crtc_state->update_pipe = true; in intel_crtc_check_fastset()
5582 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_crtc_add_planes_to_state()
5585 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { in intel_crtc_add_planes_to_state()
5588 if ((plane_ids_mask & BIT(plane->id)) == 0) in intel_crtc_add_planes_to_state()
5608 old_crtc_state->enabled_planes | in intel_atomic_add_affected_planes()
5609 new_crtc_state->enabled_planes); in intel_atomic_add_affected_planes()
5630 if (plane->pipe == crtc->pipe) in intel_crtc_add_bigjoiner_planes()
5631 plane_ids |= BIT(plane->id); in intel_crtc_add_bigjoiner_planes()
5639 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_bigjoiner_add_affected_planes()
5647 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, in intel_bigjoiner_add_affected_planes()
5648 crtc_state->bigjoiner_pipes) { in intel_bigjoiner_add_affected_planes()
5665 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_check_planes()
5683 drm_dbg_atomic(&dev_priv->drm, in intel_atomic_check_planes()
5685 plane->base.base.id, plane->base.name); in intel_atomic_check_planes()
5706 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); in intel_atomic_check_planes()
5707 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); in intel_atomic_check_planes()
5727 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_atomic_check_crtcs()
5732 drm_dbg_atomic(&i915->drm, in intel_atomic_check_crtcs()
5734 crtc->base.base.id, crtc->base.name); in intel_atomic_check_crtcs()
5750 if (new_crtc_state->hw.enable && in intel_cpu_transcoders_need_modeset()
5751 transcoders & BIT(new_crtc_state->cpu_transcoder) && in intel_cpu_transcoders_need_modeset()
5767 if (new_crtc_state->hw.enable && in intel_pipes_need_modeset()
5768 pipes & BIT(crtc->pipe) && in intel_pipes_need_modeset()
5779 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_atomic_check_bigjoiner()
5784 if (!master_crtc_state->bigjoiner_pipes) in intel_atomic_check_bigjoiner()
5788 if (drm_WARN_ON(&i915->drm, in intel_atomic_check_bigjoiner()
5789 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) in intel_atomic_check_bigjoiner()
5790 return -EINVAL; in intel_atomic_check_bigjoiner()
5792 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { in intel_atomic_check_bigjoiner()
5793 drm_dbg_kms(&i915->drm, in intel_atomic_check_bigjoiner()
5796 master_crtc->base.base.id, master_crtc->base.name, in intel_atomic_check_bigjoiner()
5797 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); in intel_atomic_check_bigjoiner()
5798 return -EINVAL; in intel_atomic_check_bigjoiner()
5801 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, in intel_atomic_check_bigjoiner()
5806 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); in intel_atomic_check_bigjoiner()
5811 if (slave_crtc_state->uapi.enable) { in intel_atomic_check_bigjoiner()
5812 drm_dbg_kms(&i915->drm, in intel_atomic_check_bigjoiner()
5815 slave_crtc->base.base.id, slave_crtc->base.name, in intel_atomic_check_bigjoiner()
5816 master_crtc->base.base.id, master_crtc->base.name); in intel_atomic_check_bigjoiner()
5817 return -EINVAL; in intel_atomic_check_bigjoiner()
5827 if (WARN_ON(drm_crtc_index(&master_crtc->base) > in intel_atomic_check_bigjoiner()
5828 drm_crtc_index(&slave_crtc->base))) in intel_atomic_check_bigjoiner()
5829 return -EINVAL; in intel_atomic_check_bigjoiner()
5831 drm_dbg_kms(&i915->drm, in intel_atomic_check_bigjoiner()
5833 slave_crtc->base.base.id, slave_crtc->base.name, in intel_atomic_check_bigjoiner()
5834 master_crtc->base.base.id, master_crtc->base.name); in intel_atomic_check_bigjoiner()
5836 slave_crtc_state->bigjoiner_pipes = in intel_atomic_check_bigjoiner()
5837 master_crtc_state->bigjoiner_pipes; in intel_atomic_check_bigjoiner()
5850 struct drm_i915_private *i915 = to_i915(state->base.dev); in kill_bigjoiner_slave()
5855 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, in kill_bigjoiner_slave()
5860 slave_crtc_state->bigjoiner_pipes = 0; in kill_bigjoiner_slave()
5865 master_crtc_state->bigjoiner_pipes = 0; in kill_bigjoiner_slave()
5889 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_async_flip_check_uapi()
5897 if (!new_crtc_state->uapi.async_flip) in intel_async_flip_check_uapi()
5900 if (!new_crtc_state->uapi.active) { in intel_async_flip_check_uapi()
5901 drm_dbg_kms(&i915->drm, in intel_async_flip_check_uapi()
5903 crtc->base.base.id, crtc->base.name); in intel_async_flip_check_uapi()
5904 return -EINVAL; in intel_async_flip_check_uapi()
5908 drm_dbg_kms(&i915->drm, in intel_async_flip_check_uapi()
5910 crtc->base.base.id, crtc->base.name); in intel_async_flip_check_uapi()
5911 return -EINVAL; in intel_async_flip_check_uapi()
5916 if (plane->pipe != crtc->pipe) in intel_async_flip_check_uapi()
5926 if (!plane->async_flip) { in intel_async_flip_check_uapi()
5927 drm_dbg_kms(&i915->drm, in intel_async_flip_check_uapi()
5929 plane->base.base.id, plane->base.name); in intel_async_flip_check_uapi()
5930 return -EINVAL; in intel_async_flip_check_uapi()
5933 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { in intel_async_flip_check_uapi()
5934 drm_dbg_kms(&i915->drm, in intel_async_flip_check_uapi()
5936 plane->base.base.id, plane->base.name); in intel_async_flip_check_uapi()
5937 return -EINVAL; in intel_async_flip_check_uapi()
5946 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_async_flip_check_hw()
5955 if (!new_crtc_state->uapi.async_flip) in intel_async_flip_check_hw()
5958 if (!new_crtc_state->hw.active) { in intel_async_flip_check_hw()
5959 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
5961 crtc->base.base.id, crtc->base.name); in intel_async_flip_check_hw()
5962 return -EINVAL; in intel_async_flip_check_hw()
5966 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
5968 crtc->base.base.id, crtc->base.name); in intel_async_flip_check_hw()
5969 return -EINVAL; in intel_async_flip_check_hw()
5972 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { in intel_async_flip_check_hw()
5973 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
5975 crtc->base.base.id, crtc->base.name); in intel_async_flip_check_hw()
5976 return -EINVAL; in intel_async_flip_check_hw()
5981 if (plane->pipe != crtc->pipe) in intel_async_flip_check_hw()
5989 if (drm_WARN_ON(&i915->drm, in intel_async_flip_check_hw()
5990 new_crtc_state->do_async_flip && !plane->async_flip)) in intel_async_flip_check_hw()
5991 return -EINVAL; in intel_async_flip_check_hw()
6001 if (!plane->async_flip) in intel_async_flip_check_hw()
6009 switch (new_plane_state->hw.fb->modifier) { in intel_async_flip_check_hw()
6018 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6020 plane->base.base.id, plane->base.name, in intel_async_flip_check_hw()
6021 new_plane_state->hw.fb->modifier, DISPLAY_VER(i915)); in intel_async_flip_check_hw()
6022 return -EINVAL; in intel_async_flip_check_hw()
6032 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6034 plane->base.base.id, plane->base.name, in intel_async_flip_check_hw()
6035 new_plane_state->hw.fb->modifier); in intel_async_flip_check_hw()
6036 return -EINVAL; in intel_async_flip_check_hw()
6039 if (new_plane_state->hw.fb->format->num_planes > 1) { in intel_async_flip_check_hw()
6040 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6042 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6043 return -EINVAL; in intel_async_flip_check_hw()
6046 if (old_plane_state->view.color_plane[0].mapping_stride != in intel_async_flip_check_hw()
6047 new_plane_state->view.color_plane[0].mapping_stride) { in intel_async_flip_check_hw()
6048 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6050 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6051 return -EINVAL; in intel_async_flip_check_hw()
6054 if (old_plane_state->hw.fb->modifier != in intel_async_flip_check_hw()
6055 new_plane_state->hw.fb->modifier) { in intel_async_flip_check_hw()
6056 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6058 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6059 return -EINVAL; in intel_async_flip_check_hw()
6062 if (old_plane_state->hw.fb->format != in intel_async_flip_check_hw()
6063 new_plane_state->hw.fb->format) { in intel_async_flip_check_hw()
6064 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6066 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6067 return -EINVAL; in intel_async_flip_check_hw()
6070 if (old_plane_state->hw.rotation != in intel_async_flip_check_hw()
6071 new_plane_state->hw.rotation) { in intel_async_flip_check_hw()
6072 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6074 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6075 return -EINVAL; in intel_async_flip_check_hw()
6078 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || in intel_async_flip_check_hw()
6079 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { in intel_async_flip_check_hw()
6080 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6081 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", in intel_async_flip_check_hw()
6082 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6083 return -EINVAL; in intel_async_flip_check_hw()
6086 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { in intel_async_flip_check_hw()
6087 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6089 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6090 return -EINVAL; in intel_async_flip_check_hw()
6093 if (old_plane_state->hw.pixel_blend_mode != in intel_async_flip_check_hw()
6094 new_plane_state->hw.pixel_blend_mode) { in intel_async_flip_check_hw()
6095 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6096 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", in intel_async_flip_check_hw()
6097 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6098 return -EINVAL; in intel_async_flip_check_hw()
6101 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { in intel_async_flip_check_hw()
6102 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6104 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6105 return -EINVAL; in intel_async_flip_check_hw()
6108 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { in intel_async_flip_check_hw()
6109 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6111 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6112 return -EINVAL; in intel_async_flip_check_hw()
6116 if (old_plane_state->decrypt != new_plane_state->decrypt) { in intel_async_flip_check_hw()
6117 drm_dbg_kms(&i915->drm, in intel_async_flip_check_hw()
6119 plane->base.base.id, plane->base.name); in intel_async_flip_check_hw()
6120 return -EINVAL; in intel_async_flip_check_hw()
6129 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_bigjoiner_add_affected_crtcs()
6137 affected_pipes |= crtc_state->bigjoiner_pipes; in intel_bigjoiner_add_affected_crtcs()
6139 modeset_pipes |= crtc_state->bigjoiner_pipes; in intel_bigjoiner_add_affected_crtcs()
6142 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { in intel_bigjoiner_add_affected_crtcs()
6143 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in intel_bigjoiner_add_affected_crtcs()
6148 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { in intel_bigjoiner_add_affected_crtcs()
6153 crtc_state->uapi.mode_changed = true; in intel_bigjoiner_add_affected_crtcs()
6155 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); in intel_bigjoiner_add_affected_crtcs()
6165 /* Kill old bigjoiner link, we may re-establish afterwards */ in intel_bigjoiner_add_affected_crtcs()
6175 * intel_atomic_check - validate state object
6195 if (!state->internal) in intel_atomic_check()
6196 new_crtc_state->inherited = false; in intel_atomic_check()
6198 if (new_crtc_state->inherited != old_crtc_state->inherited) in intel_atomic_check()
6199 new_crtc_state->uapi.mode_changed = true; in intel_atomic_check()
6201 if (new_crtc_state->uapi.scaling_filter != in intel_atomic_check()
6202 old_crtc_state->uapi.scaling_filter) in intel_atomic_check()
6203 new_crtc_state->uapi.mode_changed = true; in intel_atomic_check()
6208 ret = drm_atomic_helper_check_modeset(dev, &state->base); in intel_atomic_check()
6233 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); in intel_atomic_check()
6241 if (!new_crtc_state->hw.enable) in intel_atomic_check()
6258 if (new_crtc_state->hw.enable) { in intel_atomic_check()
6279 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) in intel_atomic_check()
6283 enum transcoder master = new_crtc_state->mst_master_transcoder; in intel_atomic_check()
6286 new_crtc_state->uapi.mode_changed = true; in intel_atomic_check()
6287 new_crtc_state->update_pipe = false; in intel_atomic_check()
6292 u8 trans = new_crtc_state->sync_mode_slaves_mask; in intel_atomic_check()
6294 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) in intel_atomic_check()
6295 trans |= BIT(new_crtc_state->master_transcoder); in intel_atomic_check()
6298 new_crtc_state->uapi.mode_changed = true; in intel_atomic_check()
6299 new_crtc_state->update_pipe = false; in intel_atomic_check()
6303 if (new_crtc_state->bigjoiner_pipes) { in intel_atomic_check()
6304 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { in intel_atomic_check()
6305 new_crtc_state->uapi.mode_changed = true; in intel_atomic_check()
6306 new_crtc_state->update_pipe = false; in intel_atomic_check()
6322 drm_dbg_kms(&dev_priv->drm, in intel_atomic_check()
6324 ret = -EINVAL; in intel_atomic_check()
6328 ret = drm_dp_mst_atomic_check(&state->base); in intel_atomic_check()
6382 drm_WARN_ON(&dev_priv->drm, in intel_atomic_check()
6398 if (ret == -EDEADLK) in intel_atomic_check()
6418 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); in intel_atomic_prepare_commit()
6433 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_arm_fifo_underrun()
6435 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) in intel_crtc_arm_fifo_underrun()
6436 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); in intel_crtc_arm_fifo_underrun()
6438 if (crtc_state->has_pch_encoder) { in intel_crtc_arm_fifo_underrun()
6449 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); in intel_pipe_fastset()
6450 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_pipe_fastset()
6454 * that in compute_mode_changes we check the native mode (not the pfit in intel_pipe_fastset()
6455 * mode) to see if we can flip rather than do a full mode set. In the in intel_pipe_fastset()
6464 if (new_crtc_state->pch_pfit.enabled) in intel_pipe_fastset()
6467 if (new_crtc_state->pch_pfit.enabled) in intel_pipe_fastset()
6469 else if (old_crtc_state->pch_pfit.enabled) in intel_pipe_fastset()
6485 if (new_crtc_state->seamless_m_n) in intel_pipe_fastset()
6486 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, in intel_pipe_fastset()
6487 &new_crtc_state->dp_m_n); in intel_pipe_fastset()
6493 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in commit_pipe_pre_planes()
6523 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in commit_pipe_post_planes()
6540 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_enable_crtc()
6550 dev_priv->display.funcs.display->crtc_enable(state, crtc); in intel_enable_crtc()
6555 /* vblanks work again, re-enable pipe CRC. */ in intel_enable_crtc()
6562 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_update_crtc()
6569 if (old_crtc_state->inherited || in intel_update_crtc()
6578 new_crtc_state->vrr.enable); in intel_update_crtc()
6582 if (new_crtc_state->preload_luts && in intel_update_crtc()
6598 drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF)); in intel_update_crtc()
6624 old_crtc_state->inherited) in intel_update_crtc()
6633 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_old_crtc_state_disables()
6641 dev_priv->display.funcs.display->crtc_disable(state, crtc); in intel_old_crtc_state_disables()
6642 crtc->active = false; in intel_old_crtc_state_disables()
6645 if (!new_crtc_state->hw.active) in intel_old_crtc_state_disables()
6661 if (!old_crtc_state->hw.active) in intel_commit_modeset_disables()
6674 if (!old_crtc_state->hw.active) in intel_commit_modeset_disables()
6689 handled |= BIT(crtc->pipe); in intel_commit_modeset_disables()
6696 (handled & BIT(crtc->pipe))) in intel_commit_modeset_disables()
6699 if (!old_crtc_state->hw.active) in intel_commit_modeset_disables()
6714 if (!new_crtc_state->hw.active) in intel_commit_modeset_enables()
6724 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in skl_commit_modeset_enables()
6732 enum pipe pipe = crtc->pipe; in skl_commit_modeset_enables()
6734 if (!new_crtc_state->hw.active) in skl_commit_modeset_enables()
6739 entries[pipe] = old_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
6758 enum pipe pipe = crtc->pipe; in skl_commit_modeset_enables()
6763 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
6767 entries[pipe] = new_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
6778 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
6779 &old_crtc_state->wm.skl.ddb) && in skl_commit_modeset_enables()
6792 enum pipe pipe = crtc->pipe; in skl_commit_modeset_enables()
6812 enum pipe pipe = crtc->pipe; in skl_commit_modeset_enables()
6826 enum pipe pipe = crtc->pipe; in skl_commit_modeset_enables()
6831 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
6834 entries[pipe] = new_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
6840 drm_WARN_ON(&dev_priv->drm, modeset_pipes); in skl_commit_modeset_enables()
6841 drm_WARN_ON(&dev_priv->drm, update_pipes); in skl_commit_modeset_enables()
6849 freed = llist_del_all(&dev_priv->display.atomic_helper.free_list); in intel_atomic_helper_free_state()
6851 drm_atomic_state_put(&state->base); in intel_atomic_helper_free_state()
6865 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); in intel_atomic_commit_fence_wait()
6870 prepare_to_wait(&intel_state->commit_ready.wait, in intel_atomic_commit_fence_wait()
6872 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, in intel_atomic_commit_fence_wait()
6877 if (i915_sw_fence_done(&intel_state->commit_ready) || in intel_atomic_commit_fence_wait()
6878 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) in intel_atomic_commit_fence_wait()
6883 finish_wait(&intel_state->commit_ready.wait, &wait_fence); in intel_atomic_commit_fence_wait()
6884 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, in intel_atomic_commit_fence_wait()
6893 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_atomic_cleanup_work()
6901 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); in intel_atomic_cleanup_work()
6902 drm_atomic_helper_commit_cleanup_done(&state->base); in intel_atomic_cleanup_work()
6903 drm_atomic_state_put(&state->base); in intel_atomic_cleanup_work()
6910 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_atomic_prepare_plane_clear_colors()
6916 struct drm_framebuffer *fb = plane_state->hw.fb; in intel_atomic_prepare_plane_clear_colors()
6932 * - 4 x 4 bytes per-channel value in intel_atomic_prepare_plane_clear_colors()
6934 * - 8 bytes native color value used by the display in intel_atomic_prepare_plane_clear_colors()
6936 * above per-channel values) in intel_atomic_prepare_plane_clear_colors()
6943 fb->offsets[cc_plane] + 16, in intel_atomic_prepare_plane_clear_colors()
6944 &plane_state->ccval, in intel_atomic_prepare_plane_clear_colors()
6945 sizeof(plane_state->ccval)); in intel_atomic_prepare_plane_clear_colors()
6947 drm_WARN_ON(&i915->drm, ret); in intel_atomic_prepare_plane_clear_colors()
6953 struct drm_device *dev = state->base.dev; in intel_atomic_commit_tail()
6963 drm_atomic_helper_wait_for_dependencies(&state->base); in intel_atomic_commit_tail()
6964 drm_dp_mst_atomic_wait_for_dependencies(&state->base); in intel_atomic_commit_tail()
6975 * 3. Due to some long delay PSR is re-entered in intel_atomic_commit_tail()
6976 * 4. DC5 entry -> DMC saves the already written new in intel_atomic_commit_tail()
6979 * 5. DC5 exit -> DMC restores a mixture of old and in intel_atomic_commit_tail()
6981 * 6. PSR exit -> hardware latches a mixture of old and in intel_atomic_commit_tail()
6982 * new register values -> corrupted frame, or worse in intel_atomic_commit_tail()
7001 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); in intel_atomic_commit_tail()
7006 /* FIXME: Eventually get rid of our crtc->config pointer */ in intel_atomic_commit_tail()
7008 crtc->config = new_crtc_state; in intel_atomic_commit_tail()
7018 if (state->modeset) { in intel_atomic_commit_tail()
7019 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); in intel_atomic_commit_tail()
7033 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { in intel_atomic_commit_tail()
7034 spin_lock_irq(&dev->event_lock); in intel_atomic_commit_tail()
7035 drm_crtc_send_vblank_event(&crtc->base, in intel_atomic_commit_tail()
7036 new_crtc_state->uapi.event); in intel_atomic_commit_tail()
7037 spin_unlock_irq(&dev->event_lock); in intel_atomic_commit_tail()
7039 new_crtc_state->uapi.event = NULL; in intel_atomic_commit_tail()
7049 if (new_crtc_state->do_async_flip) in intel_atomic_commit_tail()
7054 dev_priv->display.funcs.display->commit_modeset_enables(state); in intel_atomic_commit_tail()
7056 if (state->modeset) in intel_atomic_commit_tail()
7064 * - wrap the optimization/post_plane_update stuff into a per-crtc work. in intel_atomic_commit_tail()
7065 * - schedule that vblank worker _before_ calling hw_done in intel_atomic_commit_tail()
7066 * - at the start of commit_tail, cancel it _synchrously in intel_atomic_commit_tail()
7067 * - switch over to the vblank wait helper in the core after that since in intel_atomic_commit_tail()
7070 drm_atomic_helper_wait_for_flip_done(dev, &state->base); in intel_atomic_commit_tail()
7073 if (new_crtc_state->do_async_flip) in intel_atomic_commit_tail()
7079 * optimal watermarks on platforms that need two-step watermark in intel_atomic_commit_tail()
7088 * So re-enable underrun reporting after some planes get enabled. in intel_atomic_commit_tail()
7095 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); in intel_atomic_commit_tail()
7106 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); in intel_atomic_commit_tail()
7124 * FIXME get rid of this funny new->old swapping in intel_atomic_commit_tail()
7126 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); in intel_atomic_commit_tail()
7133 if (state->modeset) in intel_atomic_commit_tail()
7139 drm_atomic_helper_commit_hw_done(&state->base); in intel_atomic_commit_tail()
7141 if (state->modeset) { in intel_atomic_commit_tail()
7145 * so enable debugging for the next modeset - and hope we catch in intel_atomic_commit_tail()
7148 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); in intel_atomic_commit_tail()
7151 * Delay re-enabling DC states by 17 ms to avoid the off->on->off in intel_atomic_commit_tail()
7155 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); in intel_atomic_commit_tail()
7160 * are executed inline. For out-of-line asynchronous modesets/flips, in intel_atomic_commit_tail()
7165 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); in intel_atomic_commit_tail()
7166 queue_work(system_highpri_wq, &state->base.commit_work); in intel_atomic_commit_tail()
7190 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_atomic_commit_ready()
7192 &i915->display.atomic_helper; in intel_atomic_commit_ready()
7194 if (llist_add(&state->freed, &helper->free_list)) in intel_atomic_commit_ready()
7195 queue_work(i915->unordered_wq, &helper->free_work); in intel_atomic_commit_ready()
7211 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), in intel_atomic_track_fbs()
7212 to_intel_frontbuffer(new_plane_state->hw.fb), in intel_atomic_track_fbs()
7213 plane->frontbuffer_bit); in intel_atomic_track_fbs()
7223 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); in intel_atomic_commit()
7225 drm_atomic_state_get(&state->base); in intel_atomic_commit()
7226 i915_sw_fence_init(&state->commit_ready, in intel_atomic_commit()
7237 * Unset state->legacy_cursor_update before the call to in intel_atomic_commit()
7246 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { in intel_atomic_commit()
7252 if (new_crtc_state->wm.need_postvbl_update || in intel_atomic_commit()
7253 new_crtc_state->update_wm_post) in intel_atomic_commit()
7254 state->base.legacy_cursor_update = false; in intel_atomic_commit()
7259 drm_dbg_atomic(&dev_priv->drm, in intel_atomic_commit()
7261 i915_sw_fence_commit(&state->commit_ready); in intel_atomic_commit()
7262 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); in intel_atomic_commit()
7266 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); in intel_atomic_commit()
7268 ret = drm_atomic_helper_swap_state(&state->base, true); in intel_atomic_commit()
7277 i915_sw_fence_commit(&state->commit_ready); in intel_atomic_commit()
7282 drm_atomic_helper_cleanup_planes(dev, &state->base); in intel_atomic_commit()
7283 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); in intel_atomic_commit()
7289 drm_atomic_state_get(&state->base); in intel_atomic_commit()
7290 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); in intel_atomic_commit()
7292 i915_sw_fence_commit(&state->commit_ready); in intel_atomic_commit()
7293 if (nonblock && state->modeset) { in intel_atomic_commit()
7294 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work); in intel_atomic_commit()
7296 queue_work(dev_priv->display.wq.flip, &state->base.commit_work); in intel_atomic_commit()
7298 if (state->modeset) in intel_atomic_commit()
7299 flush_workqueue(dev_priv->display.wq.modeset); in intel_atomic_commit()
7307 * intel_plane_destroy - destroy a plane
7326 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); in intel_get_pipe_from_crtc_id_ioctl()
7328 return -ENOENT; in intel_get_pipe_from_crtc_id_ioctl()
7331 pipe_from_crtc_id->pipe = crtc->pipe; in intel_get_pipe_from_crtc_id_ioctl()
7338 struct drm_device *dev = encoder->base.dev; in intel_encoder_possible_clones()
7344 possible_clones |= drm_encoder_mask(&source_encoder->base); in intel_encoder_possible_clones()
7352 struct drm_device *dev = encoder->base.dev; in intel_encoder_possible_crtcs()
7356 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) in intel_encoder_possible_crtcs()
7357 possible_crtcs |= drm_crtc_mask(&crtc->base); in intel_encoder_possible_crtcs()
7392 if (!dev_priv->display.vbt.int_crt_support) in intel_ddi_crt_present()
7400 return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)->port_mask & BIT(port)), in assert_port_valid()
7461 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support) in intel_setup_outputs()
7467 * (no way to plug in a DP->HDMI dongle) the DDC pins for in intel_setup_outputs()
7474 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap in intel_setup_outputs()
7518 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); in intel_setup_outputs()
7521 drm_dbg_kms(&dev_priv->drm, in intel_setup_outputs()
7533 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); in intel_setup_outputs()
7540 drm_dbg_kms(&dev_priv->drm, in intel_setup_outputs()
7561 for_each_intel_encoder(&dev_priv->drm, encoder) { in intel_setup_outputs()
7562 encoder->base.possible_crtcs = in intel_setup_outputs()
7564 encoder->base.possible_clones = in intel_setup_outputs()
7570 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); in intel_setup_outputs()
7575 int max_dotclock = i915->max_dotclk_freq; in max_dotclock()
7585 const struct drm_display_mode *mode) in intel_mode_valid() argument
7593 * of DBLSCAN modes to the output's mode list when they detect in intel_mode_valid()
7594 * the scaling mode property on the connector. And they don't in intel_mode_valid()
7599 * reject modes with the DBLSCAN flag in encoder->compute_config(). in intel_mode_valid()
7600 * And we always reject DBLSCAN modes in connector->mode_valid() in intel_mode_valid()
7601 * as we never want such modes on the connector's mode list. in intel_mode_valid()
7604 if (mode->vscan > 1) in intel_mode_valid()
7607 if (mode->flags & DRM_MODE_FLAG_HSKEW) in intel_mode_valid()
7610 if (mode->flags & (DRM_MODE_FLAG_CSYNC | in intel_mode_valid()
7615 if (mode->flags & (DRM_MODE_FLAG_BCAST | in intel_mode_valid()
7624 if (mode->clock > max_dotclock(dev_priv)) in intel_mode_valid()
7651 if (mode->hdisplay > hdisplay_max || in intel_mode_valid()
7652 mode->hsync_start > htotal_max || in intel_mode_valid()
7653 mode->hsync_end > htotal_max || in intel_mode_valid()
7654 mode->htotal > htotal_max) in intel_mode_valid()
7657 if (mode->vdisplay > vdisplay_max || in intel_mode_valid()
7658 mode->vsync_start > vtotal_max || in intel_mode_valid()
7659 mode->vsync_end > vtotal_max || in intel_mode_valid()
7660 mode->vtotal > vtotal_max) in intel_mode_valid()
7664 if (mode->hdisplay < 64 || in intel_mode_valid()
7665 mode->htotal - mode->hdisplay < 32) in intel_mode_valid()
7668 if (mode->vtotal - mode->vdisplay < 5) in intel_mode_valid()
7671 if (mode->htotal - mode->hdisplay < 32) in intel_mode_valid()
7674 if (mode->vtotal - mode->vdisplay < 3) in intel_mode_valid()
7683 mode->hsync_start == mode->hdisplay) in intel_mode_valid()
7691 const struct drm_display_mode *mode, in intel_mode_valid_max_plane_size() argument
7716 if (mode->hdisplay > plane_width_max) in intel_mode_valid_max_plane_size()
7719 if (mode->vdisplay > plane_height_max) in intel_mode_valid_max_plane_size()
7766 * intel_init_display_hooks - initialize the display modesetting hooks
7772 dev_priv->display.funcs.display = &skl_display_funcs; in intel_init_display_hooks()
7774 dev_priv->display.funcs.display = &ddi_display_funcs; in intel_init_display_hooks()
7776 dev_priv->display.funcs.display = &pch_split_display_funcs; in intel_init_display_hooks()
7779 dev_priv->display.funcs.display = &vlv_display_funcs; in intel_init_display_hooks()
7781 dev_priv->display.funcs.display = &i9xx_display_funcs; in intel_init_display_hooks()
7794 return -ENOMEM; in intel_initial_commit()
7798 state->acquire_ctx = &ctx; in intel_initial_commit()
7799 to_intel_atomic_state(state)->internal = true; in intel_initial_commit()
7811 if (crtc_state->hw.active) { in intel_initial_commit()
7814 ret = drm_atomic_add_affected_planes(state, &crtc->base); in intel_initial_commit()
7824 crtc_state->uapi.color_mgmt_changed = true; in intel_initial_commit()
7827 crtc_state->uapi.encoder_mask) { in intel_initial_commit()
7828 if (encoder->initial_fastset_check && in intel_initial_commit()
7829 !encoder->initial_fastset_check(encoder, crtc_state)) { in intel_initial_commit()
7831 &crtc->base); in intel_initial_commit()
7842 if (ret == -EDEADLK) { in intel_initial_commit()
7871 drm_WARN_ON(&dev_priv->drm, in i830_enable_pipe()
7874 drm_dbg_kms(&dev_priv->drm, in i830_enable_pipe()
7881 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | in i830_enable_pipe()
7887 HACTIVE(640 - 1) | HTOTAL(800 - 1)); in i830_enable_pipe()
7889 HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); in i830_enable_pipe()
7891 HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); in i830_enable_pipe()
7893 VACTIVE(480 - 1) | VTOTAL(525 - 1)); in i830_enable_pipe()
7895 VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); in i830_enable_pipe()
7897 VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); in i830_enable_pipe()
7899 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); in i830_enable_pipe()
7905 * Apparently we need to have VGA mode enabled prior to changing in i830_enable_pipe()
7940 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", in i830_disable_pipe()
7943 drm_WARN_ON(&dev_priv->drm, in i830_disable_pipe()
7945 drm_WARN_ON(&dev_priv->drm, in i830_disable_pipe()
7947 drm_WARN_ON(&dev_priv->drm, in i830_disable_pipe()
7949 drm_WARN_ON(&dev_priv->drm, in i830_disable_pipe()
7951 drm_WARN_ON(&dev_priv->drm, in i830_disable_pipe()
7969 drm_connector_list_iter_begin(&i915->drm, &conn_iter); in intel_hpd_poll_fini()
7971 if (connector->modeset_retry_work.func) in intel_hpd_poll_fini()
7972 cancel_work_sync(&connector->modeset_retry_work); in intel_hpd_poll_fini()
7973 if (connector->hdcp.shim) { in intel_hpd_poll_fini()
7974 cancel_delayed_work_sync(&connector->hdcp.check_work); in intel_hpd_poll_fini()
7975 cancel_work_sync(&connector->hdcp.prop_work); in intel_hpd_poll_fini()