Lines Matching +full:needs +full:- +full:hpd
2 * Copyright © 2006-2007 Intel Corporation
102 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_crt_get_hw_state()
108 encoder->power_domain); in intel_crt_get_hw_state()
112 ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe); in intel_crt_get_hw_state()
114 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_crt_get_hw_state()
121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_crt_get_flags()
125 tmp = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_get_flags()
143 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); in intel_crt_get_config()
145 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); in intel_crt_get_config()
147 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_crt_get_config()
157 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | in hsw_crt_get_config()
161 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); in hsw_crt_get_config()
170 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_crt_set_dpms()
172 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crt_set_dpms()
173 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_crt_set_dpms()
181 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) in intel_crt_set_dpms()
183 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) in intel_crt_set_dpms()
190 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); in intel_crt_set_dpms()
192 adpa |= ADPA_PIPE_SEL(crtc->pipe); in intel_crt_set_dpms()
195 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); in intel_crt_set_dpms()
212 intel_de_write(dev_priv, crt->adpa_reg, adpa); in intel_crt_set_dpms()
243 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_disable_crt()
245 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder); in hsw_disable_crt()
255 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in hsw_post_disable_crt()
256 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_post_disable_crt()
274 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder); in hsw_post_disable_crt()
284 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_pre_pll_enable_crt()
286 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); in hsw_pre_pll_enable_crt()
296 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_pre_enable_crt()
297 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_pre_enable_crt()
298 enum pipe pipe = crtc->pipe; in hsw_pre_enable_crt()
300 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); in hsw_pre_enable_crt()
314 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_enable_crt()
315 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_enable_crt()
316 enum pipe pipe = crtc->pipe; in hsw_enable_crt()
318 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); in hsw_enable_crt()
348 struct drm_device *dev = connector->dev; in intel_crt_mode_valid()
350 int max_dotclk = dev_priv->max_dotclk_freq; in intel_crt_mode_valid()
353 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_crt_mode_valid()
356 if (mode->clock < 25000) in intel_crt_mode_valid()
371 if (mode->clock > max_clock) in intel_crt_mode_valid()
374 if (mode->clock > max_dotclk) in intel_crt_mode_valid()
379 ilk_get_lanes_required(mode->clock, 270000, 24) > 2) in intel_crt_mode_valid()
383 if (mode->hdisplay > 4096) in intel_crt_mode_valid()
394 &pipe_config->hw.adjusted_mode; in intel_crt_compute_config()
396 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_crt_compute_config()
397 return -EINVAL; in intel_crt_compute_config()
399 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; in intel_crt_compute_config()
400 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_crt_compute_config()
410 &pipe_config->hw.adjusted_mode; in pch_crt_compute_config()
412 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in pch_crt_compute_config()
413 return -EINVAL; in pch_crt_compute_config()
415 pipe_config->has_pch_encoder = true; in pch_crt_compute_config()
416 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in pch_crt_compute_config()
425 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_crt_compute_config()
427 &pipe_config->hw.adjusted_mode; in hsw_crt_compute_config()
429 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in hsw_crt_compute_config()
430 return -EINVAL; in hsw_crt_compute_config()
433 if (adjusted_mode->crtc_hdisplay > 4096 || in hsw_crt_compute_config()
434 adjusted_mode->crtc_hblank_start > 4096) in hsw_crt_compute_config()
435 return -EINVAL; in hsw_crt_compute_config()
437 pipe_config->has_pch_encoder = true; in hsw_crt_compute_config()
438 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in hsw_crt_compute_config()
442 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { in hsw_crt_compute_config()
443 drm_dbg_kms(&dev_priv->drm, in hsw_crt_compute_config()
445 return -EINVAL; in hsw_crt_compute_config()
448 pipe_config->pipe_bpp = 24; in hsw_crt_compute_config()
452 pipe_config->port_clock = 135000 * 2; in hsw_crt_compute_config()
454 adjusted_mode->crtc_clock = lpt_iclkip(pipe_config); in hsw_crt_compute_config()
461 struct drm_device *dev = connector->dev; in ilk_crt_detect_hotplug()
468 if (crt->force_hotplug_required) { in ilk_crt_detect_hotplug()
472 crt->force_hotplug_required = false; in ilk_crt_detect_hotplug()
474 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
475 drm_dbg_kms(&dev_priv->drm, in ilk_crt_detect_hotplug()
482 intel_de_write(dev_priv, crt->adpa_reg, adpa); in ilk_crt_detect_hotplug()
485 crt->adpa_reg, in ilk_crt_detect_hotplug()
488 drm_dbg_kms(&dev_priv->drm, in ilk_crt_detect_hotplug()
492 intel_de_write(dev_priv, crt->adpa_reg, save_adpa); in ilk_crt_detect_hotplug()
493 intel_de_posting_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
498 adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
503 drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n", in ilk_crt_detect_hotplug()
511 struct drm_device *dev = connector->dev; in valleyview_crt_detect_hotplug()
520 * Doing a force trigger causes a hpd interrupt to get sent, which can in valleyview_crt_detect_hotplug()
522 * - We enable power wells and reset the ADPA in valleyview_crt_detect_hotplug()
523 * - output_poll_exec does force probe on VGA, triggering a hpd in valleyview_crt_detect_hotplug()
524 * - HPD handler waits for poll to unlock dev->mode_config.mutex in valleyview_crt_detect_hotplug()
525 * - output_poll_exec shuts off the ADPA, unlocks in valleyview_crt_detect_hotplug()
526 * dev->mode_config.mutex in valleyview_crt_detect_hotplug()
527 * - HPD handler runs, resets ADPA and brings us back to the start in valleyview_crt_detect_hotplug()
529 * Just disable HPD interrupts here to prevent this in valleyview_crt_detect_hotplug()
531 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); in valleyview_crt_detect_hotplug()
533 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
534 drm_dbg_kms(&dev_priv->drm, in valleyview_crt_detect_hotplug()
539 intel_de_write(dev_priv, crt->adpa_reg, adpa); in valleyview_crt_detect_hotplug()
541 if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg, in valleyview_crt_detect_hotplug()
543 drm_dbg_kms(&dev_priv->drm, in valleyview_crt_detect_hotplug()
545 intel_de_write(dev_priv, crt->adpa_reg, save_adpa); in valleyview_crt_detect_hotplug()
549 adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
555 drm_dbg_kms(&dev_priv->drm, in valleyview_crt_detect_hotplug()
559 intel_hpd_enable(dev_priv, crt->base.hpd_pin); in valleyview_crt_detect_hotplug()
566 struct drm_device *dev = connector->dev; in intel_crt_detect_hotplug()
596 drm_dbg_kms(&dev_priv->drm, in intel_crt_detect_hotplug()
620 drm_dbg_kms(connector->dev, in intel_crt_get_edid()
621 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); in intel_crt_get_edid()
651 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); in intel_crt_detect_ddc()
656 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin); in intel_crt_detect_ddc()
661 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; in intel_crt_detect_ddc()
664 * This may be a DVI-I connector with a shared DDC in intel_crt_detect_ddc()
669 drm_dbg_kms(&dev_priv->drm, in intel_crt_detect_ddc()
673 drm_dbg_kms(&dev_priv->drm, in intel_crt_detect_ddc()
677 drm_dbg_kms(&dev_priv->drm, in intel_crt_detect_ddc()
689 struct drm_device *dev = crt->base.base.dev; in intel_crt_load_detect()
701 drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n"); in intel_crt_load_detect()
745 VBLANK_START(vblank_start - 1) | in intel_crt_load_detect()
746 VBLANK_END(vblank_end - 1)); in intel_crt_load_detect()
750 if (vblank_start - vactive >= vtotal - vblank_end) in intel_crt_load_detect()
797 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); in intel_spurious_crt_detect_dmi_callback()
812 .ident = "Intel DZ77BH-55K",
815 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
826 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_crt_detect()
828 struct intel_encoder *intel_encoder = &crt->base; in intel_crt_detect()
833 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n", in intel_crt_detect()
834 connector->base.id, connector->name, in intel_crt_detect()
840 if (dev_priv->params.load_detect_test) { in intel_crt_detect()
842 intel_encoder->power_domain); in intel_crt_detect()
851 intel_encoder->power_domain); in intel_crt_detect()
854 /* We can not rely on the HPD pin always being correctly wired in intel_crt_detect()
859 drm_dbg_kms(&dev_priv->drm, in intel_crt_detect()
864 drm_dbg_kms(&dev_priv->drm, in intel_crt_detect()
873 /* Load detection is broken on HPD capable machines. Whoever wants a in intel_crt_detect()
875 * to have the right resistors for HP detection) needs to fix this up. in intel_crt_detect()
884 status = connector->status; in intel_crt_detect()
888 /* for pre-945g platforms use load detect */ in intel_crt_detect()
899 to_intel_crtc(connector->state->crtc)->pipe); in intel_crt_detect()
900 else if (dev_priv->params.load_detect_test) in intel_crt_detect()
908 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); in intel_crt_detect()
912 * dropped to avoid a new detect cycle triggered by HPD polling. in intel_crt_detect()
921 struct drm_device *dev = connector->dev; in intel_crt_get_modes()
924 struct intel_encoder *intel_encoder = &crt->base; in intel_crt_get_modes()
930 intel_encoder->power_domain); in intel_crt_get_modes()
932 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin); in intel_crt_get_modes()
937 /* Try to probe digital port for output in DVI-I -> VGA mode. */ in intel_crt_get_modes()
942 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); in intel_crt_get_modes()
949 struct drm_i915_private *dev_priv = to_i915(encoder->dev); in intel_crt_reset()
955 adpa = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_reset()
958 intel_de_write(dev_priv, crt->adpa_reg, adpa); in intel_crt_reset()
959 intel_de_posting_read(dev_priv, crt->adpa_reg); in intel_crt_reset()
961 drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa); in intel_crt_reset()
962 crt->force_hotplug_required = true; in intel_crt_reset()
1033 connector = &intel_connector->base; in intel_crt_init()
1034 crt->connector = intel_connector; in intel_crt_init()
1035 drm_connector_init(&dev_priv->drm, &intel_connector->base, in intel_crt_init()
1038 drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, in intel_crt_init()
1041 intel_connector_attach_encoder(intel_connector, &crt->base); in intel_crt_init()
1043 crt->base.type = INTEL_OUTPUT_ANALOG; in intel_crt_init()
1044 crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI); in intel_crt_init()
1046 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1048 crt->base.pipe_mask = ~0; in intel_crt_init()
1051 connector->interlace_allowed = true; in intel_crt_init()
1053 crt->adpa_reg = adpa_reg; in intel_crt_init()
1055 crt->base.power_domain = POWER_DOMAIN_PORT_CRT; in intel_crt_init()
1059 crt->base.hpd_pin = HPD_CRT; in intel_crt_init()
1060 crt->base.hotplug = intel_encoder_hotplug; in intel_crt_init()
1061 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; in intel_crt_init()
1063 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; in intel_crt_init()
1069 crt->base.port = PORT_E; in intel_crt_init()
1070 crt->base.get_config = hsw_crt_get_config; in intel_crt_init()
1071 crt->base.get_hw_state = intel_ddi_get_hw_state; in intel_crt_init()
1072 crt->base.compute_config = hsw_crt_compute_config; in intel_crt_init()
1073 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; in intel_crt_init()
1074 crt->base.pre_enable = hsw_pre_enable_crt; in intel_crt_init()
1075 crt->base.enable = hsw_enable_crt; in intel_crt_init()
1076 crt->base.disable = hsw_disable_crt; in intel_crt_init()
1077 crt->base.post_disable = hsw_post_disable_crt; in intel_crt_init()
1078 crt->base.enable_clock = hsw_ddi_enable_clock; in intel_crt_init()
1079 crt->base.disable_clock = hsw_ddi_disable_clock; in intel_crt_init()
1080 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled; in intel_crt_init()
1082 intel_ddi_buf_trans_init(&crt->base); in intel_crt_init()
1085 crt->base.compute_config = pch_crt_compute_config; in intel_crt_init()
1086 crt->base.disable = pch_disable_crt; in intel_crt_init()
1087 crt->base.post_disable = pch_post_disable_crt; in intel_crt_init()
1089 crt->base.compute_config = intel_crt_compute_config; in intel_crt_init()
1090 crt->base.disable = intel_disable_crt; in intel_crt_init()
1092 crt->base.port = PORT_NONE; in intel_crt_init()
1093 crt->base.get_config = intel_crt_get_config; in intel_crt_init()
1094 crt->base.get_hw_state = intel_crt_get_hw_state; in intel_crt_init()
1095 crt->base.enable = intel_enable_crt; in intel_crt_init()
1097 intel_connector->get_hw_state = intel_connector_get_hw_state; in intel_crt_init()
1110 dev_priv->display.fdi.rx_config = intel_de_read(dev_priv, in intel_crt_init()
1114 intel_crt_reset(&crt->base.base); in intel_crt_init()