Lines Matching refs:display
84 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
91 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
97 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
103 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
553 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
1031 dev_priv->display.cdclk.hw.vco = vco; in skl_dpll0_enable()
1045 dev_priv->display.cdclk.hw.vco = 0; in skl_dpll0_disable()
1054 cdclk != dev_priv->display.cdclk.hw.bypass); in skl_cdclk_freq_sel()
1103 if (dev_priv->display.cdclk.hw.vco != 0 && in skl_set_cdclk()
1104 dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1109 if (dev_priv->display.cdclk.hw.vco != vco) { in skl_set_cdclk()
1121 if (dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1156 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1159 if (dev_priv->display.cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1160 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in skl_sanitize_cdclk()
1171 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); in skl_sanitize_cdclk()
1180 dev_priv->display.cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1182 dev_priv->display.cdclk.hw.vco = -1; in skl_sanitize_cdclk()
1191 if (dev_priv->display.cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1192 dev_priv->display.cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1199 dev_priv->display.cdclk.hw.vco); in skl_cdclk_init_hw()
1203 cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_init_hw()
1216 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_uninit_hw()
1386 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk()
1390 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk()
1396 min_cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk()
1402 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk_pll_vco()
1405 if (cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1409 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1411 return dev_priv->display.cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1414 cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1600 dev_priv->display.cdclk.hw.vco = 0; in bxt_de_pll_disable()
1605 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in bxt_de_pll_enable()
1617 dev_priv->display.cdclk.hw.vco = vco; in bxt_de_pll_enable()
1629 dev_priv->display.cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1634 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in icl_cdclk_pll_enable()
1647 dev_priv->display.cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1652 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1671 dev_priv->display.cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1701 cdclk != dev_priv->display.cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1718 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in cdclk_squash_waveform()
1721 if (cdclk == dev_priv->display.cdclk.hw.bypass) in cdclk_squash_waveform()
1725 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in cdclk_squash_waveform()
1730 cdclk, dev_priv->display.cdclk.hw.ref); in cdclk_squash_waveform()
1737 if (i915->display.cdclk.hw.vco != 0 && in icl_cdclk_pll_update()
1738 i915->display.cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1741 if (i915->display.cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1747 if (i915->display.cdclk.hw.vco != 0 && in bxt_cdclk_pll_update()
1748 i915->display.cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1751 if (i915->display.cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1834 i915->display.cdclk.max_cdclk_freq); in cdclk_compute_crawl_and_squash_midpoint()
1844 dev_priv->display.cdclk.hw.vco > 0 && in pll_enable_wa_needed()
1858 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
1859 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { in _bxt_set_cdclk()
1860 if (dev_priv->display.cdclk.hw.vco != vco) in _bxt_set_cdclk()
1935 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, in bxt_set_cdclk()
1977 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
1986 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
1988 if (dev_priv->display.cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
1989 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_sanitize_cdclk()
2007 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); in bxt_sanitize_cdclk()
2008 if (cdclk != dev_priv->display.cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2013 if (vco != dev_priv->display.cdclk.hw.vco) in bxt_sanitize_cdclk()
2020 clock = dev_priv->display.cdclk.hw.vco / 2; in bxt_sanitize_cdclk()
2022 clock = dev_priv->display.cdclk.hw.cdclk; in bxt_sanitize_cdclk()
2025 dev_priv->display.cdclk.hw.vco); in bxt_sanitize_cdclk()
2032 dev_priv->display.cdclk.hw.cdclk >= 500000) in bxt_sanitize_cdclk()
2043 dev_priv->display.cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
2046 dev_priv->display.cdclk.hw.vco = -1; in bxt_sanitize_cdclk()
2055 if (dev_priv->display.cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
2056 dev_priv->display.cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2059 cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_init_hw()
2076 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_uninit_hw()
2305 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) in intel_set_cdclk()
2308 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2326 mutex_lock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2331 &dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2341 mutex_unlock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2352 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), in intel_set_cdclk()
2354 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); in intel_set_cdclk()
2638 dev_priv->display.cdclk.max_cdclk_freq)); in intel_crtc_compute_min_cdclk()
2691 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2694 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2958 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); in intel_atomic_get_cdclk_state()
3008 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, in intel_cdclk_init()
3133 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
3159 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3160 dev_priv->display.cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
3162 dev_priv->display.cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
3164 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3165 dev_priv->display.cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
3167 dev_priv->display.cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
3169 dev_priv->display.cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
3171 dev_priv->display.cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
3193 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
3202 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3204 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3206 dev_priv->display.cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
3208 dev_priv->display.cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
3210 dev_priv->display.cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
3212 dev_priv->display.cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
3215 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; in intel_update_max_cdclk()
3221 dev_priv->display.cdclk.max_cdclk_freq); in intel_update_max_cdclk()
3235 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); in intel_update_cdclk()
3245 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3396 seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); in i915_cdclk_info_show()
3397 seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); in i915_cdclk_info_show()
3563 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; in intel_init_cdclk_hooks()
3564 dev_priv->display.cdclk.table = mtl_cdclk_table; in intel_init_cdclk_hooks()
3566 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3567 dev_priv->display.cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3571 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3572 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3574 dev_priv->display.cdclk.table = rplu_cdclk_table; in intel_init_cdclk_hooks()
3575 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3577 dev_priv->display.cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3578 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3581 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3582 dev_priv->display.cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3584 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3585 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3587 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3588 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3590 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3591 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3593 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3595 dev_priv->display.cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3597 dev_priv->display.cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3599 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3601 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3603 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3605 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3607 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3609 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3611 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3613 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3615 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3617 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3619 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3621 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3623 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3625 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3627 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3629 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3631 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3633 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3635 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3637 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3639 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3642 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, in intel_init_cdclk_hooks()
3644 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()