Lines Matching refs:dev_priv
81 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, in intel_cdclk_get_cdclk() argument
84 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
87 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv, in intel_cdclk_set_cdclk() argument
91 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
94 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv, in intel_cdclk_modeset_calc_cdclk() argument
97 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
100 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, in intel_cdclk_calc_voltage_level() argument
103 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
106 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_133mhz_get_cdclk() argument
112 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_200mhz_get_cdclk() argument
118 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_266mhz_get_cdclk() argument
124 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_333mhz_get_cdclk() argument
130 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_400mhz_get_cdclk() argument
136 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_450mhz_get_cdclk() argument
142 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, in i85x_get_cdclk() argument
145 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i85x_get_cdclk()
184 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, in i915gm_get_cdclk() argument
187 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i915gm_get_cdclk()
208 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, in i945gm_get_cdclk() argument
211 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i945gm_get_cdclk()
232 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) in intel_hpll_vco() argument
276 if (IS_GM45(dev_priv)) in intel_hpll_vco()
278 else if (IS_G45(dev_priv)) in intel_hpll_vco()
280 else if (IS_I965GM(dev_priv)) in intel_hpll_vco()
282 else if (IS_PINEVIEW(dev_priv)) in intel_hpll_vco()
284 else if (IS_G33(dev_priv)) in intel_hpll_vco()
289 tmp = intel_de_read(dev_priv, in intel_hpll_vco()
290 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); in intel_hpll_vco()
294 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
297 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
302 static void g33_get_cdclk(struct drm_i915_private *dev_priv, in g33_get_cdclk() argument
305 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in g33_get_cdclk()
314 cdclk_config->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
345 drm_err(&dev_priv->drm, in g33_get_cdclk()
351 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, in pnv_get_cdclk() argument
354 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in pnv_get_cdclk()
373 drm_err(&dev_priv->drm, in pnv_get_cdclk()
385 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, in i965gm_get_cdclk() argument
388 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i965gm_get_cdclk()
396 cdclk_config->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
424 drm_err(&dev_priv->drm, in i965gm_get_cdclk()
430 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, in gm45_get_cdclk() argument
433 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in gm45_get_cdclk()
437 cdclk_config->vco = intel_hpll_vco(dev_priv); in gm45_get_cdclk()
453 drm_err(&dev_priv->drm, in gm45_get_cdclk()
461 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, in hsw_get_cdclk() argument
464 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); in hsw_get_cdclk()
469 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) in hsw_get_cdclk()
473 else if (IS_HASWELL_ULT(dev_priv)) in hsw_get_cdclk()
479 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) in vlv_calc_cdclk() argument
481 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? in vlv_calc_cdclk()
489 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) in vlv_calc_cdclk()
499 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) in vlv_calc_voltage_level() argument
501 if (IS_VALLEYVIEW(dev_priv)) { in vlv_calc_voltage_level()
514 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
518 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, in vlv_get_cdclk() argument
523 vlv_iosf_sb_get(dev_priv, in vlv_get_cdclk()
526 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
527 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
531 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_get_cdclk()
533 vlv_iosf_sb_put(dev_priv, in vlv_get_cdclk()
536 if (IS_VALLEYVIEW(dev_priv)) in vlv_get_cdclk()
544 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) in vlv_program_pfi_credits() argument
548 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
553 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
555 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
567 intel_de_write(dev_priv, GCI_CONTROL, in vlv_program_pfi_credits()
570 intel_de_write(dev_priv, GCI_CONTROL, in vlv_program_pfi_credits()
577 drm_WARN_ON(&dev_priv->drm, in vlv_program_pfi_credits()
578 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); in vlv_program_pfi_credits()
581 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, in vlv_set_cdclk() argument
607 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); in vlv_set_cdclk()
609 vlv_iosf_sb_get(dev_priv, in vlv_set_cdclk()
614 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_set_cdclk()
617 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); in vlv_set_cdclk()
618 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in vlv_set_cdclk()
621 drm_err(&dev_priv->drm, in vlv_set_cdclk()
628 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, in vlv_set_cdclk()
632 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); in vlv_set_cdclk()
635 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); in vlv_set_cdclk()
637 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & in vlv_set_cdclk()
640 drm_err(&dev_priv->drm, in vlv_set_cdclk()
645 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); in vlv_set_cdclk()
656 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); in vlv_set_cdclk()
658 vlv_iosf_sb_put(dev_priv, in vlv_set_cdclk()
663 intel_update_cdclk(dev_priv); in vlv_set_cdclk()
665 vlv_program_pfi_credits(dev_priv); in vlv_set_cdclk()
667 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); in vlv_set_cdclk()
670 static void chv_set_cdclk(struct drm_i915_private *dev_priv, in chv_set_cdclk() argument
695 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); in chv_set_cdclk()
697 vlv_punit_get(dev_priv); in chv_set_cdclk()
698 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_cdclk()
701 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); in chv_set_cdclk()
702 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in chv_set_cdclk()
705 drm_err(&dev_priv->drm, in chv_set_cdclk()
709 vlv_punit_put(dev_priv); in chv_set_cdclk()
711 intel_update_cdclk(dev_priv); in chv_set_cdclk()
713 vlv_program_pfi_credits(dev_priv); in chv_set_cdclk()
715 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); in chv_set_cdclk()
745 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, in bdw_get_cdclk() argument
748 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); in bdw_get_cdclk()
753 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) in bdw_get_cdclk()
789 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, in bdw_set_cdclk() argument
796 if (drm_WARN(&dev_priv->drm, in bdw_set_cdclk()
797 (intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
805 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); in bdw_set_cdclk()
807 drm_err(&dev_priv->drm, in bdw_set_cdclk()
812 intel_de_rmw(dev_priv, LCPLL_CTL, in bdw_set_cdclk()
819 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
821 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); in bdw_set_cdclk()
823 intel_de_rmw(dev_priv, LCPLL_CTL, in bdw_set_cdclk()
826 intel_de_rmw(dev_priv, LCPLL_CTL, in bdw_set_cdclk()
829 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
831 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); in bdw_set_cdclk()
833 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, in bdw_set_cdclk()
836 intel_de_write(dev_priv, CDCLK_FREQ, in bdw_set_cdclk()
839 intel_update_cdclk(dev_priv); in bdw_set_cdclk()
877 static void skl_dpll0_update(struct drm_i915_private *dev_priv, in skl_dpll0_update() argument
885 val = intel_de_read(dev_priv, LCPLL1_CTL); in skl_dpll0_update()
889 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) in skl_dpll0_update()
892 val = intel_de_read(dev_priv, DPLL_CTRL1); in skl_dpll0_update()
894 if (drm_WARN_ON(&dev_priv->drm, in skl_dpll0_update()
918 static void skl_get_cdclk(struct drm_i915_private *dev_priv, in skl_get_cdclk() argument
923 skl_dpll0_update(dev_priv, cdclk_config); in skl_get_cdclk()
930 cdctl = intel_de_read(dev_priv, CDCLK_CTL); in skl_get_cdclk()
985 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, in skl_set_preferred_cdclk_vco() argument
988 bool changed = dev_priv->skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
990 dev_priv->skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
993 intel_update_max_cdclk(dev_priv); in skl_set_preferred_cdclk_vco()
996 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) in skl_dpll0_link_rate() argument
998 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in skl_dpll0_link_rate()
1015 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) in skl_dpll0_enable() argument
1017 intel_de_rmw(dev_priv, DPLL_CTRL1, in skl_dpll0_enable()
1022 skl_dpll0_link_rate(dev_priv, vco)); in skl_dpll0_enable()
1023 intel_de_posting_read(dev_priv, DPLL_CTRL1); in skl_dpll0_enable()
1025 intel_de_rmw(dev_priv, LCPLL1_CTL, in skl_dpll0_enable()
1028 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) in skl_dpll0_enable()
1029 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); in skl_dpll0_enable()
1031 dev_priv->display.cdclk.hw.vco = vco; in skl_dpll0_enable()
1034 skl_set_preferred_cdclk_vco(dev_priv, vco); in skl_dpll0_enable()
1037 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) in skl_dpll0_disable() argument
1039 intel_de_rmw(dev_priv, LCPLL1_CTL, in skl_dpll0_disable()
1042 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) in skl_dpll0_disable()
1043 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); in skl_dpll0_disable()
1045 dev_priv->display.cdclk.hw.vco = 0; in skl_dpll0_disable()
1048 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, in skl_cdclk_freq_sel() argument
1053 drm_WARN_ON(&dev_priv->drm, in skl_cdclk_freq_sel()
1054 cdclk != dev_priv->display.cdclk.hw.bypass); in skl_cdclk_freq_sel()
1055 drm_WARN_ON(&dev_priv->drm, vco != 0); in skl_cdclk_freq_sel()
1071 static void skl_set_cdclk(struct drm_i915_private *dev_priv, in skl_set_cdclk() argument
1088 drm_WARN_ON_ONCE(&dev_priv->drm, in skl_set_cdclk()
1089 IS_SKYLAKE(dev_priv) && vco == 8640000); in skl_set_cdclk()
1091 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1096 drm_err(&dev_priv->drm, in skl_set_cdclk()
1101 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); in skl_set_cdclk()
1103 if (dev_priv->display.cdclk.hw.vco != 0 && in skl_set_cdclk()
1104 dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1105 skl_dpll0_disable(dev_priv); in skl_set_cdclk()
1107 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
1109 if (dev_priv->display.cdclk.hw.vco != vco) { in skl_set_cdclk()
1113 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1118 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1119 intel_de_posting_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
1121 if (dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1122 skl_dpll0_enable(dev_priv, vco); in skl_set_cdclk()
1126 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1129 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1133 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1134 intel_de_posting_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
1137 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1140 intel_update_cdclk(dev_priv); in skl_set_cdclk()
1143 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) in skl_sanitize_cdclk() argument
1152 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) in skl_sanitize_cdclk()
1155 intel_update_cdclk(dev_priv); in skl_sanitize_cdclk()
1156 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1159 if (dev_priv->display.cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1160 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in skl_sanitize_cdclk()
1169 cdctl = intel_de_read(dev_priv, CDCLK_CTL); in skl_sanitize_cdclk()
1171 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); in skl_sanitize_cdclk()
1177 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1180 dev_priv->display.cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1182 dev_priv->display.cdclk.hw.vco = -1; in skl_sanitize_cdclk()
1185 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) in skl_cdclk_init_hw() argument
1189 skl_sanitize_cdclk(dev_priv); in skl_cdclk_init_hw()
1191 if (dev_priv->display.cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1192 dev_priv->display.cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1197 if (dev_priv->skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1198 skl_set_preferred_cdclk_vco(dev_priv, in skl_cdclk_init_hw()
1199 dev_priv->display.cdclk.hw.vco); in skl_cdclk_init_hw()
1203 cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_init_hw()
1205 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; in skl_cdclk_init_hw()
1211 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in skl_cdclk_init_hw()
1214 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) in skl_cdclk_uninit_hw() argument
1216 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_uninit_hw()
1222 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in skl_cdclk_uninit_hw()
1384 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) in bxt_calc_cdclk() argument
1386 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk()
1390 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk()
1394 drm_WARN(&dev_priv->drm, 1, in bxt_calc_cdclk()
1396 min_cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk()
1400 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) in bxt_calc_cdclk_pll_vco() argument
1402 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk_pll_vco()
1405 if (cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1409 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1411 return dev_priv->display.cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1413 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1414 cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1469 static void icl_readout_refclk(struct drm_i915_private *dev_priv, in icl_readout_refclk() argument
1472 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; in icl_readout_refclk()
1490 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, in bxt_de_pll_readout() argument
1495 if (IS_DG2(dev_priv)) in bxt_de_pll_readout()
1497 else if (DISPLAY_VER(dev_priv) >= 11) in bxt_de_pll_readout()
1498 icl_readout_refclk(dev_priv, cdclk_config); in bxt_de_pll_readout()
1502 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); in bxt_de_pll_readout()
1517 if (DISPLAY_VER(dev_priv) >= 11) in bxt_de_pll_readout()
1520 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; in bxt_de_pll_readout()
1525 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, in bxt_get_cdclk() argument
1532 bxt_de_pll_readout(dev_priv, cdclk_config); in bxt_get_cdclk()
1534 if (DISPLAY_VER(dev_priv) >= 12) in bxt_get_cdclk()
1536 else if (DISPLAY_VER(dev_priv) >= 11) in bxt_get_cdclk()
1546 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; in bxt_get_cdclk()
1566 if (HAS_CDCLK_SQUASH(dev_priv)) in bxt_get_cdclk()
1567 squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL); in bxt_get_cdclk()
1588 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); in bxt_get_cdclk()
1591 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) in bxt_de_pll_disable() argument
1593 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); in bxt_de_pll_disable()
1596 if (intel_de_wait_for_clear(dev_priv, in bxt_de_pll_disable()
1598 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); in bxt_de_pll_disable()
1600 dev_priv->display.cdclk.hw.vco = 0; in bxt_de_pll_disable()
1603 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) in bxt_de_pll_enable() argument
1605 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in bxt_de_pll_enable()
1607 intel_de_rmw(dev_priv, BXT_DE_PLL_CTL, in bxt_de_pll_enable()
1610 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); in bxt_de_pll_enable()
1613 if (intel_de_wait_for_set(dev_priv, in bxt_de_pll_enable()
1615 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); in bxt_de_pll_enable()
1617 dev_priv->display.cdclk.hw.vco = vco; in bxt_de_pll_enable()
1620 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv) in icl_cdclk_pll_disable() argument
1622 intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE, in icl_cdclk_pll_disable()
1626 if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) in icl_cdclk_pll_disable()
1627 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); in icl_cdclk_pll_disable()
1629 dev_priv->display.cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1632 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) in icl_cdclk_pll_enable() argument
1634 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in icl_cdclk_pll_enable()
1638 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in icl_cdclk_pll_enable()
1641 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in icl_cdclk_pll_enable()
1644 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) in icl_cdclk_pll_enable()
1645 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); in icl_cdclk_pll_enable()
1647 dev_priv->display.cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1650 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) in adlp_cdclk_pll_crawl() argument
1652 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1657 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1661 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1664 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, in adlp_cdclk_pll_crawl()
1666 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n"); in adlp_cdclk_pll_crawl()
1669 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1671 dev_priv->display.cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1674 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) in bxt_cdclk_cd2x_pipe() argument
1676 if (DISPLAY_VER(dev_priv) >= 12) { in bxt_cdclk_cd2x_pipe()
1681 } else if (DISPLAY_VER(dev_priv) >= 11) { in bxt_cdclk_cd2x_pipe()
1694 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, in bxt_cdclk_cd2x_div_sel() argument
1700 drm_WARN_ON(&dev_priv->drm, in bxt_cdclk_cd2x_div_sel()
1701 cdclk != dev_priv->display.cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1702 drm_WARN_ON(&dev_priv->drm, vco != 0); in bxt_cdclk_cd2x_div_sel()
1715 static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv, in cdclk_squash_waveform() argument
1718 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in cdclk_squash_waveform()
1721 if (cdclk == dev_priv->display.cdclk.hw.bypass) in cdclk_squash_waveform()
1725 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in cdclk_squash_waveform()
1729 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in cdclk_squash_waveform()
1730 cdclk, dev_priv->display.cdclk.hw.ref); in cdclk_squash_waveform()
1841 static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) in pll_enable_wa_needed() argument
1843 return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) && in pll_enable_wa_needed()
1844 dev_priv->display.cdclk.hw.vco > 0 && in pll_enable_wa_needed()
1845 HAS_CDCLK_SQUASH(dev_priv)); in pll_enable_wa_needed()
1848 static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, in _bxt_set_cdclk() argument
1858 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
1859 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { in _bxt_set_cdclk()
1860 if (dev_priv->display.cdclk.hw.vco != vco) in _bxt_set_cdclk()
1861 adlp_cdclk_pll_crawl(dev_priv, vco); in _bxt_set_cdclk()
1862 } else if (DISPLAY_VER(dev_priv) >= 11) { in _bxt_set_cdclk()
1864 if (pll_enable_wa_needed(dev_priv)) in _bxt_set_cdclk()
1865 dg2_cdclk_squash_program(dev_priv, 0); in _bxt_set_cdclk()
1867 icl_cdclk_pll_update(dev_priv, vco); in _bxt_set_cdclk()
1869 bxt_cdclk_pll_update(dev_priv, vco); in _bxt_set_cdclk()
1871 waveform = cdclk_squash_waveform(dev_priv, cdclk); in _bxt_set_cdclk()
1878 if (HAS_CDCLK_SQUASH(dev_priv)) in _bxt_set_cdclk()
1879 dg2_cdclk_squash_program(dev_priv, waveform); in _bxt_set_cdclk()
1881 val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) | in _bxt_set_cdclk()
1882 bxt_cdclk_cd2x_pipe(dev_priv, pipe) | in _bxt_set_cdclk()
1889 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && in _bxt_set_cdclk()
1892 intel_de_write(dev_priv, CDCLK_CTL, val); in _bxt_set_cdclk()
1895 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); in _bxt_set_cdclk()
1898 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, in bxt_set_cdclk() argument
1912 if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv)) in bxt_set_cdclk()
1914 else if (DISPLAY_VER(dev_priv) >= 11) in bxt_set_cdclk()
1915 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
1924 ret = snb_pcode_write_timeout(&dev_priv->uncore, in bxt_set_cdclk()
1929 drm_err(&dev_priv->drm, in bxt_set_cdclk()
1935 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, in bxt_set_cdclk()
1937 _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe); in bxt_set_cdclk()
1938 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); in bxt_set_cdclk()
1940 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); in bxt_set_cdclk()
1943 if (DISPLAY_VER(dev_priv) >= 14) in bxt_set_cdclk()
1948 else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv)) in bxt_set_cdclk()
1949 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
1951 if (DISPLAY_VER(dev_priv) < 11) { in bxt_set_cdclk()
1958 ret = snb_pcode_write_timeout(&dev_priv->uncore, in bxt_set_cdclk()
1964 drm_err(&dev_priv->drm, in bxt_set_cdclk()
1970 intel_update_cdclk(dev_priv); in bxt_set_cdclk()
1972 if (DISPLAY_VER(dev_priv) >= 11) in bxt_set_cdclk()
1977 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
1980 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) in bxt_sanitize_cdclk() argument
1985 intel_update_cdclk(dev_priv); in bxt_sanitize_cdclk()
1986 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
1988 if (dev_priv->display.cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
1989 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_sanitize_cdclk()
1998 cdctl = intel_de_read(dev_priv, CDCLK_CTL); in bxt_sanitize_cdclk()
2004 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); in bxt_sanitize_cdclk()
2007 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); in bxt_sanitize_cdclk()
2008 if (cdclk != dev_priv->display.cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2012 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_sanitize_cdclk()
2013 if (vco != dev_priv->display.cdclk.hw.vco) in bxt_sanitize_cdclk()
2019 if (HAS_CDCLK_SQUASH(dev_priv)) in bxt_sanitize_cdclk()
2020 clock = dev_priv->display.cdclk.hw.vco / 2; in bxt_sanitize_cdclk()
2022 clock = dev_priv->display.cdclk.hw.cdclk; in bxt_sanitize_cdclk()
2024 expected |= bxt_cdclk_cd2x_div_sel(dev_priv, clock, in bxt_sanitize_cdclk()
2025 dev_priv->display.cdclk.hw.vco); in bxt_sanitize_cdclk()
2031 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && in bxt_sanitize_cdclk()
2032 dev_priv->display.cdclk.hw.cdclk >= 500000) in bxt_sanitize_cdclk()
2040 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
2043 dev_priv->display.cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
2046 dev_priv->display.cdclk.hw.vco = -1; in bxt_sanitize_cdclk()
2049 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) in bxt_cdclk_init_hw() argument
2053 bxt_sanitize_cdclk(dev_priv); in bxt_cdclk_init_hw()
2055 if (dev_priv->display.cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
2056 dev_priv->display.cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2059 cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_init_hw()
2066 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); in bxt_cdclk_init_hw()
2067 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2069 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2071 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in bxt_cdclk_init_hw()
2074 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) in bxt_cdclk_uninit_hw() argument
2076 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_uninit_hw()
2081 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
2083 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in bxt_cdclk_uninit_hw()
2140 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, in intel_cdclk_can_crawl() argument
2146 if (!HAS_CDCLK_CRAWL(dev_priv)) in intel_cdclk_can_crawl()
2162 static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, in intel_cdclk_can_squash() argument
2172 if (!HAS_CDCLK_SQUASH(dev_priv)) in intel_cdclk_can_squash()
2210 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, in intel_cdclk_can_cd2x_update() argument
2215 if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) in intel_cdclk_can_cd2x_update()
2224 if (HAS_CDCLK_SQUASH(dev_priv)) in intel_cdclk_can_cd2x_update()
2299 static void intel_set_cdclk(struct drm_i915_private *dev_priv, in intel_set_cdclk() argument
2305 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) in intel_set_cdclk()
2308 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2311 intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to"); in intel_set_cdclk()
2313 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_set_cdclk()
2319 intel_audio_cdclk_change_pre(dev_priv); in intel_set_cdclk()
2326 mutex_lock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2327 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
2331 &dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2334 intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); in intel_set_cdclk()
2336 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
2341 mutex_unlock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2343 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_set_cdclk()
2349 intel_audio_cdclk_change_post(dev_priv); in intel_set_cdclk()
2351 if (drm_WARN(&dev_priv->drm, in intel_set_cdclk()
2352 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), in intel_set_cdclk()
2354 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); in intel_set_cdclk()
2355 intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]"); in intel_set_cdclk()
2507 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_pixel_rate_to_cdclk() local
2510 if (DISPLAY_VER(dev_priv) >= 10) in intel_pixel_rate_to_cdclk()
2512 else if (DISPLAY_VER(dev_priv) == 9 || in intel_pixel_rate_to_cdclk()
2513 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_pixel_rate_to_cdclk()
2515 else if (IS_CHERRYVIEW(dev_priv)) in intel_pixel_rate_to_cdclk()
2526 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_planes_min_cdclk() local
2530 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) in intel_planes_min_cdclk()
2538 struct drm_i915_private *dev_priv = in intel_crtc_compute_min_cdclk() local
2548 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) in intel_crtc_compute_min_cdclk()
2560 if (DISPLAY_VER(dev_priv) == 10) { in intel_crtc_compute_min_cdclk()
2563 } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) { in intel_crtc_compute_min_cdclk()
2573 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) in intel_crtc_compute_min_cdclk()
2583 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_crtc_compute_min_cdclk()
2592 IS_VALLEYVIEW(dev_priv)) in intel_crtc_compute_min_cdclk()
2601 IS_GEMINILAKE(dev_priv)) in intel_crtc_compute_min_cdclk()
2631 if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { in intel_crtc_compute_min_cdclk()
2638 dev_priv->display.cdclk.max_cdclk_freq)); in intel_crtc_compute_min_cdclk()
2647 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_compute_min_cdclk() local
2673 min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state); in intel_compute_min_cdclk()
2688 for_each_pipe(dev_priv, pipe) in intel_compute_min_cdclk()
2691 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2692 drm_dbg_kms(&dev_priv->drm, in intel_compute_min_cdclk()
2694 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2717 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_compute_min_voltage_level() local
2743 for_each_pipe(dev_priv, pipe) in bxt_compute_min_voltage_level()
2753 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in vlv_modeset_calc_cdclk() local
2760 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); in vlv_modeset_calc_cdclk()
2764 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2767 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2771 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2809 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in skl_dpll0_vco() local
2816 vco = dev_priv->skl_preferred_vco_freq; in skl_dpll0_vco()
2877 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_modeset_calc_cdclk() local
2888 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); in bxt_modeset_calc_cdclk()
2889 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2895 intel_cdclk_calc_voltage_level(dev_priv, cdclk)); in bxt_modeset_calc_cdclk()
2898 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
2899 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2904 intel_cdclk_calc_voltage_level(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2955 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_get_cdclk_state() local
2958 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); in intel_atomic_get_cdclk_state()
3000 int intel_cdclk_init(struct drm_i915_private *dev_priv) in intel_cdclk_init() argument
3008 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, in intel_cdclk_init()
3031 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_calc_cdclk() local
3046 ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state); in intel_modeset_calc_cdclk()
3050 if (intel_cdclk_need_serialize(dev_priv, old_cdclk_state, new_cdclk_state)) { in intel_modeset_calc_cdclk()
3070 intel_cdclk_can_cd2x_update(dev_priv, in intel_modeset_calc_cdclk()
3077 crtc = intel_crtc_for_pipe(dev_priv, pipe); in intel_modeset_calc_cdclk()
3087 if (intel_cdclk_can_crawl_and_squash(dev_priv, in intel_modeset_calc_cdclk()
3090 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3092 } else if (intel_cdclk_can_squash(dev_priv, in intel_modeset_calc_cdclk()
3095 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3097 } else if (intel_cdclk_can_crawl(dev_priv, in intel_modeset_calc_cdclk()
3100 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3105 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3115 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3119 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3123 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3131 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) in intel_compute_max_dotclk() argument
3133 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
3135 if (DISPLAY_VER(dev_priv) >= 10) in intel_compute_max_dotclk()
3137 else if (DISPLAY_VER(dev_priv) == 9 || in intel_compute_max_dotclk()
3138 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_compute_max_dotclk()
3140 else if (IS_CHERRYVIEW(dev_priv)) in intel_compute_max_dotclk()
3142 else if (DISPLAY_VER(dev_priv) < 4) in intel_compute_max_dotclk()
3156 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) in intel_update_max_cdclk() argument
3158 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { in intel_update_max_cdclk()
3159 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3160 dev_priv->display.cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
3162 dev_priv->display.cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
3163 } else if (DISPLAY_VER(dev_priv) >= 11) { in intel_update_max_cdclk()
3164 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3165 dev_priv->display.cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
3167 dev_priv->display.cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
3168 } else if (IS_GEMINILAKE(dev_priv)) { in intel_update_max_cdclk()
3169 dev_priv->display.cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
3170 } else if (IS_BROXTON(dev_priv)) { in intel_update_max_cdclk()
3171 dev_priv->display.cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
3172 } else if (DISPLAY_VER(dev_priv) == 9) { in intel_update_max_cdclk()
3173 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; in intel_update_max_cdclk()
3176 vco = dev_priv->skl_preferred_vco_freq; in intel_update_max_cdclk()
3177 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in intel_update_max_cdclk()
3193 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
3194 } else if (IS_BROADWELL(dev_priv)) { in intel_update_max_cdclk()
3201 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) in intel_update_max_cdclk()
3202 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3203 else if (IS_BROADWELL_ULX(dev_priv)) in intel_update_max_cdclk()
3204 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3205 else if (IS_BROADWELL_ULT(dev_priv)) in intel_update_max_cdclk()
3206 dev_priv->display.cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
3208 dev_priv->display.cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
3209 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_update_max_cdclk()
3210 dev_priv->display.cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
3211 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_update_max_cdclk()
3212 dev_priv->display.cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
3215 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; in intel_update_max_cdclk()
3218 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); in intel_update_max_cdclk()
3220 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", in intel_update_max_cdclk()
3221 dev_priv->display.cdclk.max_cdclk_freq); in intel_update_max_cdclk()
3223 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", in intel_update_max_cdclk()
3224 dev_priv->max_dotclk_freq); in intel_update_max_cdclk()
3233 void intel_update_cdclk(struct drm_i915_private *dev_priv) in intel_update_cdclk() argument
3235 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); in intel_update_cdclk()
3243 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_cdclk()
3244 intel_de_write(dev_priv, GMBUSFREQ_VLV, in intel_update_cdclk()
3245 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3248 static int dg1_rawclk(struct drm_i915_private *dev_priv) in dg1_rawclk() argument
3254 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, in dg1_rawclk()
3260 static int cnp_rawclk(struct drm_i915_private *dev_priv) in cnp_rawclk() argument
3265 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { in cnp_rawclk()
3281 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) in cnp_rawclk()
3285 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); in cnp_rawclk()
3289 static int pch_rawclk(struct drm_i915_private *dev_priv) in pch_rawclk() argument
3291 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; in pch_rawclk()
3294 static int vlv_hrawclk(struct drm_i915_private *dev_priv) in vlv_hrawclk() argument
3297 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", in vlv_hrawclk()
3301 static int i9xx_hrawclk(struct drm_i915_private *dev_priv) in i9xx_hrawclk() argument
3315 clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; in i9xx_hrawclk()
3317 if (IS_MOBILE(dev_priv)) { in i9xx_hrawclk()
3364 u32 intel_read_rawclk(struct drm_i915_private *dev_priv) in intel_read_rawclk() argument
3368 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) in intel_read_rawclk()
3369 freq = dg1_rawclk(dev_priv); in intel_read_rawclk()
3370 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP) in intel_read_rawclk()
3377 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) in intel_read_rawclk()
3378 freq = cnp_rawclk(dev_priv); in intel_read_rawclk()
3379 else if (HAS_PCH_SPLIT(dev_priv)) in intel_read_rawclk()
3380 freq = pch_rawclk(dev_priv); in intel_read_rawclk()
3381 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_read_rawclk()
3382 freq = vlv_hrawclk(dev_priv); in intel_read_rawclk()
3383 else if (DISPLAY_VER(dev_priv) >= 3) in intel_read_rawclk()
3384 freq = i9xx_hrawclk(dev_priv); in intel_read_rawclk()
3560 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) in intel_init_cdclk_hooks() argument
3562 if (IS_METEORLAKE(dev_priv)) { in intel_init_cdclk_hooks()
3563 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; in intel_init_cdclk_hooks()
3564 dev_priv->display.cdclk.table = mtl_cdclk_table; in intel_init_cdclk_hooks()
3565 } else if (IS_DG2(dev_priv)) { in intel_init_cdclk_hooks()
3566 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3567 dev_priv->display.cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3568 } else if (IS_ALDERLAKE_P(dev_priv)) { in intel_init_cdclk_hooks()
3570 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { in intel_init_cdclk_hooks()
3571 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3572 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3573 } else if (IS_RAPTORLAKE_U(dev_priv)) { in intel_init_cdclk_hooks()
3574 dev_priv->display.cdclk.table = rplu_cdclk_table; in intel_init_cdclk_hooks()
3575 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3577 dev_priv->display.cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3578 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3580 } else if (IS_ROCKETLAKE(dev_priv)) { in intel_init_cdclk_hooks()
3581 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3582 dev_priv->display.cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3583 } else if (DISPLAY_VER(dev_priv) >= 12) { in intel_init_cdclk_hooks()
3584 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3585 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3586 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { in intel_init_cdclk_hooks()
3587 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3588 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3589 } else if (DISPLAY_VER(dev_priv) >= 11) { in intel_init_cdclk_hooks()
3590 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3591 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3592 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_init_cdclk_hooks()
3593 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3594 if (IS_GEMINILAKE(dev_priv)) in intel_init_cdclk_hooks()
3595 dev_priv->display.cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3597 dev_priv->display.cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3598 } else if (DISPLAY_VER(dev_priv) == 9) { in intel_init_cdclk_hooks()
3599 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3600 } else if (IS_BROADWELL(dev_priv)) { in intel_init_cdclk_hooks()
3601 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3602 } else if (IS_HASWELL(dev_priv)) { in intel_init_cdclk_hooks()
3603 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3604 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
3605 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3606 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
3607 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3608 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) { in intel_init_cdclk_hooks()
3609 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3610 } else if (IS_IRONLAKE(dev_priv)) { in intel_init_cdclk_hooks()
3611 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3612 } else if (IS_GM45(dev_priv)) { in intel_init_cdclk_hooks()
3613 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3614 } else if (IS_G45(dev_priv)) { in intel_init_cdclk_hooks()
3615 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3616 } else if (IS_I965GM(dev_priv)) { in intel_init_cdclk_hooks()
3617 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3618 } else if (IS_I965G(dev_priv)) { in intel_init_cdclk_hooks()
3619 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3620 } else if (IS_PINEVIEW(dev_priv)) { in intel_init_cdclk_hooks()
3621 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3622 } else if (IS_G33(dev_priv)) { in intel_init_cdclk_hooks()
3623 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3624 } else if (IS_I945GM(dev_priv)) { in intel_init_cdclk_hooks()
3625 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3626 } else if (IS_I945G(dev_priv)) { in intel_init_cdclk_hooks()
3627 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3628 } else if (IS_I915GM(dev_priv)) { in intel_init_cdclk_hooks()
3629 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3630 } else if (IS_I915G(dev_priv)) { in intel_init_cdclk_hooks()
3631 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3632 } else if (IS_I865G(dev_priv)) { in intel_init_cdclk_hooks()
3633 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3634 } else if (IS_I85X(dev_priv)) { in intel_init_cdclk_hooks()
3635 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3636 } else if (IS_I845G(dev_priv)) { in intel_init_cdclk_hooks()
3637 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3638 } else if (IS_I830(dev_priv)) { in intel_init_cdclk_hooks()
3639 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3642 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, in intel_init_cdclk_hooks()
3644 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()