Lines Matching full:450000
139 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
470 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
472 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
722 else if (min_cdclk > 450000) in bdw_calc_cdclk()
725 return 450000; in bdw_calc_cdclk()
736 case 450000: in bdw_calc_voltage_level()
754 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
756 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
780 case 450000: in bdw_cdclk_freq_sel()
856 else if (min_cdclk > 450000) in skl_calc_cdclk()
859 return 450000; in skl_calc_cdclk()
869 else if (cdclk > 450000) in skl_calc_voltage_level()
953 cdclk_config->cdclk = 450000; in skl_get_cdclk()
1060 case 450000: in skl_cdclk_freq_sel()
3202 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3204 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()