824 	dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;  in g4x_setup_wm_latency()
825 	dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_SR] = 12;  in g4x_setup_wm_latency()
826 	dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;  in g4x_setup_wm_latency()
881 	unsigned int latency = dev_priv->display.wm.pri_latency[level] * 10;  in g4x_compute_wm()
1388 	dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;  in vlv_setup_wm_latency()
1393 		dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;  in vlv_setup_wm_latency()
1394 		dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;  in vlv_setup_wm_latency()
1410 	if (dev_priv->display.wm.pri_latency[level] == 0)  in vlv_compute_wm_level()
1431 				    dev_priv->display.wm.pri_latency[level] * 10);  in vlv_compute_wm_level()
2584 	u16 pri_latency = dev_priv->display.wm.pri_latency[level];  in ilk_compute_wm_level()  local
2590 		pri_latency *= 5;  in ilk_compute_wm_level()
2597 						     pri_latency, level);  in ilk_compute_wm_level()
2694 	changed = ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.pri_latency, 12);  in snb_wm_latency_quirk()
2703 	intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency);  in snb_wm_latency_quirk()
2721 	if (dev_priv->display.wm.pri_latency[3] == 0 &&  in snb_wm_lp3_irq_quirk()
2726 	dev_priv->display.wm.pri_latency[3] = 0;  in snb_wm_lp3_irq_quirk()
2732 	intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency);  in snb_wm_lp3_irq_quirk()
2740 		hsw_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);  in ilk_setup_wm_latency()
2742 		snb_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);  in ilk_setup_wm_latency()
2744 		ilk_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);  in ilk_setup_wm_latency()
2746 	memcpy(dev_priv->display.wm.spr_latency, dev_priv->display.wm.pri_latency,  in ilk_setup_wm_latency()
2747 	       sizeof(dev_priv->display.wm.pri_latency));  in ilk_setup_wm_latency()
2748 	memcpy(dev_priv->display.wm.cur_latency, dev_priv->display.wm.pri_latency,  in ilk_setup_wm_latency()
2749 	       sizeof(dev_priv->display.wm.pri_latency));  in ilk_setup_wm_latency()
2754 	intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency);  in ilk_setup_wm_latency()
3018 		return dev_priv->display.wm.pri_latency[level];  in ilk_wm_lp_latency()