828 	dev_priv->display.wm.num_levels = G4X_WM_LEVEL_HPLL + 1;  in g4x_setup_wm_latency()
935 	for (; level < dev_priv->display.wm.num_levels; level++) {  in g4x_raw_plane_wm_set()
954 	for (; level < dev_priv->display.wm.num_levels; level++) {  in g4x_raw_fbc_wm_set()
984 	for (level = 0; level < dev_priv->display.wm.num_levels; level++) {  in g4x_raw_plane_wm_compute()
1054 	if (level >= dev_priv->display.wm.num_levels)  in g4x_raw_crtc_wm_is_valid()
1390 	dev_priv->display.wm.num_levels = VLV_WM_LEVEL_PM2 + 1;  in vlv_setup_wm_latency()
1396 		dev_priv->display.wm.num_levels = VLV_WM_LEVEL_DDR_DVFS + 1;  in vlv_setup_wm_latency()
1532 	for (; level < dev_priv->display.wm.num_levels; level++) {  in vlv_invalidate_wms()
1561 	for (; level < dev_priv->display.wm.num_levels; level++) {  in vlv_raw_plane_wm_set()
1585 	for (level = 0; level < dev_priv->display.wm.num_levels; level++) {  in vlv_raw_plane_wm_compute()
1644 	wm_state->num_levels = dev_priv->display.wm.num_levels;  in _vlv_compute_pipe_wm()
1652 	for (level = 0; level < wm_state->num_levels; level++) {  in _vlv_compute_pipe_wm()
1680 	wm_state->num_levels = level;  in _vlv_compute_pipe_wm()
1869 	intermediate->num_levels = min(optimal->num_levels, active->num_levels);  in vlv_compute_intermediate_wm()
1873 	for (level = 0; level < intermediate->num_levels; level++) {  in vlv_compute_intermediate_wm()
1907 	wm->level = dev_priv->display.wm.num_levels - 1;  in vlv_merge_wm()
1920 		wm->level = min_t(int, wm->level, wm_state->num_levels - 1);  in vlv_merge_wm()
2614 	i915->display.wm.num_levels = 5;  in hsw_read_wm_latency()
2631 	i915->display.wm.num_levels = 4;  in snb_read_wm_latency()
2645 	i915->display.wm.num_levels = 3;  in ilk_read_wm_latency()
2680 	for (level = 1; level < dev_priv->display.wm.num_levels; level++)  in ilk_increase_wm_latency()
2818 	usable_level = dev_priv->display.wm.num_levels - 1;  in ilk_compute_pipe_wm()
2889 	for (level = 0; level < dev_priv->display.wm.num_levels; level++) {  in ilk_compute_intermediate_wm()
2960 	int level, num_levels = dev_priv->display.wm.num_levels;  in ilk_wm_merge()  local
2961 	int last_enabled_level = num_levels - 1;  in ilk_wm_merge()
2972 	for (level = 1; level < num_levels; level++) {  in ilk_wm_merge()
2997 		for (level = 2; level < num_levels; level++) {  in ilk_wm_merge()
3096 	for (level = 1; level < dev_priv->display.wm.num_levels; level++) {  in ilk_find_best_result()
3377 		for (level = 0; level < dev_priv->display.wm.num_levels; level++)  in ilk_pipe_wm_get_hw_state()
3726 		for (level = 0; level < dev_priv->display.wm.num_levels; level++) {  in g4x_wm_sanitize()
3797 			dev_priv->display.wm.num_levels = VLV_WM_LEVEL_PM5 + 1;  in vlv_wm_get_hw_state()
3819 		active->num_levels = wm->level + 1;  in vlv_wm_get_hw_state()
3822 		for (level = 0; level < active->num_levels; level++) {  in vlv_wm_get_hw_state()
3881 		for (level = 0; level < dev_priv->display.wm.num_levels; level++) {  in vlv_wm_sanitize()