237 		dev_priv->display.wm.g4x.cxsr = enable;  in intel_set_memory_cxsr()
936 		struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];  in g4x_raw_plane_wm_set()
955 		struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];  in g4x_raw_fbc_wm_set()
985 		struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];  in g4x_raw_plane_wm_compute()
1027 			    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],  in g4x_raw_plane_wm_compute()
1028 			    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],  in g4x_raw_plane_wm_compute()
1029 			    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);  in g4x_raw_plane_wm_compute()
1034 				    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,  in g4x_raw_plane_wm_compute()
1035 				    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);  in g4x_raw_plane_wm_compute()
1044 	const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];  in g4x_raw_plane_wm_is_valid()
1108 	struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;  in _g4x_compute_pipe_wm()
1118 	raw = &crtc_state->wm.g4x.raw[level];  in _g4x_compute_pipe_wm()
1126 	raw = &crtc_state->wm.g4x.raw[level];  in _g4x_compute_pipe_wm()
1137 	raw = &crtc_state->wm.g4x.raw[level];  in _g4x_compute_pipe_wm()
1201 	struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;  in g4x_compute_intermediate_wm()
1202 	const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;  in g4x_compute_intermediate_wm()
1203 	const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;  in g4x_compute_intermediate_wm()
1286 		const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;  in g4x_merge_wm()
1308 		const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;  in g4x_merge_wm()
1321 	struct g4x_wm_values *old_wm = &dev_priv->display.wm.g4x;  in g4x_program_watermarks()
1348 	crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;  in g4x_initial_watermarks()
1364 	crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;  in g4x_optimize_watermarks()
3615 	struct g4x_wm_values *wm = &dev_priv->display.wm.g4x;  in g4x_wm_get_hw_state()
3625 		struct g4x_wm_state *active = &crtc->wm.active.g4x;  in g4x_wm_get_hw_state()
3651 		raw = &crtc_state->wm.g4x.raw[level];  in g4x_wm_get_hw_state()
3659 		raw = &crtc_state->wm.g4x.raw[level];  in g4x_wm_get_hw_state()
3669 		raw = &crtc_state->wm.g4x.raw[level];  in g4x_wm_get_hw_state()
3684 		crtc_state->wm.g4x.optimal = *active;  in g4x_wm_get_hw_state()
3685 		crtc_state->wm.g4x.intermediate = *active;  in g4x_wm_get_hw_state()
3728 				&crtc_state->wm.g4x.raw[level];  in g4x_wm_sanitize()
3745 		crtc_state->wm.g4x.intermediate =  in g4x_wm_sanitize()
3746 			crtc_state->wm.g4x.optimal;  in g4x_wm_sanitize()
3747 		crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;  in g4x_wm_sanitize()