256 	uint32_t DP;  member
1045 	intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;  in cdv_intel_dp_mode_set()
1046 	intel_dp->DP |= intel_dp->color_range;  in cdv_intel_dp_mode_set()
1049 		intel_dp->DP |= DP_SYNC_HS_HIGH;  in cdv_intel_dp_mode_set()
1051 		intel_dp->DP |= DP_SYNC_VS_HIGH;  in cdv_intel_dp_mode_set()
1053 	intel_dp->DP |= DP_LINK_TRAIN_OFF;  in cdv_intel_dp_mode_set()
1057 		intel_dp->DP |= DP_PORT_WIDTH_1;  in cdv_intel_dp_mode_set()
1060 		intel_dp->DP |= DP_PORT_WIDTH_2;  in cdv_intel_dp_mode_set()
1063 		intel_dp->DP |= DP_PORT_WIDTH_4;  in cdv_intel_dp_mode_set()
1067 		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;  in cdv_intel_dp_mode_set()
1079 		intel_dp->DP |= DP_ENHANCED_FRAMING;  in cdv_intel_dp_mode_set()
1084 		intel_dp->DP |= DP_PIPEB_SELECT;  in cdv_intel_dp_mode_set()
1086 	REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));  in cdv_intel_dp_mode_set()
1087 	DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);  in cdv_intel_dp_mode_set()
1474 	uint32_t DP = intel_dp->DP;  in cdv_intel_dp_start_link_train()  local
1476 	DP |= DP_PORT_EN;  in cdv_intel_dp_start_link_train()
1477 	DP &= ~DP_LINK_TRAIN_MASK;  in cdv_intel_dp_start_link_train()
1479 	reg = DP;  in cdv_intel_dp_start_link_train()
1498 	reg = DP | DP_LINK_TRAIN_PAT_1;  in cdv_intel_dp_start_link_train()
1554 	intel_dp->DP = DP;  in cdv_intel_dp_start_link_train()
1564 	uint32_t DP = intel_dp->DP;  in cdv_intel_dp_complete_link_train()  local
1571 	reg = DP | DP_LINK_TRAIN_PAT_2;  in cdv_intel_dp_complete_link_train()
1632 	reg = DP | DP_LINK_TRAIN_OFF;  in cdv_intel_dp_complete_link_train()
1645 	uint32_t DP = intel_dp->DP;  in cdv_intel_dp_link_down()  local
1654 		DP &= ~DP_LINK_TRAIN_MASK;  in cdv_intel_dp_link_down()
1655 		REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);  in cdv_intel_dp_link_down()
1661 	REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);  in cdv_intel_dp_link_down()