Lines Matching refs:gpu_write
475 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
477 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
523 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
526 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, in etnaviv_hw_reset()
531 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
539 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
543 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
566 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
652 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); in etnaviv_gpu_start_fe()
653 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
658 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
733 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); in etnaviv_gpu_hw_init()
743 gpu_write(gpu, VIVS_HI_AXI_CONFIG, in etnaviv_gpu_hw_init()
754 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); in etnaviv_gpu_hw_init()
760 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); in etnaviv_gpu_hw_init()
766 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); in etnaviv_gpu_hw_init()
1319 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); in sync_point_perfmon_sample_pre()
1342 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); in sync_point_perfmon_sample_post()