770 			       const u8 port_cap[4], u8 type)  in drm_dp_downstream_is_type()
774 		(port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;  in drm_dp_downstream_is_type()
787 			       const u8 port_cap[4],  in drm_dp_downstream_is_tmds()
799 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_is_tmds()
1016 				   const u8 port_cap[4])  in drm_dp_downstream_max_dotclock()
1024 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_max_dotclock()
1028 		return port_cap[1] * 8000;  in drm_dp_downstream_max_dotclock()
1045 				     const u8 port_cap[4],  in drm_dp_downstream_max_tmds_clock()
1060 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_max_tmds_clock()
1088 		return port_cap[1] * 2500;  in drm_dp_downstream_max_tmds_clock()
1093 		return port_cap[1] * 2500;  in drm_dp_downstream_max_tmds_clock()
1110 				     const u8 port_cap[4],  in drm_dp_downstream_min_tmds_clock()
1125 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_min_tmds_clock()
1153 			      const u8 port_cap[4],  in drm_dp_downstream_max_bpc()
1168 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_max_bpc()
1181 		switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {  in drm_dp_downstream_max_bpc()
1209 				       const u8 port_cap[4])  in drm_dp_downstream_420_passthrough()
1217 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_420_passthrough()
1224 		return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;  in drm_dp_downstream_420_passthrough()
1240 					     const u8 port_cap[4])  in drm_dp_downstream_444_to_420_conversion()
1248 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_444_to_420_conversion()
1253 		return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;  in drm_dp_downstream_444_to_420_conversion()
1271 					       const u8 port_cap[4],  in drm_dp_downstream_rgb_to_ycbcr_conversion()
1280 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_rgb_to_ycbcr_conversion()
1285 		return port_cap[3] & color_spc;  in drm_dp_downstream_rgb_to_ycbcr_conversion()
1305 		       const u8 port_cap[4])  in drm_dp_downstream_mode()
1316 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_mode()
1318 		switch (port_cap[0] & DP_DS_NON_EDID_MASK) {  in drm_dp_downstream_mode()
1371 			     const u8 port_cap[4],  in drm_dp_downstream_debug()
1382 	int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;  in drm_dp_downstream_debug()
1431 		clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);  in drm_dp_downstream_debug()
1435 		clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid);  in drm_dp_downstream_debug()
1439 		clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid);  in drm_dp_downstream_debug()
1443 		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);  in drm_dp_downstream_debug()
1458 			 const u8 port_cap[4])  in drm_dp_subconnector_type()
1482 	type = port_cap[0] & DP_DS_PORT_TYPE_MASK;  in drm_dp_subconnector_type()
1515 				      const u8 port_cap[4])  in drm_dp_set_subconnector_property()
1520 		subconnector = drm_dp_subconnector_type(dpcd, port_cap);  in drm_dp_set_subconnector_property()
2893 			       const u8 port_cap[4])  in drm_dp_get_pcon_max_frl_bw()
2898 	buf = port_cap[2];  in drm_dp_get_pcon_max_frl_bw()