Lines Matching full:x1
123 #define RESET_DP_TX (0x1 << 0)
126 #define MASTER_VID_FUNC_EN_N (0x1 << 7)
127 #define RK_VID_CAP_FUNC_EN_N (0x1 << 6)
128 #define SLAVE_VID_FUNC_EN_N (0x1 << 5)
129 #define RK_VID_FIFO_FUNC_EN_N (0x1 << 5)
130 #define AUD_FIFO_FUNC_EN_N (0x1 << 4)
131 #define AUD_FUNC_EN_N (0x1 << 3)
132 #define HDCP_FUNC_EN_N (0x1 << 2)
133 #define CRC_FUNC_EN_N (0x1 << 1)
134 #define SW_FUNC_EN_N (0x1 << 0)
137 #define SSC_FUNC_EN_N (0x1 << 7)
138 #define AUX_FUNC_EN_N (0x1 << 2)
139 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
140 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
143 #define VIDEO_EN (0x1 << 7)
144 #define HDCP_VIDEO_MUTE (0x1 << 6)
147 #define IN_D_RANGE_MASK (0x1 << 7)
149 #define IN_D_RANGE_CEA (0x1 << 7)
155 #define IN_BPC_8_BITS (0x1 << 4)
160 #define IN_COLOR_F_YCBCR422 (0x1 << 0)
164 #define IN_YC_COEFFI_MASK (0x1 << 7)
166 #define IN_YC_COEFFI_ITU709 (0x1 << 7)
168 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4)
170 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
172 #define REUSE_SPD_EN (0x1 << 3)
179 #define FORMAT_SEL (0x1 << 4)
180 #define INTERACE_SCAN_CFG (0x1 << 2)
181 #define VSYNC_POLARITY_CFG (0x1 << 1)
182 #define HSYNC_POLARITY_CFG (0x1 << 0)
185 #define REF_CLK_24M (0x1 << 0)
187 #define REF_CLK_MASK (0x1 << 0)
190 #define PSR_FRAME_UP_TYPE_BURST (0x1 << 0)
192 #define PSR_CRC_SEL_HARDWARE (0x1 << 1)
197 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6)
201 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4)
205 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2)
209 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0)
214 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4)
217 #define SEL_24M (0x1 << 3)
225 #define PD_RING_OSC (0x1 << 6)
227 #define TX_CUR1_2X (0x1 << 2)
240 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3)
246 #define VSYNC_DET (0x1 << 7)
247 #define PLL_LOCK_CHG (0x1 << 6)
248 #define SPDIF_ERR (0x1 << 5)
249 #define SPDIF_UNSTBL (0x1 << 4)
250 #define VID_FORMAT_CHG (0x1 << 3)
251 #define AUD_CLK_CHG (0x1 << 2)
252 #define VID_CLK_CHG (0x1 << 1)
253 #define SW_INT (0x1 << 0)
256 #define ENC_EN_CHG (0x1 << 6)
257 #define HW_BKSV_RDY (0x1 << 3)
258 #define HW_SHA_DONE (0x1 << 2)
259 #define HW_AUTH_STATE_CHG (0x1 << 1)
260 #define HW_AUTH_DONE (0x1 << 0)
263 #define AFIFO_UNDER (0x1 << 7)
264 #define AFIFO_OVER (0x1 << 6)
265 #define R0_CHK_FLAG (0x1 << 5)
268 #define PSR_ACTIVE (0x1 << 7)
269 #define PSR_INACTIVE (0x1 << 6)
270 #define SPDIF_BI_PHASE_ERR (0x1 << 5)
271 #define HOTPLUG_CHG (0x1 << 2)
272 #define HPD_LOST (0x1 << 1)
273 #define PLUG (0x1 << 0)
276 #define INT_HPD (0x1 << 6)
277 #define HW_TRAINING_FINISH (0x1 << 5)
278 #define RPLY_RECEIV (0x1 << 1)
279 #define AUX_ERR (0x1 << 0)
282 #define SOFT_INT_CTRL (0x1 << 2)
283 #define INT_POL1 (0x1 << 1)
284 #define INT_POL0 (0x1 << 0)
287 #define DET_STA (0x1 << 2)
288 #define FORCE_DET (0x1 << 1)
289 #define DET_CTRL (0x1 << 0)
293 #define CHA_STA (0x1 << 2)
294 #define FORCE_CHA (0x1 << 1)
295 #define CHA_CTRL (0x1 << 0)
298 #define HPD_STATUS (0x1 << 6)
299 #define F_HPD (0x1 << 5)
300 #define HPD_CTRL (0x1 << 4)
301 #define HDCP_RDY (0x1 << 3)
302 #define STRM_VALID (0x1 << 2)
303 #define F_VALID (0x1 << 1)
304 #define VALID_CTRL (0x1 << 0)
307 #define FIX_M_AUD (0x1 << 4)
308 #define ENHANCED (0x1 << 3)
309 #define FIX_M_VID (0x1 << 2)
313 #define SCRAMBLER_TYPE (0x1 << 9)
314 #define HW_LINK_TRAINING_PATTERN (0x1 << 8)
315 #define SCRAMBLING_DISABLE (0x1 << 5)
319 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
323 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
331 #define PLL_LOCK (0x1 << 4)
332 #define F_PLL_LOCK (0x1 << 3)
333 #define PLL_LOCK_CTRL (0x1 << 2)
334 #define PN_INV (0x1 << 0)
337 #define DP_PLL_PD (0x1 << 7)
338 #define DP_PLL_RESET (0x1 << 6)
339 #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4)
344 #define DP_INC_BG (0x1 << 7)
345 #define DP_EXP_BG (0x1 << 6)
346 #define DP_PHY_PD (0x1 << 5)
347 #define RK_AUX_PD (0x1 << 5)
348 #define AUX_PD (0x1 << 4)
349 #define RK_PLL_PD (0x1 << 4)
350 #define CH3_PD (0x1 << 3)
351 #define CH2_PD (0x1 << 2)
352 #define CH1_PD (0x1 << 1)
353 #define CH0_PD (0x1 << 0)
357 #define MACRO_RST (0x1 << 5)
358 #define CH1_TEST (0x1 << 1)
359 #define CH0_TEST (0x1 << 0)
362 #define AUX_BUSY (0x1 << 4)
366 #define DEFER_CTRL_EN (0x1 << 7)
374 #define BUF_CLR (0x1 << 7)
380 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
382 #define AUX_TX_COMM_MOT (0x1 << 2)
384 #define AUX_TX_COMM_READ (0x1 << 0)
396 #define ADDR_ONLY (0x1 << 1)
397 #define AUX_EN (0x1 << 0)
400 #define AUDIO_MODE_SPDIF_MODE (0x1 << 8)
402 #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4)
403 #define VIDEO_MASTER_CLK_SEL (0x1 << 2)
404 #define VIDEO_MASTER_MODE_EN (0x1 << 1)
405 #define VIDEO_MODE_MASK (0x1 << 0)
406 #define VIDEO_MODE_SLAVE_MODE (0x1 << 0)
410 #define IF_UP (0x1 << 4)
411 #define IF_EN (0x1 << 0)
414 #define PSR_VID_CRC_FLUSH (0x1 << 2)
415 #define PSR_VID_CRC_ENABLE (0x1 << 0)