679 	u16 pass[32][2][2];  in finetuneDQSI()  local
693 		pass[dqidly][0][0] = 0xff;  in finetuneDQSI()
694 		pass[dqidly][0][1] = 0x0;  in finetuneDQSI()
695 		pass[dqidly][1][0] = 0xff;  in finetuneDQSI()
696 		pass[dqidly][1][1] = 0x0;  in finetuneDQSI()
713 					if (dlli < pass[dqidly][dqsip][0])  in finetuneDQSI()
714 						pass[dqidly][dqsip][0] = (u16) dlli;  in finetuneDQSI()
715 					if (dlli > pass[dqidly][dqsip][1])  in finetuneDQSI()
716 						pass[dqidly][dqsip][1] = (u16) dlli;  in finetuneDQSI()
720 					pass[dqidly][dqsip][0] = 0xff;  in finetuneDQSI()
721 					pass[dqidly][dqsip][1] = 0x0;  in finetuneDQSI()
733 			if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])  in finetuneDQSI()
735 			diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];  in finetuneDQSI()
739 			for (dlli = pass[dqidly][dqsip][0]; dlli > 0  && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);  in finetuneDQSI()
740 			for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);  in finetuneDQSI()
1694 	u32 data, pass, timecnt;  in ddr_phy_init_2500()  local
1696 	pass = 0;  in ddr_phy_init_2500()
1698 	while (!pass) {  in ddr_phy_init_2500()
1707 				pass = 1;  in ddr_phy_init_2500()
1709 		if (!pass) {  in ddr_phy_init_2500()
1854 	u32 data, data2, pass, retrycnt;  in ddr4_init_2500()  local
1889 	pass = 0;  in ddr4_init_2500()
1891 	for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {  in ddr4_init_2500()
1893 		pass = 0;  in ddr4_init_2500()
1903 				pass++;  in ddr4_init_2500()
1913 			} else if (pass > 0)  in ddr4_init_2500()
1920 	pass = 0;  in ddr4_init_2500()
1922 	for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {  in ddr4_init_2500()
1925 		pass = 0;  in ddr4_init_2500()
1934 				pass++;  in ddr4_init_2500()
1939 			} else if (pass != 0)  in ddr4_init_2500()