Lines Matching refs:ast
46 struct ast_device *ast = to_ast_device(dev); in ast_set_def_ext_reg() local
52 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); in ast_set_def_ext_reg()
54 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) in ast_set_def_ext_reg()
61 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info); in ast_set_def_ext_reg()
70 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01); in ast_set_def_ext_reg()
71 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00); in ast_set_def_ext_reg()
75 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) in ast_set_def_ext_reg()
77 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); in ast_set_def_ext_reg()
80 u32 ast_mindwm(struct ast_device *ast, u32 r) in ast_mindwm() argument
84 ast_write32(ast, 0xf004, r & 0xffff0000); in ast_mindwm()
85 ast_write32(ast, 0xf000, 0x1); in ast_mindwm()
88 data = ast_read32(ast, 0xf004) & 0xffff0000; in ast_mindwm()
90 return ast_read32(ast, 0x10000 + (r & 0x0000ffff)); in ast_mindwm()
93 void ast_moutdwm(struct ast_device *ast, u32 r, u32 v) in ast_moutdwm() argument
96 ast_write32(ast, 0xf004, r & 0xffff0000); in ast_moutdwm()
97 ast_write32(ast, 0xf000, 0x1); in ast_moutdwm()
99 data = ast_read32(ast, 0xf004) & 0xffff0000; in ast_moutdwm()
101 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v); in ast_moutdwm()
132 static u32 mmctestburst2_ast2150(struct ast_device *ast, u32 datagen) in mmctestburst2_ast2150() argument
136 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
137 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3)); in mmctestburst2_ast2150()
140 data = ast_mindwm(ast, 0x1e6e0070) & 0x40; in mmctestburst2_ast2150()
142 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
146 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
147 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3)); in mmctestburst2_ast2150()
150 data = ast_mindwm(ast, 0x1e6e0070) & 0x40; in mmctestburst2_ast2150()
152 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
156 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7; in mmctestburst2_ast2150()
157 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
162 static u32 mmctestsingle2_ast2150(struct ast_device *ast, u32 datagen)
166 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
167 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
170 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
172 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
176 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
177 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
182 static int cbrtest_ast2150(struct ast_device *ast) in cbrtest_ast2150() argument
187 if (mmctestburst2_ast2150(ast, i)) in cbrtest_ast2150()
192 static int cbrscan_ast2150(struct ast_device *ast, int busw) in cbrscan_ast2150() argument
197 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]); in cbrscan_ast2150()
199 if (cbrtest_ast2150(ast)) in cbrscan_ast2150()
209 static void cbrdlli_ast2150(struct ast_device *ast, int busw) in cbrdlli_ast2150() argument
219 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); in cbrdlli_ast2150()
220 data = cbrscan_ast2150(ast, busw); in cbrdlli_ast2150()
236 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); in cbrdlli_ast2150()
243 struct ast_device *ast = to_ast_device(dev); in ast_init_dram_reg() local
248 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_init_dram_reg()
251 if (IS_AST_GEN1(ast)) { in ast_init_dram_reg()
253 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_init_dram_reg()
254 ast_write32(ast, 0xf000, 0x1); in ast_init_dram_reg()
255 ast_write32(ast, 0x10100, 0xa8); in ast_init_dram_reg()
259 } while (ast_read32(ast, 0x10100) != 0xa8); in ast_init_dram_reg()
261 if (ast->chip == AST2100 || ast->chip == AST2200) in ast_init_dram_reg()
266 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_init_dram_reg()
267 ast_write32(ast, 0xf000, 0x1); in ast_init_dram_reg()
268 ast_write32(ast, 0x12000, 0x1688A8A8); in ast_init_dram_reg()
271 } while (ast_read32(ast, 0x12000) != 0x01); in ast_init_dram_reg()
273 ast_write32(ast, 0x10000, 0xfc600309); in ast_init_dram_reg()
276 } while (ast_read32(ast, 0x10000) != 0x01); in ast_init_dram_reg()
283 } else if (dram_reg_info->index == 0x4 && !IS_AST_GEN1(ast)) { in ast_init_dram_reg()
285 if (ast->dram_type == AST_DRAM_1Gx16) in ast_init_dram_reg()
287 else if (ast->dram_type == AST_DRAM_1Gx32) in ast_init_dram_reg()
290 temp = ast_read32(ast, 0x12070); in ast_init_dram_reg()
293 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp); in ast_init_dram_reg()
295 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data); in ast_init_dram_reg()
300 data = ast_read32(ast, 0x10120); in ast_init_dram_reg()
302 data = ast_read32(ast, 0x10004); in ast_init_dram_reg()
304 cbrdlli_ast2150(ast, 16); /* 16 bits */ in ast_init_dram_reg()
306 cbrdlli_ast2150(ast, 32); /* 32 bits */ in ast_init_dram_reg()
309 switch (AST_GEN(ast)) { in ast_init_dram_reg()
311 temp = ast_read32(ast, 0x10140); in ast_init_dram_reg()
312 ast_write32(ast, 0x10140, temp | 0x40); in ast_init_dram_reg()
316 temp = ast_read32(ast, 0x1200c); in ast_init_dram_reg()
317 ast_write32(ast, 0x1200c, temp & 0xfffffffd); in ast_init_dram_reg()
318 temp = ast_read32(ast, 0x12040); in ast_init_dram_reg()
319 ast_write32(ast, 0x12040, temp | 0x40); in ast_init_dram_reg()
328 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_init_dram_reg()
334 struct ast_device *ast = to_ast_device(dev); in ast_post_gpu() local
338 if (IS_AST_GEN7(ast)) { in ast_post_gpu()
339 if (ast->tx_chip_types & AST_TX_ASTDP_BIT) in ast_post_gpu()
341 } else if (ast->config_mode == ast_use_p2a) { in ast_post_gpu()
342 if (IS_AST_GEN6(ast)) in ast_post_gpu()
344 else if (IS_AST_GEN5(ast) || IS_AST_GEN4(ast)) in ast_post_gpu()
351 if (ast->tx_chip_types & AST_TX_SIL164_BIT) in ast_post_gpu()
352 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */ in ast_post_gpu()
409 static bool mmc_test(struct ast_device *ast, u32 datagen, u8 test_ctl) in mmc_test() argument
413 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test()
414 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); in mmc_test()
417 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000; in mmc_test()
421 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test()
425 ast_moutdwm(ast, 0x1e6e0070, 0x0); in mmc_test()
429 static u32 mmc_test2(struct ast_device *ast, u32 datagen, u8 test_ctl) in mmc_test2() argument
433 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test2()
434 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); in mmc_test2()
437 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; in mmc_test2()
439 ast_moutdwm(ast, 0x1e6e0070, 0x0); in mmc_test2()
443 data = ast_mindwm(ast, 0x1e6e0078); in mmc_test2()
445 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test2()
450 static bool mmc_test_burst(struct ast_device *ast, u32 datagen) in mmc_test_burst() argument
452 return mmc_test(ast, datagen, 0xc1); in mmc_test_burst()
455 static u32 mmc_test_burst2(struct ast_device *ast, u32 datagen) in mmc_test_burst2() argument
457 return mmc_test2(ast, datagen, 0x41); in mmc_test_burst2()
460 static bool mmc_test_single(struct ast_device *ast, u32 datagen) in mmc_test_single() argument
462 return mmc_test(ast, datagen, 0xc5); in mmc_test_single()
465 static u32 mmc_test_single2(struct ast_device *ast, u32 datagen) in mmc_test_single2() argument
467 return mmc_test2(ast, datagen, 0x05); in mmc_test_single2()
470 static bool mmc_test_single_2500(struct ast_device *ast, u32 datagen) in mmc_test_single_2500() argument
472 return mmc_test(ast, datagen, 0x85); in mmc_test_single_2500()
475 static int cbr_test(struct ast_device *ast) in cbr_test() argument
479 data = mmc_test_single2(ast, 0); in cbr_test()
483 data = mmc_test_burst2(ast, i); in cbr_test()
494 static int cbr_scan(struct ast_device *ast) in cbr_scan() argument
500 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); in cbr_scan()
502 if ((data = cbr_test(ast)) != 0) { in cbr_scan()
515 static u32 cbr_test2(struct ast_device *ast) in cbr_test2() argument
519 data = mmc_test_burst2(ast, 0); in cbr_test2()
522 data |= mmc_test_single2(ast, 0); in cbr_test2()
529 static u32 cbr_scan2(struct ast_device *ast) in cbr_scan2() argument
535 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); in cbr_scan2()
537 if ((data = cbr_test2(ast)) != 0) { in cbr_scan2()
550 static bool cbr_test3(struct ast_device *ast) in cbr_test3() argument
552 if (!mmc_test_burst(ast, 0)) in cbr_test3()
554 if (!mmc_test_single(ast, 0)) in cbr_test3()
559 static bool cbr_scan3(struct ast_device *ast) in cbr_scan3() argument
564 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); in cbr_scan3()
566 if (cbr_test3(ast)) in cbr_scan3()
575 static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *param) in finetuneDQI_L() argument
586 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); in finetuneDQI_L()
587 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1); in finetuneDQI_L()
588 data = cbr_scan2(ast); in finetuneDQI_L()
645 ast_moutdwm(ast, 0x1E6E0080, data); in finetuneDQI_L()
670 ast_moutdwm(ast, 0x1E6E0084, data); in finetuneDQI_L()
674 static void finetuneDQSI(struct ast_device *ast) in finetuneDQSI() argument
683 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C); in finetuneDQSI()
684 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018); in finetuneDQSI()
686 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); in finetuneDQSI()
701 ast_moutdwm(ast, 0x1E6E000C, 0); in finetuneDQSI()
702 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23)); in finetuneDQSI()
703 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c); in finetuneDQSI()
705 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); in finetuneDQSI()
706 ast_moutdwm(ast, 0x1E6E0070, 0); in finetuneDQSI()
707 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0); in finetuneDQSI()
708 if (cbr_scan3(ast)) { in finetuneDQSI()
761 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); in finetuneDQSI()
764 static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param) in cbr_dll2() argument
769 finetuneDQSI(ast); in cbr_dll2()
770 if (finetuneDQI_L(ast, param) == false) in cbr_dll2()
778 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); in cbr_dll2()
779 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2); in cbr_dll2()
780 data = cbr_scan(ast); in cbr_dll2()
816 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16)); in cbr_dll2()
820 static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *param) in get_ddr3_info() argument
824 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); in get_ddr3_info()
827 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; in get_ddr3_info()
841 ast_moutdwm(ast, 0x1E6E2020, 0x0190); in get_ddr3_info()
869 ast_moutdwm(ast, 0x1E6E2020, 0x03F1); in get_ddr3_info()
899 ast_moutdwm(ast, 0x1E6E2020, 0x01F0); in get_ddr3_info()
929 ast_moutdwm(ast, 0x1E6E2020, 0x0230); in get_ddr3_info()
943 ast_moutdwm(ast, 0x1E6E2020, 0x0270); in get_ddr3_info()
957 ast_moutdwm(ast, 0x1E6E2020, 0x0290); in get_ddr3_info()
973 ast_moutdwm(ast, 0x1E6E2020, 0x0140); in get_ddr3_info()
991 ast_moutdwm(ast, 0x1E6E2020, 0x02E1); in get_ddr3_info()
1009 ast_moutdwm(ast, 0x1E6E2020, 0x0160); in get_ddr3_info()
1062 static void ddr3_init(struct ast_device *ast, struct ast2300_dram_param *param) in ddr3_init() argument
1067 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in ddr3_init()
1068 ast_moutdwm(ast, 0x1E6E0018, 0x00000100); in ddr3_init()
1069 ast_moutdwm(ast, 0x1E6E0024, 0x00000000); in ddr3_init()
1070 ast_moutdwm(ast, 0x1E6E0034, 0x00000000); in ddr3_init()
1072 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); in ddr3_init()
1073 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); in ddr3_init()
1075 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); in ddr3_init()
1078 ast_moutdwm(ast, 0x1E6E0004, param->dram_config); in ddr3_init()
1079 ast_moutdwm(ast, 0x1E6E0008, 0x90040f); in ddr3_init()
1080 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); in ddr3_init()
1081 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); in ddr3_init()
1082 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); in ddr3_init()
1083 ast_moutdwm(ast, 0x1E6E0080, 0x00000000); in ddr3_init()
1084 ast_moutdwm(ast, 0x1E6E0084, 0x00000000); in ddr3_init()
1085 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); in ddr3_init()
1086 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170); in ddr3_init()
1087 ast_moutdwm(ast, 0x1E6E0018, 0x00002370); in ddr3_init()
1088 ast_moutdwm(ast, 0x1E6E0038, 0x00000000); in ddr3_init()
1089 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444); in ddr3_init()
1090 ast_moutdwm(ast, 0x1E6E0044, 0x22222222); in ddr3_init()
1091 ast_moutdwm(ast, 0x1E6E0048, 0x22222222); in ddr3_init()
1092 ast_moutdwm(ast, 0x1E6E004C, 0x00000002); in ddr3_init()
1093 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr3_init()
1094 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr3_init()
1095 ast_moutdwm(ast, 0x1E6E0054, 0); in ddr3_init()
1096 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); in ddr3_init()
1097 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); in ddr3_init()
1098 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr3_init()
1099 ast_moutdwm(ast, 0x1E6E0074, 0x00000000); in ddr3_init()
1100 ast_moutdwm(ast, 0x1E6E0078, 0x00000000); in ddr3_init()
1101 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr3_init()
1104 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1106 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1109 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; in ddr3_init()
1113 ast_moutdwm(ast, 0x1E6E0064, data2); in ddr3_init()
1119 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; in ddr3_init()
1122 ast_moutdwm(ast, 0x1E6E0068, data); in ddr3_init()
1124 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); in ddr3_init()
1126 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; in ddr3_init()
1127 ast_moutdwm(ast, 0x1E6E0018, data); in ddr3_init()
1129 ast_moutdwm(ast, 0x1E6E0018, data); in ddr3_init()
1131 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1134 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1137 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff); in ddr3_init()
1138 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; in ddr3_init()
1139 ast_moutdwm(ast, 0x1E6E0018, data); in ddr3_init()
1141 ast_moutdwm(ast, 0x1E6E0034, 0x00000001); in ddr3_init()
1142 ast_moutdwm(ast, 0x1E6E000C, 0x00000040); in ddr3_init()
1145 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); in ddr3_init()
1146 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); in ddr3_init()
1147 ast_moutdwm(ast, 0x1E6E0028, 0x00000005); in ddr3_init()
1148 ast_moutdwm(ast, 0x1E6E0028, 0x00000007); in ddr3_init()
1149 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr3_init()
1150 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr3_init()
1151 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); in ddr3_init()
1152 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); in ddr3_init()
1153 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr3_init()
1155 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); in ddr3_init()
1163 ast_moutdwm(ast, 0x1E6E0034, data | 0x3); in ddr3_init()
1166 if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) in ddr3_init()
1169 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); in ddr3_init()
1172 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr3_init()
1173 ast_moutdwm(ast, 0x1E6E0070, 0x221); in ddr3_init()
1175 data = ast_mindwm(ast, 0x1E6E0070); in ddr3_init()
1177 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr3_init()
1178 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr3_init()
1179 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr3_init()
1185 static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *param) in get_ddr2_info() argument
1189 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); in get_ddr2_info()
1192 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; in get_ddr2_info()
1206 ast_moutdwm(ast, 0x1E6E2020, 0x0130); in get_ddr2_info()
1221 ast_moutdwm(ast, 0x1E6E2020, 0x0190); in get_ddr2_info()
1252 ast_moutdwm(ast, 0x1E6E2020, 0x03F1); in get_ddr2_info()
1286 ast_moutdwm(ast, 0x1E6E2020, 0x01F0); in get_ddr2_info()
1319 ast_moutdwm(ast, 0x1E6E2020, 0x0230); in get_ddr2_info()
1334 ast_moutdwm(ast, 0x1E6E2020, 0x0261); in get_ddr2_info()
1350 ast_moutdwm(ast, 0x1E6E2020, 0x0120); in get_ddr2_info()
1366 ast_moutdwm(ast, 0x1E6E2020, 0x02A1); in get_ddr2_info()
1382 ast_moutdwm(ast, 0x1E6E2020, 0x0140); in get_ddr2_info()
1432 static void ddr2_init(struct ast_device *ast, struct ast2300_dram_param *param) in ddr2_init() argument
1437 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in ddr2_init()
1438 ast_moutdwm(ast, 0x1E6E0018, 0x00000100); in ddr2_init()
1439 ast_moutdwm(ast, 0x1E6E0024, 0x00000000); in ddr2_init()
1440 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); in ddr2_init()
1441 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); in ddr2_init()
1443 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); in ddr2_init()
1446 ast_moutdwm(ast, 0x1E6E0004, param->dram_config); in ddr2_init()
1447 ast_moutdwm(ast, 0x1E6E0008, 0x90040f); in ddr2_init()
1448 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); in ddr2_init()
1449 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); in ddr2_init()
1450 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); in ddr2_init()
1451 ast_moutdwm(ast, 0x1E6E0080, 0x00000000); in ddr2_init()
1452 ast_moutdwm(ast, 0x1E6E0084, 0x00000000); in ddr2_init()
1453 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); in ddr2_init()
1454 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130); in ddr2_init()
1455 ast_moutdwm(ast, 0x1E6E0018, 0x00002330); in ddr2_init()
1456 ast_moutdwm(ast, 0x1E6E0038, 0x00000000); in ddr2_init()
1457 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000); in ddr2_init()
1458 ast_moutdwm(ast, 0x1E6E0044, 0x88848466); in ddr2_init()
1459 ast_moutdwm(ast, 0x1E6E0048, 0x44440008); in ddr2_init()
1460 ast_moutdwm(ast, 0x1E6E004C, 0x00000000); in ddr2_init()
1461 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr2_init()
1462 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr2_init()
1463 ast_moutdwm(ast, 0x1E6E0054, 0); in ddr2_init()
1464 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); in ddr2_init()
1465 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); in ddr2_init()
1466 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr2_init()
1467 ast_moutdwm(ast, 0x1E6E0074, 0x00000000); in ddr2_init()
1468 ast_moutdwm(ast, 0x1E6E0078, 0x00000000); in ddr2_init()
1469 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr2_init()
1473 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1475 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1478 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; in ddr2_init()
1482 ast_moutdwm(ast, 0x1E6E0064, data2); in ddr2_init()
1488 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; in ddr2_init()
1491 ast_moutdwm(ast, 0x1E6E0068, data); in ddr2_init()
1493 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); in ddr2_init()
1495 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; in ddr2_init()
1496 ast_moutdwm(ast, 0x1E6E0018, data); in ddr2_init()
1498 ast_moutdwm(ast, 0x1E6E0018, data); in ddr2_init()
1500 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1503 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1506 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff); in ddr2_init()
1507 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; in ddr2_init()
1508 ast_moutdwm(ast, 0x1E6E0018, data); in ddr2_init()
1510 ast_moutdwm(ast, 0x1E6E0034, 0x00000001); in ddr2_init()
1511 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr2_init()
1514 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); in ddr2_init()
1515 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); in ddr2_init()
1516 ast_moutdwm(ast, 0x1E6E0028, 0x00000005); in ddr2_init()
1517 ast_moutdwm(ast, 0x1E6E0028, 0x00000007); in ddr2_init()
1518 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr2_init()
1519 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr2_init()
1521 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); in ddr2_init()
1522 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); in ddr2_init()
1523 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr2_init()
1524 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380); in ddr2_init()
1525 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr2_init()
1526 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); in ddr2_init()
1527 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr2_init()
1529 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01); in ddr2_init()
1537 ast_moutdwm(ast, 0x1E6E0034, data | 0x3); in ddr2_init()
1538 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); in ddr2_init()
1541 if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) in ddr2_init()
1546 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr2_init()
1547 ast_moutdwm(ast, 0x1E6E0070, 0x221); in ddr2_init()
1549 data = ast_mindwm(ast, 0x1E6E0070); in ddr2_init()
1551 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr2_init()
1552 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr2_init()
1553 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr2_init()
1560 struct ast_device *ast = to_ast_device(dev); in ast_post_chip_2300() local
1565 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_post_chip_2300()
1567 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_post_chip_2300()
1568 ast_write32(ast, 0xf000, 0x1); in ast_post_chip_2300()
1569 ast_write32(ast, 0x12000, 0x1688a8a8); in ast_post_chip_2300()
1572 } while (ast_read32(ast, 0x12000) != 0x1); in ast_post_chip_2300()
1574 ast_write32(ast, 0x10000, 0xfc600309); in ast_post_chip_2300()
1577 } while (ast_read32(ast, 0x10000) != 0x1); in ast_post_chip_2300()
1580 temp = ast_read32(ast, 0x12008); in ast_post_chip_2300()
1582 ast_write32(ast, 0x12008, temp); in ast_post_chip_2300()
1586 temp = ast_mindwm(ast, 0x1e6e2070); in ast_post_chip_2300()
1624 get_ddr3_info(ast, ¶m); in ast_post_chip_2300()
1625 ddr3_init(ast, ¶m); in ast_post_chip_2300()
1627 get_ddr2_info(ast, ¶m); in ast_post_chip_2300()
1628 ddr2_init(ast, ¶m); in ast_post_chip_2300()
1631 temp = ast_mindwm(ast, 0x1e6e2040); in ast_post_chip_2300()
1632 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); in ast_post_chip_2300()
1637 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_post_chip_2300()
1641 static bool cbr_test_2500(struct ast_device *ast) in cbr_test_2500() argument
1643 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); in cbr_test_2500()
1644 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); in cbr_test_2500()
1645 if (!mmc_test_burst(ast, 0)) in cbr_test_2500()
1647 if (!mmc_test_single_2500(ast, 0)) in cbr_test_2500()
1652 static bool ddr_test_2500(struct ast_device *ast) in ddr_test_2500() argument
1654 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); in ddr_test_2500()
1655 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); in ddr_test_2500()
1656 if (!mmc_test_burst(ast, 0)) in ddr_test_2500()
1658 if (!mmc_test_burst(ast, 1)) in ddr_test_2500()
1660 if (!mmc_test_burst(ast, 2)) in ddr_test_2500()
1662 if (!mmc_test_burst(ast, 3)) in ddr_test_2500()
1664 if (!mmc_test_single_2500(ast, 0)) in ddr_test_2500()
1669 static void ddr_init_common_2500(struct ast_device *ast) in ddr_init_common_2500() argument
1671 ast_moutdwm(ast, 0x1E6E0034, 0x00020080); in ddr_init_common_2500()
1672 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F); in ddr_init_common_2500()
1673 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF); in ddr_init_common_2500()
1674 ast_moutdwm(ast, 0x1E6E0040, 0x88448844); in ddr_init_common_2500()
1675 ast_moutdwm(ast, 0x1E6E0044, 0x24422288); in ddr_init_common_2500()
1676 ast_moutdwm(ast, 0x1E6E0048, 0x22222222); in ddr_init_common_2500()
1677 ast_moutdwm(ast, 0x1E6E004C, 0x22222222); in ddr_init_common_2500()
1678 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr_init_common_2500()
1679 ast_moutdwm(ast, 0x1E6E0208, 0x00000000); in ddr_init_common_2500()
1680 ast_moutdwm(ast, 0x1E6E0218, 0x00000000); in ddr_init_common_2500()
1681 ast_moutdwm(ast, 0x1E6E0220, 0x00000000); in ddr_init_common_2500()
1682 ast_moutdwm(ast, 0x1E6E0228, 0x00000000); in ddr_init_common_2500()
1683 ast_moutdwm(ast, 0x1E6E0230, 0x00000000); in ddr_init_common_2500()
1684 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000); in ddr_init_common_2500()
1685 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000); in ddr_init_common_2500()
1686 ast_moutdwm(ast, 0x1E6E0240, 0x86000000); in ddr_init_common_2500()
1687 ast_moutdwm(ast, 0x1E6E0244, 0x00008600); in ddr_init_common_2500()
1688 ast_moutdwm(ast, 0x1E6E0248, 0x80000000); in ddr_init_common_2500()
1689 ast_moutdwm(ast, 0x1E6E024C, 0x80808080); in ddr_init_common_2500()
1692 static void ddr_phy_init_2500(struct ast_device *ast) in ddr_phy_init_2500() argument
1697 ast_moutdwm(ast, 0x1E6E0060, 0x00000005); in ddr_phy_init_2500()
1700 data = ast_mindwm(ast, 0x1E6E0060) & 0x1; in ddr_phy_init_2500()
1705 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000; in ddr_phy_init_2500()
1710 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr_phy_init_2500()
1712 ast_moutdwm(ast, 0x1E6E0060, 0x00000005); in ddr_phy_init_2500()
1716 ast_moutdwm(ast, 0x1E6E0060, 0x00000006); in ddr_phy_init_2500()
1726 static void check_dram_size_2500(struct ast_device *ast, u32 tRFC) in check_dram_size_2500() argument
1730 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc; in check_dram_size_2500()
1731 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00; in check_dram_size_2500()
1733 ast_moutdwm(ast, 0xA0100000, 0x41424344); in check_dram_size_2500()
1734 ast_moutdwm(ast, 0x90100000, 0x35363738); in check_dram_size_2500()
1735 ast_moutdwm(ast, 0x88100000, 0x292A2B2C); in check_dram_size_2500()
1736 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10); in check_dram_size_2500()
1739 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) { in check_dram_size_2500()
1743 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) { in check_dram_size_2500()
1747 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) { in check_dram_size_2500()
1753 ast_moutdwm(ast, 0x1E6E0004, reg_04); in check_dram_size_2500()
1754 ast_moutdwm(ast, 0x1E6E0014, reg_14); in check_dram_size_2500()
1757 static void enable_cache_2500(struct ast_device *ast) in enable_cache_2500() argument
1761 reg_04 = ast_mindwm(ast, 0x1E6E0004); in enable_cache_2500()
1762 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000); in enable_cache_2500()
1765 data = ast_mindwm(ast, 0x1E6E0004); in enable_cache_2500()
1767 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400); in enable_cache_2500()
1770 static void set_mpll_2500(struct ast_device *ast) in set_mpll_2500() argument
1775 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in set_mpll_2500()
1776 ast_moutdwm(ast, 0x1E6E0034, 0x00020080); in set_mpll_2500()
1778 ast_moutdwm(ast, addr, 0x0); in set_mpll_2500()
1781 ast_moutdwm(ast, 0x1E6E0034, 0x00020000); in set_mpll_2500()
1783 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); in set_mpll_2500()
1784 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000; in set_mpll_2500()
1788 ast_moutdwm(ast, 0x1E6E2160, 0x00011320); in set_mpll_2500()
1793 ast_moutdwm(ast, 0x1E6E2020, param); in set_mpll_2500()
1797 static void reset_mmc_2500(struct ast_device *ast) in reset_mmc_2500() argument
1799 ast_moutdwm(ast, 0x1E78505C, 0x00000004); in reset_mmc_2500()
1800 ast_moutdwm(ast, 0x1E785044, 0x00000001); in reset_mmc_2500()
1801 ast_moutdwm(ast, 0x1E785048, 0x00004755); in reset_mmc_2500()
1802 ast_moutdwm(ast, 0x1E78504C, 0x00000013); in reset_mmc_2500()
1804 ast_moutdwm(ast, 0x1E785054, 0x00000077); in reset_mmc_2500()
1805 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in reset_mmc_2500()
1808 static void ddr3_init_2500(struct ast_device *ast, const u32 *ddr_table) in ddr3_init_2500() argument
1811 ast_moutdwm(ast, 0x1E6E0004, 0x00000303); in ddr3_init_2500()
1812 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); in ddr3_init_2500()
1813 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); in ddr3_init_2500()
1814 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); in ddr3_init_2500()
1815 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ in ddr3_init_2500()
1816 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ in ddr3_init_2500()
1817 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ in ddr3_init_2500()
1818 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ in ddr3_init_2500()
1821 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE); in ddr3_init_2500()
1822 ast_moutdwm(ast, 0x1E6E0204, 0x00001001); in ddr3_init_2500()
1823 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); in ddr3_init_2500()
1824 ast_moutdwm(ast, 0x1E6E0210, 0x20000000); in ddr3_init_2500()
1825 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); in ddr3_init_2500()
1826 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); in ddr3_init_2500()
1827 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); in ddr3_init_2500()
1828 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); in ddr3_init_2500()
1829 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); in ddr3_init_2500()
1830 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); in ddr3_init_2500()
1831 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); in ddr3_init_2500()
1832 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); in ddr3_init_2500()
1833 ast_moutdwm(ast, 0x1E6E0290, 0x00100008); in ddr3_init_2500()
1834 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006); in ddr3_init_2500()
1837 ast_moutdwm(ast, 0x1E6E0034, 0x00020091); in ddr3_init_2500()
1840 ddr_phy_init_2500(ast); in ddr3_init_2500()
1842 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); in ddr3_init_2500()
1843 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); in ddr3_init_2500()
1844 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); in ddr3_init_2500()
1846 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); in ddr3_init_2500()
1847 enable_cache_2500(ast); in ddr3_init_2500()
1848 ast_moutdwm(ast, 0x1E6E001C, 0x00000008); in ddr3_init_2500()
1849 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); in ddr3_init_2500()
1852 static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table) in ddr4_init_2500() argument
1859 ast_moutdwm(ast, 0x1E6E0004, 0x00000313); in ddr4_init_2500()
1860 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); in ddr4_init_2500()
1861 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); in ddr4_init_2500()
1862 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); in ddr4_init_2500()
1863 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ in ddr4_init_2500()
1864 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ in ddr4_init_2500()
1865 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ in ddr4_init_2500()
1866 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ in ddr4_init_2500()
1869 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE); in ddr4_init_2500()
1870 ast_moutdwm(ast, 0x1E6E0204, 0x09002000); in ddr4_init_2500()
1871 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); in ddr4_init_2500()
1872 ast_moutdwm(ast, 0x1E6E0210, 0x20000000); in ddr4_init_2500()
1873 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); in ddr4_init_2500()
1874 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); in ddr4_init_2500()
1875 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); in ddr4_init_2500()
1876 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); in ddr4_init_2500()
1877 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); in ddr4_init_2500()
1878 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); in ddr4_init_2500()
1879 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); in ddr4_init_2500()
1880 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); in ddr4_init_2500()
1881 ast_moutdwm(ast, 0x1E6E0290, 0x00100008); in ddr4_init_2500()
1882 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C); in ddr4_init_2500()
1883 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E); in ddr4_init_2500()
1886 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991); in ddr4_init_2500()
1894 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06); in ddr4_init_2500()
1896 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr4_init_2500()
1897 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr4_init_2500()
1898 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8)); in ddr4_init_2500()
1900 ddr_phy_init_2500(ast); in ddr4_init_2500()
1901 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); in ddr4_init_2500()
1902 if (cbr_test_2500(ast)) { in ddr4_init_2500()
1904 data = ast_mindwm(ast, 0x1E6E03D0); in ddr4_init_2500()
1917 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8)); in ddr4_init_2500()
1927 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr4_init_2500()
1928 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr4_init_2500()
1929 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); in ddr4_init_2500()
1931 ddr_phy_init_2500(ast); in ddr4_init_2500()
1932 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); in ddr4_init_2500()
1933 if (cbr_test_2500(ast)) { in ddr4_init_2500()
1944 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr4_init_2500()
1945 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr4_init_2500()
1947 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); in ddr4_init_2500()
1950 ddr_phy_init_2500(ast); in ddr4_init_2500()
1952 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); in ddr4_init_2500()
1953 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); in ddr4_init_2500()
1954 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); in ddr4_init_2500()
1956 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); in ddr4_init_2500()
1957 enable_cache_2500(ast); in ddr4_init_2500()
1958 ast_moutdwm(ast, 0x1E6E001C, 0x00000008); in ddr4_init_2500()
1959 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); in ddr4_init_2500()
1962 static bool ast_dram_init_2500(struct ast_device *ast) in ast_dram_init_2500() argument
1970 set_mpll_2500(ast); in ast_dram_init_2500()
1971 reset_mmc_2500(ast); in ast_dram_init_2500()
1972 ddr_init_common_2500(ast); in ast_dram_init_2500()
1974 data = ast_mindwm(ast, 0x1E6E2070); in ast_dram_init_2500()
1976 ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table); in ast_dram_init_2500()
1978 ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table); in ast_dram_init_2500()
1979 } while (!ddr_test_2500(ast)); in ast_dram_init_2500()
1981 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41); in ast_dram_init_2500()
1984 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF; in ast_dram_init_2500()
1985 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000); in ast_dram_init_2500()
1990 void ast_patch_ahb_2500(struct ast_device *ast) in ast_patch_ahb_2500() argument
1995 ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); in ast_patch_ahb_2500()
1996 ast_moutdwm(ast, 0x1e600084, 0x00010000); in ast_patch_ahb_2500()
1997 ast_moutdwm(ast, 0x1e600088, 0x00000000); in ast_patch_ahb_2500()
1998 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); in ast_patch_ahb_2500()
1999 data = ast_mindwm(ast, 0x1e6e2070); in ast_patch_ahb_2500()
2012 ast_moutdwm(ast, 0x1E785004, 0x00000010); in ast_patch_ahb_2500()
2013 ast_moutdwm(ast, 0x1E785008, 0x00004755); in ast_patch_ahb_2500()
2014 ast_moutdwm(ast, 0x1E78500c, 0x00000033); in ast_patch_ahb_2500()
2018 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); in ast_patch_ahb_2500()
2019 data = ast_mindwm(ast, 0x1e6e2000); in ast_patch_ahb_2500()
2021 ast_moutdwm(ast, 0x1e6e207c, 0x08000000); /* clear fast reset */ in ast_patch_ahb_2500()
2026 struct ast_device *ast = to_ast_device(dev); in ast_post_chip_2500() local
2030 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_post_chip_2500()
2033 ast_patch_ahb_2500(ast); in ast_post_chip_2500()
2036 ast_moutdwm(ast, 0x1E78502C, 0x00000000); in ast_post_chip_2500()
2037 ast_moutdwm(ast, 0x1E78504C, 0x00000000); in ast_post_chip_2500()
2052 ast_moutdwm(ast, 0x1E6E2090, 0x20000000); in ast_post_chip_2500()
2053 ast_moutdwm(ast, 0x1E6E2094, 0x00004000); in ast_post_chip_2500()
2054 if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) { in ast_post_chip_2500()
2055 ast_moutdwm(ast, 0x1E6E207C, 0x00800000); in ast_post_chip_2500()
2057 ast_moutdwm(ast, 0x1E6E2070, 0x00800000); in ast_post_chip_2500()
2060 temp = ast_mindwm(ast, 0x1E6E2070); in ast_post_chip_2500()
2062 ast_moutdwm(ast, 0x1E6E207C, 0x00004000); in ast_post_chip_2500()
2065 temp = ast_read32(ast, 0x12008); in ast_post_chip_2500()
2067 ast_write32(ast, 0x12008, temp); in ast_post_chip_2500()
2069 if (!ast_dram_init_2500(ast)) in ast_post_chip_2500()
2072 temp = ast_mindwm(ast, 0x1e6e2040); in ast_post_chip_2500()
2073 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); in ast_post_chip_2500()
2078 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_post_chip_2500()