Lines Matching +full:0 +full:x00040000
27 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000
28 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000
29 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000
30 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000
31 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5 0x00100000
32 #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000
36 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001
37 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002
38 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004
39 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008
40 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5 0x00000010
41 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF
42 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0
52 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 0x00010000
53 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 0x00020000
54 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 0x00040000
55 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 0x00080000
56 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 0x00100000
57 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 0x00200000
58 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 0x00400000