59 	if (adev->irq.ih.ring_size) {  in vega20_ih_init_register_offset()
60 		ih_regs = &adev->irq.ih.ih_regs;  in vega20_ih_init_register_offset()
105 					    struct amdgpu_ih_ring *ih,  in vega20_ih_toggle_ring_interrupts()  argument
111 	ih_regs = &ih->ih_regs;  in vega20_ih_toggle_ring_interrupts()
118 	if (ih == &adev->irq.ih)  in vega20_ih_toggle_ring_interrupts()
130 		ih->enabled = true;  in vega20_ih_toggle_ring_interrupts()
135 		ih->enabled = false;  in vega20_ih_toggle_ring_interrupts()
136 		ih->rptr = 0;  in vega20_ih_toggle_ring_interrupts()
152 	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};  in vega20_ih_toggle_interrupts()  local
156 	for (i = 0; i < ARRAY_SIZE(ih); i++) {  in vega20_ih_toggle_interrupts()
157 		if (ih[i]->ring_size) {  in vega20_ih_toggle_interrupts()
158 			r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable);  in vega20_ih_toggle_interrupts()
167 static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)  in vega20_ih_rb_cntl()  argument
169 	int rb_bufsz = order_base_2(ih->ring_size / 4);  in vega20_ih_rb_cntl()
172 				   MC_SPACE, ih->use_bus_addr ? 1 : 4);  in vega20_ih_rb_cntl()
190 static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)  in vega20_ih_doorbell_rptr()  argument
194 	if (ih->use_doorbell) {  in vega20_ih_doorbell_rptr()
197 						 ih->doorbell_index);  in vega20_ih_doorbell_rptr()
218 				 struct amdgpu_ih_ring *ih)  in vega20_ih_enable_ring()  argument
223 	ih_regs = &ih->ih_regs;  in vega20_ih_enable_ring()
226 	WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);  in vega20_ih_enable_ring()
227 	WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);  in vega20_ih_enable_ring()
230 	tmp = vega20_ih_rb_cntl(ih, tmp);  in vega20_ih_enable_ring()
231 	if (ih == &adev->irq.ih)  in vega20_ih_enable_ring()
233 	if (ih == &adev->irq.ih1)  in vega20_ih_enable_ring()
244 	if (ih == &adev->irq.ih) {  in vega20_ih_enable_ring()
246 		WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));  in vega20_ih_enable_ring()
247 		WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);  in vega20_ih_enable_ring()
254 	WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));  in vega20_ih_enable_ring()
282 	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};  in vega20_ih_irq_init()  local
297 		if (adev->irq.ih.use_bus_addr) {  in vega20_ih_irq_init()
310 		if (adev->irq.ih.use_bus_addr) {  in vega20_ih_irq_init()
317 	for (i = 0; i < ARRAY_SIZE(ih); i++) {  in vega20_ih_irq_init()
318 		if (ih[i]->ring_size) {  in vega20_ih_irq_init()
319 			ret = vega20_ih_enable_ring(adev, ih[i]);  in vega20_ih_irq_init()
326 		adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,  in vega20_ih_irq_init()
327 						    adev->irq.ih.doorbell_index);  in vega20_ih_irq_init()
332 	adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 3) << 1;  in vega20_ih_irq_init()
384 			      struct amdgpu_ih_ring *ih)  in vega20_ih_get_wptr()  argument
389 	if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {  in vega20_ih_get_wptr()
395 		wptr = le32_to_cpu(*ih->wptr_cpu);  in vega20_ih_get_wptr()
401 	ih_regs = &ih->ih_regs;  in vega20_ih_get_wptr()
414 	tmp = (wptr + 32) & ih->ptr_mask;  in vega20_ih_get_wptr()
417 		 wptr, ih->rptr, tmp);  in vega20_ih_get_wptr()
418 	ih->rptr = tmp;  in vega20_ih_get_wptr()
425 	return (wptr & ih->ptr_mask);  in vega20_ih_get_wptr()
436 			       struct amdgpu_ih_ring *ih)  in vega20_ih_irq_rearm()  argument
442 	ih_regs = &ih->ih_regs;  in vega20_ih_irq_rearm()
447 		if ((v < ih->ring_size) && (v != ih->rptr))  in vega20_ih_irq_rearm()
448 			WDOORBELL32(ih->doorbell_index, ih->rptr);  in vega20_ih_irq_rearm()
463 			       struct amdgpu_ih_ring *ih)  in vega20_ih_set_rptr()  argument
467 	if (ih == &adev->irq.ih_soft)  in vega20_ih_set_rptr()
470 	if (ih->use_doorbell) {  in vega20_ih_set_rptr()
472 		*ih->rptr_cpu = ih->rptr;  in vega20_ih_set_rptr()
473 		WDOORBELL32(ih->doorbell_index, ih->rptr);  in vega20_ih_set_rptr()
476 			vega20_ih_irq_rearm(adev, ih);  in vega20_ih_set_rptr()
478 		ih_regs = &ih->ih_regs;  in vega20_ih_set_rptr()
479 		WREG32(ih_regs->ih_rb_rptr, ih->rptr);  in vega20_ih_set_rptr()
543 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);  in vega20_ih_sw_init()
547 	adev->irq.ih.use_doorbell = true;  in vega20_ih_sw_init()
548 	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;  in vega20_ih_sw_init()
555 	adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;  in vega20_ih_sw_init()
563 		adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;  in vega20_ih_sw_init()