Lines Matching refs:vcn
84 adev->vcn.harvest_config = VCN_HARVEST_MMSCH; in vcn_v4_0_early_init()
85 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_early_init()
87 adev->vcn.harvest_config |= 1 << i; in vcn_v4_0_early_init()
94 adev->vcn.num_enc_rings = 1; in vcn_v4_0_early_init()
126 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_sw_init()
129 if (adev->vcn.harvest_config & (1 << i)) in vcn_v4_0_sw_init()
134 atomic_set(&adev->vcn.inst[i].sched_score, 1); in vcn_v4_0_sw_init()
136 atomic_set(&adev->vcn.inst[i].sched_score, 0); in vcn_v4_0_sw_init()
140 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); in vcn_v4_0_sw_init()
146 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].ras_poison_irq); in vcn_v4_0_sw_init()
150 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_sw_init()
153 …ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings … in vcn_v4_0_sw_init()
155 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; in vcn_v4_0_sw_init()
159 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, in vcn_v4_0_sw_init()
160 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); in vcn_v4_0_sw_init()
164 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; in vcn_v4_0_sw_init()
182 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); in vcn_v4_0_sw_init()
192 adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode; in vcn_v4_0_sw_init()
214 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_sw_fini()
217 if (adev->vcn.harvest_config & (1 << i)) in vcn_v4_0_sw_fini()
220 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; in vcn_v4_0_sw_fini()
258 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_hw_init()
259 if (adev->vcn.harvest_config & (1 << i)) in vcn_v4_0_hw_init()
262 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_hw_init()
270 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_hw_init()
271 if (adev->vcn.harvest_config & (1 << i)) in vcn_v4_0_hw_init()
274 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_hw_init()
277 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); in vcn_v4_0_hw_init()
306 cancel_delayed_work_sync(&adev->vcn.idle_work); in vcn_v4_0_hw_fini()
308 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_hw_fini()
309 if (adev->vcn.harvest_config & (1 << i)) in vcn_v4_0_hw_fini()
313 (adev->vcn.cur_state != AMD_PG_STATE_GATE && in vcn_v4_0_hw_fini()
319 amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0); in vcn_v4_0_hw_fini()
380 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; in vcn_v4_0_mc_resume()
393 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v4_0_mc_resume()
395 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v4_0_mc_resume()
403 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v4_0_mc_resume()
405 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v4_0_mc_resume()
411 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_mc_resume()
413 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_mc_resume()
419 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v4_0_mc_resume()
421 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v4_0_mc_resume()
440 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; in vcn_v4_0_mc_resume_dpg_mode()
466 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
469 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
487 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
490 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
507 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
510 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
519 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
522 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
916 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; in vcn_v4_0_start_dpg_mode()
930 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v4_0_start_dpg_mode()
1004 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; in vcn_v4_0_start_dpg_mode()
1051 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_start()
1052 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; in vcn_v4_0_start()
1055 r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); in vcn_v4_0_start()
1184 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_start()
1258 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_start_sriov()
1259 if (adev->vcn.harvest_config & (1 << i)) in vcn_v4_0_start_sriov()
1268 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v4_0_start_sriov()
1284 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v4_0_start_sriov()
1287 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v4_0_start_sriov()
1298 cache_addr = adev->vcn.inst[i].gpu_addr + offset; in vcn_v4_0_start_sriov()
1312 cache_addr = adev->vcn.inst[i].gpu_addr + offset + in vcn_v4_0_start_sriov()
1327 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; in vcn_v4_0_start_sriov()
1330 ring_enc = &adev->vcn.inst[i].ring_enc[0]; in vcn_v4_0_start_sriov()
1342 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); in vcn_v4_0_start_sriov()
1345 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); in vcn_v4_0_start_sriov()
1464 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_stop()
1465 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; in vcn_v4_0_stop()
1550 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v4_0_pause_dpg_mode()
1552 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v4_0_pause_dpg_mode()
1578 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v4_0_pause_dpg_mode()
1595 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v4_0_unified_ring_get_rptr()
1612 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v4_0_unified_ring_get_wptr()
1632 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v4_0_unified_ring_set_wptr()
1653 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) in vcn_v4_0_limit_sched()
1848 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_set_unified_ring_funcs()
1849 if (adev->vcn.harvest_config & (1 << i)) in vcn_v4_0_set_unified_ring_funcs()
1855 adev->vcn.inst[i].ring_enc[0].funcs = in vcn_v4_0_set_unified_ring_funcs()
1857 adev->vcn.inst[i].ring_enc[0].me = i; in vcn_v4_0_set_unified_ring_funcs()
1875 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_is_idle()
1876 if (adev->vcn.harvest_config & (1 << i)) in vcn_v4_0_is_idle()
1897 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_wait_for_idle()
1898 if (adev->vcn.harvest_config & (1 << i)) in vcn_v4_0_wait_for_idle()
1924 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_set_clockgating_state()
1925 if (adev->vcn.harvest_config & (1 << i)) in vcn_v4_0_set_clockgating_state()
1958 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; in vcn_v4_0_set_powergating_state()
1962 if (state == adev->vcn.cur_state) in vcn_v4_0_set_powergating_state()
1971 adev->vcn.cur_state = state; in vcn_v4_0_set_powergating_state()
2040 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); in vcn_v4_0_process_interrupt()
2072 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_set_irq_funcs()
2073 if (adev->vcn.harvest_config & (1 << i)) in vcn_v4_0_set_irq_funcs()
2076 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; in vcn_v4_0_set_irq_funcs()
2077 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs; in vcn_v4_0_set_irq_funcs()
2079 adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1; in vcn_v4_0_set_irq_funcs()
2080 adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v4_0_ras_irq_funcs; in vcn_v4_0_set_irq_funcs()
2138 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) in vcn_v4_0_query_ras_poison_status()
2161 adev->vcn.ras = &vcn_v4_0_ras; in vcn_v4_0_set_ras_funcs()