Lines Matching refs:vcn
93 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; in vcn_v3_0_early_init()
94 adev->vcn.harvest_config = 0; in vcn_v3_0_early_init()
95 adev->vcn.num_enc_rings = 1; in vcn_v3_0_early_init()
98 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | in vcn_v3_0_early_init()
104 adev->vcn.num_enc_rings = 0; in vcn_v3_0_early_init()
106 adev->vcn.num_enc_rings = 2; in vcn_v3_0_early_init()
148 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; in vcn_v3_0_sw_init()
153 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_sw_init()
156 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_sw_init()
159 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
160 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
161 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
162 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
163 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
164 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
166 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
167 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); in vcn_v3_0_sw_init()
168 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
169 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); in vcn_v3_0_sw_init()
170 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
171 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); in vcn_v3_0_sw_init()
172 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
173 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); in vcn_v3_0_sw_init()
174 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
175 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); in vcn_v3_0_sw_init()
179 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); in vcn_v3_0_sw_init()
183 atomic_set(&adev->vcn.inst[i].sched_score, 0); in vcn_v3_0_sw_init()
185 ring = &adev->vcn.inst[i].ring_dec; in vcn_v3_0_sw_init()
188 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1); in vcn_v3_0_sw_init()
190 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; in vcn_v3_0_sw_init()
194 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, in vcn_v3_0_sw_init()
196 &adev->vcn.inst[i].sched_score); in vcn_v3_0_sw_init()
200 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { in vcn_v3_0_sw_init()
205 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); in vcn_v3_0_sw_init()
209 ring = &adev->vcn.inst[i].ring_enc[j]; in vcn_v3_0_sw_init()
212 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j; in vcn_v3_0_sw_init()
214 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; in vcn_v3_0_sw_init()
218 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, in vcn_v3_0_sw_init()
219 hw_prio, &adev->vcn.inst[i].sched_score); in vcn_v3_0_sw_init()
224 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; in vcn_v3_0_sw_init()
236 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); in vcn_v3_0_sw_init()
245 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode; in vcn_v3_0_sw_init()
263 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_sw_fini()
266 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_sw_fini()
268 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; in vcn_v3_0_sw_fini()
307 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_init()
308 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_hw_init()
311 ring = &adev->vcn.inst[i].ring_dec; in vcn_v3_0_hw_init()
323 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { in vcn_v3_0_hw_init()
324 ring = &adev->vcn.inst[i].ring_enc[j]; in vcn_v3_0_hw_init()
338 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_init()
339 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_hw_init()
342 ring = &adev->vcn.inst[i].ring_dec; in vcn_v3_0_hw_init()
351 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { in vcn_v3_0_hw_init()
352 ring = &adev->vcn.inst[i].ring_enc[j]; in vcn_v3_0_hw_init()
380 cancel_delayed_work_sync(&adev->vcn.idle_work); in vcn_v3_0_hw_fini()
382 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_fini()
383 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_hw_fini()
388 (adev->vcn.cur_state != AMD_PG_STATE_GATE && in vcn_v3_0_hw_fini()
450 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v3_0_mc_resume()
463 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v3_0_mc_resume()
465 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v3_0_mc_resume()
474 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v3_0_mc_resume()
476 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v3_0_mc_resume()
482 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v3_0_mc_resume()
484 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v3_0_mc_resume()
490 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v3_0_mc_resume()
492 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v3_0_mc_resume()
500 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v3_0_mc_resume_dpg_mode()
526 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
529 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
547 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
550 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
567 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
570 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
579 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
582 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
944 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; in vcn_v3_0_start_dpg_mode()
958 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v3_0_start_dpg_mode()
1042 ring = &adev->vcn.inst[inst_idx].ring_dec; in vcn_v3_0_start_dpg_mode()
1104 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_start()
1105 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_start()
1109 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); in vcn_v3_0_start()
1229 ring = &adev->vcn.inst[i].ring_dec; in vcn_v3_0_start()
1239 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; in vcn_v3_0_start()
1260 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v3_0_start()
1269 ring = &adev->vcn.inst[i].ring_enc[1]; in vcn_v3_0_start()
1322 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_start_sriov()
1323 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_start_sriov()
1332 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v3_0_start_sriov()
1348 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v3_0_start_sriov()
1351 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v3_0_start_sriov()
1362 cache_addr = adev->vcn.inst[i].gpu_addr + offset; in vcn_v3_0_start_sriov()
1376 cache_addr = adev->vcn.inst[i].gpu_addr + offset + in vcn_v3_0_start_sriov()
1391 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { in vcn_v3_0_start_sriov()
1392 ring = &adev->vcn.inst[i].ring_enc[j]; in vcn_v3_0_start_sriov()
1406 ring = &adev->vcn.inst[i].ring_dec; in vcn_v3_0_start_sriov()
1527 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_stop()
1528 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_stop()
1606 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v3_0_pause_dpg_mode()
1608 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v3_0_pause_dpg_mode()
1633 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; in vcn_v3_0_pause_dpg_mode()
1635 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; in vcn_v3_0_pause_dpg_mode()
1645 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; in vcn_v3_0_pause_dpg_mode()
1671 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v3_0_pause_dpg_mode()
1722 fw_shared = adev->vcn.inst[ring->me].fw_shared.cpu_addr; in vcn_v3_0_dec_ring_set_wptr()
1774 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) in vcn_v3_0_limit_sched()
1882 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) { in vcn_v3_0_ring_patch_cs_in_place()
1884 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) { in vcn_v3_0_ring_patch_cs_in_place()
1886 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) && in vcn_v3_0_ring_patch_cs_in_place()
1939 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v3_0_enc_ring_get_rptr()
1956 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { in vcn_v3_0_enc_ring_get_wptr()
1980 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { in vcn_v3_0_enc_ring_set_wptr()
2030 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_set_dec_ring_funcs()
2031 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_set_dec_ring_funcs()
2035 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; in vcn_v3_0_set_dec_ring_funcs()
2037 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs; in vcn_v3_0_set_dec_ring_funcs()
2038 adev->vcn.inst[i].ring_dec.me = i; in vcn_v3_0_set_dec_ring_funcs()
2048 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_set_enc_ring_funcs()
2049 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_set_enc_ring_funcs()
2052 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { in vcn_v3_0_set_enc_ring_funcs()
2053 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; in vcn_v3_0_set_enc_ring_funcs()
2054 adev->vcn.inst[i].ring_enc[j].me = i; in vcn_v3_0_set_enc_ring_funcs()
2056 if (adev->vcn.num_enc_rings > 0) in vcn_v3_0_set_enc_ring_funcs()
2066 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_is_idle()
2067 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_is_idle()
2081 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_wait_for_idle()
2082 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_wait_for_idle()
2101 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_set_clockgating_state()
2102 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_set_clockgating_state()
2128 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; in vcn_v3_0_set_powergating_state()
2132 if (state == adev->vcn.cur_state) in vcn_v3_0_set_powergating_state()
2141 adev->vcn.cur_state = state; in vcn_v3_0_set_powergating_state()
2176 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); in vcn_v3_0_process_interrupt()
2179 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); in vcn_v3_0_process_interrupt()
2182 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); in vcn_v3_0_process_interrupt()
2202 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_set_irq_funcs()
2203 if (adev->vcn.harvest_config & (1 << i)) in vcn_v3_0_set_irq_funcs()
2206 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; in vcn_v3_0_set_irq_funcs()
2207 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; in vcn_v3_0_set_irq_funcs()