Lines Matching refs:vcn
86 adev->vcn.num_vcn_inst = 2; in vcn_v2_5_early_init()
87 adev->vcn.harvest_config = 0; in vcn_v2_5_early_init()
88 adev->vcn.num_enc_rings = 1; in vcn_v2_5_early_init()
93 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_early_init()
96 adev->vcn.harvest_config |= 1 << i; in vcn_v2_5_early_init()
98 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | in vcn_v2_5_early_init()
103 adev->vcn.num_enc_rings = 2; in vcn_v2_5_early_init()
127 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()
128 if (adev->vcn.harvest_config & (1 << j)) in vcn_v2_5_sw_init()
132 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq); in vcn_v2_5_sw_init()
137 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_sw_init()
139 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq); in vcn_v2_5_sw_init()
146 VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[j].ras_poison_irq); in vcn_v2_5_sw_init()
161 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()
164 if (adev->vcn.harvest_config & (1 << j)) in vcn_v2_5_sw_init()
166 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
167 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
168 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
169 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
170 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
171 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
173 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
174 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9); in vcn_v2_5_sw_init()
175 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
176 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_5_sw_init()
177 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
178 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_5_sw_init()
179 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
180 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_5_sw_init()
181 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
182 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP); in vcn_v2_5_sw_init()
184 ring = &adev->vcn.inst[j].ring_dec; in vcn_v2_5_sw_init()
187 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + in vcn_v2_5_sw_init()
196 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, in vcn_v2_5_sw_init()
201 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_sw_init()
204 ring = &adev->vcn.inst[j].ring_enc[i]; in vcn_v2_5_sw_init()
207 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + in vcn_v2_5_sw_init()
217 &adev->vcn.inst[j].irq, 0, in vcn_v2_5_sw_init()
223 fw_shared = adev->vcn.inst[j].fw_shared.cpu_addr; in vcn_v2_5_sw_init()
227 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); in vcn_v2_5_sw_init()
237 adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode; in vcn_v2_5_sw_init()
260 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_sw_fini()
261 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_sw_fini()
263 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; in vcn_v2_5_sw_fini()
298 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in vcn_v2_5_hw_init()
299 if (adev->vcn.harvest_config & (1 << j)) in vcn_v2_5_hw_init()
303 adev->vcn.inst[j].ring_enc[0].sched.ready = true; in vcn_v2_5_hw_init()
304 adev->vcn.inst[j].ring_enc[1].sched.ready = false; in vcn_v2_5_hw_init()
305 adev->vcn.inst[j].ring_enc[2].sched.ready = false; in vcn_v2_5_hw_init()
306 adev->vcn.inst[j].ring_dec.sched.ready = true; in vcn_v2_5_hw_init()
309 ring = &adev->vcn.inst[j].ring_dec; in vcn_v2_5_hw_init()
318 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_hw_init()
319 ring = &adev->vcn.inst[j].ring_enc[i]; in vcn_v2_5_hw_init()
347 cancel_delayed_work_sync(&adev->vcn.idle_work); in vcn_v2_5_hw_fini()
349 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_hw_fini()
350 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_hw_fini()
354 (adev->vcn.cur_state != AMD_PG_STATE_GATE && in vcn_v2_5_hw_fini()
359 amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0); in vcn_v2_5_hw_fini()
416 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_5_mc_resume()
420 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_mc_resume()
421 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_mc_resume()
433 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
435 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
444 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
446 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
452 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
454 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
460 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); in vcn_v2_5_mc_resume()
462 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); in vcn_v2_5_mc_resume()
471 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_5_mc_resume_dpg_mode()
497 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
500 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
518 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
521 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
538 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
541 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
550 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
553 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
577 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_disable_clock_gating()
578 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_disable_clock_gating()
742 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_enable_clock_gating()
743 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_enable_clock_gating()
821 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; in vcn_v2_5_start_dpg_mode()
835 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v2_5_start_dpg_mode()
917 ring = &adev->vcn.inst[inst_idx].ring_dec; in vcn_v2_5_start_dpg_mode()
972 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_start()
973 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_start()
976 r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram); in vcn_v2_5_start()
995 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_start()
996 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_start()
1044 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_start()
1045 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; in vcn_v2_5_start()
1046 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_start()
1109 ring = &adev->vcn.inst[i].ring_dec; in vcn_v2_5_start()
1135 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v2_5_start()
1144 ring = &adev->vcn.inst[i].ring_enc[1]; in vcn_v2_5_start()
1231 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_sriov_start()
1242 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_5_sriov_start()
1260 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_sriov_start()
1264 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_sriov_start()
1277 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_sriov_start()
1281 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_sriov_start()
1291 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + in vcn_v2_5_sriov_start()
1296 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + in vcn_v2_5_sriov_start()
1305 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v2_5_sriov_start()
1318 ring = &adev->vcn.inst[i].ring_dec; in vcn_v2_5_sriov_start()
1385 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_stop()
1386 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_stop()
1456 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v2_5_pause_dpg_mode()
1458 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v2_5_pause_dpg_mode()
1467 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; in vcn_v2_5_pause_dpg_mode()
1485 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; in vcn_v2_5_pause_dpg_mode()
1495 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; in vcn_v2_5_pause_dpg_mode()
1517 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v2_5_pause_dpg_mode()
1614 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v2_5_enc_ring_get_rptr()
1631 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { in vcn_v2_5_enc_ring_get_wptr()
1655 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { in vcn_v2_5_enc_ring_set_wptr()
1705 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_set_dec_ring_funcs()
1706 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_set_dec_ring_funcs()
1708 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs; in vcn_v2_5_set_dec_ring_funcs()
1709 adev->vcn.inst[i].ring_dec.me = i; in vcn_v2_5_set_dec_ring_funcs()
1718 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in vcn_v2_5_set_enc_ring_funcs()
1719 if (adev->vcn.harvest_config & (1 << j)) in vcn_v2_5_set_enc_ring_funcs()
1721 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_set_enc_ring_funcs()
1722 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs; in vcn_v2_5_set_enc_ring_funcs()
1723 adev->vcn.inst[j].ring_enc[i].me = j; in vcn_v2_5_set_enc_ring_funcs()
1734 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_is_idle()
1735 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_is_idle()
1748 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_wait_for_idle()
1749 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_wait_for_idle()
1789 if(state == adev->vcn.cur_state) in vcn_v2_5_set_powergating_state()
1798 adev->vcn.cur_state = state; in vcn_v2_5_set_powergating_state()
1841 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); in vcn_v2_5_process_interrupt()
1844 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); in vcn_v2_5_process_interrupt()
1847 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); in vcn_v2_5_process_interrupt()
1872 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_set_irq_funcs()
1873 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_set_irq_funcs()
1875 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; in vcn_v2_5_set_irq_funcs()
1876 adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs; in vcn_v2_5_set_irq_funcs()
1878 adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1; in vcn_v2_5_set_irq_funcs()
1879 adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v2_6_ras_irq_funcs; in vcn_v2_5_set_irq_funcs()
1967 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) in vcn_v2_6_query_poison_status()
1990 adev->vcn.ras = &vcn_v2_6_ras; in vcn_v2_5_set_ras_funcs()