1433 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in vcn_v1_0_dec_ring_insert_start()
1436 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_ring_insert_start()
1452 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_ring_insert_end()
1474 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));  in vcn_v1_0_dec_ring_emit_fence()
1477 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in vcn_v1_0_dec_ring_emit_fence()
1480 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));  in vcn_v1_0_dec_ring_emit_fence()
1483 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_ring_emit_fence()
1487 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in vcn_v1_0_dec_ring_emit_fence()
1490 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));  in vcn_v1_0_dec_ring_emit_fence()
1493 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_ring_emit_fence()
1516 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));  in vcn_v1_0_dec_ring_emit_ib()
1520 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));  in vcn_v1_0_dec_ring_emit_ib()
1523 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));  in vcn_v1_0_dec_ring_emit_ib()
1526 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));  in vcn_v1_0_dec_ring_emit_ib()
1537 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in vcn_v1_0_dec_ring_emit_reg_wait()
1540 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));  in vcn_v1_0_dec_ring_emit_reg_wait()
1543 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));  in vcn_v1_0_dec_ring_emit_reg_wait()
1546 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_ring_emit_reg_wait()
1571 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in vcn_v1_0_dec_ring_emit_wreg()
1574 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));  in vcn_v1_0_dec_ring_emit_wreg()
1577 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_ring_emit_wreg()
1757 		amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));  in vcn_v1_0_dec_ring_insert_nop()
1961 		if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) {  in vcn_v1_0_ring_patch_cs_in_place()
1963 		} else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) {  in vcn_v1_0_ring_patch_cs_in_place()
1965 		} else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0)) {  in vcn_v1_0_ring_patch_cs_in_place()