90 		v = RREG32(mmVCE_RB_RPTR);  in vce_v3_0_ring_get_rptr()
92 		v = RREG32(mmVCE_RB_RPTR2);  in vce_v3_0_ring_get_rptr()
94 		v = RREG32(mmVCE_RB_RPTR3);  in vce_v3_0_ring_get_rptr()
122 		v = RREG32(mmVCE_RB_WPTR);  in vce_v3_0_ring_get_wptr()
124 		v = RREG32(mmVCE_RB_WPTR2);  in vce_v3_0_ring_get_wptr()
126 		v = RREG32(mmVCE_RB_WPTR3);  in vce_v3_0_ring_get_wptr()
182 		data = RREG32(mmVCE_CLOCK_GATING_B);  in vce_v3_0_set_vce_sw_clock_gating()
187 		data = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v3_0_set_vce_sw_clock_gating()
192 		data = RREG32(mmVCE_UENC_CLOCK_GATING_2);  in vce_v3_0_set_vce_sw_clock_gating()
197 		data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);  in vce_v3_0_set_vce_sw_clock_gating()
201 		data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);  in vce_v3_0_set_vce_sw_clock_gating()
208 		data = RREG32(mmVCE_CLOCK_GATING_B);  in vce_v3_0_set_vce_sw_clock_gating()
213 		data = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v3_0_set_vce_sw_clock_gating()
217 		data = RREG32(mmVCE_UENC_CLOCK_GATING_2);  in vce_v3_0_set_vce_sw_clock_gating()
221 		data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);  in vce_v3_0_set_vce_sw_clock_gating()
225 		data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);  in vce_v3_0_set_vce_sw_clock_gating()
241 			uint32_t status = RREG32(mmVCE_STATUS);  in vce_v3_0_firmware_loaded()
611 	return !(RREG32(mmSRBM_STATUS2) & mask);  in vce_v3_0_is_idle()
652 	if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {  in vce_v3_0_check_soft_reset()
657 	if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {  in vce_v3_0_check_soft_reset()
685 		tmp = RREG32(mmSRBM_SOFT_RESET);  in vce_v3_0_soft_reset()
689 		tmp = RREG32(mmSRBM_SOFT_RESET);  in vce_v3_0_soft_reset()
695 		tmp = RREG32(mmSRBM_SOFT_RESET);  in vce_v3_0_soft_reset()
786 			uint32_t data = RREG32(mmVCE_CLOCK_GATING_A);  in vce_v3_0_set_clockgating_state()
792 			data = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v3_0_set_clockgating_state()
854 	data = RREG32(mmVCE_CLOCK_GATING_A);  in vce_v3_0_get_clockgating_state()