Lines Matching refs:adev
150 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, in soc21_query_video_codecs() argument
153 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in soc21_query_video_codecs()
156 switch (adev->ip_versions[UVD_HWIP][0]) { in soc21_query_video_codecs()
160 if (amdgpu_sriov_vf(adev)) { in soc21_query_video_codecs()
161 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || in soc21_query_video_codecs()
162 !amdgpu_sriov_is_av1_support(adev)) { in soc21_query_video_codecs()
174 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) { in soc21_query_video_codecs()
192 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) in soc21_didt_rreg() argument
200 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc21_didt_rreg()
203 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc21_didt_rreg()
207 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc21_didt_wreg() argument
214 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc21_didt_wreg()
217 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc21_didt_wreg()
220 static u32 soc21_get_config_memsize(struct amdgpu_device *adev) in soc21_get_config_memsize() argument
222 return adev->nbio.funcs->get_memsize(adev); in soc21_get_config_memsize()
225 static u32 soc21_get_xclk(struct amdgpu_device *adev) in soc21_get_xclk() argument
227 return adev->clock.spll.reference_freq; in soc21_get_xclk()
231 void soc21_grbm_select(struct amdgpu_device *adev, in soc21_grbm_select() argument
243 static bool soc21_read_disabled_bios(struct amdgpu_device *adev) in soc21_read_disabled_bios() argument
271 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc21_read_indexed_register() argument
276 mutex_lock(&adev->grbm_idx_mutex); in soc21_read_indexed_register()
278 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in soc21_read_indexed_register()
283 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in soc21_read_indexed_register()
284 mutex_unlock(&adev->grbm_idx_mutex); in soc21_read_indexed_register()
288 static uint32_t soc21_get_register_value(struct amdgpu_device *adev, in soc21_get_register_value() argument
293 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc21_get_register_value()
295 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) in soc21_get_register_value()
296 return adev->gfx.config.gb_addr_config; in soc21_get_register_value()
301 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, in soc21_read_register() argument
310 if (!adev->reg_offset[en->hwip][en->inst]) in soc21_read_register()
312 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc21_read_register()
316 *value = soc21_get_register_value(adev, in soc21_read_register()
325 static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
330 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
333 pci_clear_master(adev->pdev);
335 amdgpu_device_cache_pci_state(adev->pdev);
337 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
338 dev_info(adev->dev, "GPU smu mode1 reset\n");
339 ret = amdgpu_dpm_mode1_reset(adev);
341 dev_info(adev->dev, "GPU psp mode1 reset\n");
342 ret = psp_gpu_reset(adev);
346 dev_err(adev->dev, "GPU mode1 reset failed\n");
347 amdgpu_device_load_pci_state(adev->pdev);
350 for (i = 0; i < adev->usec_timeout; i++) {
351 u32 memsize = adev->nbio.funcs->get_memsize(adev);
358 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
365 soc21_asic_reset_method(struct amdgpu_device *adev) in soc21_asic_reset_method() argument
373 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in soc21_asic_reset_method()
376 switch (adev->ip_versions[MP1_HWIP][0]) { in soc21_asic_reset_method()
385 if (amdgpu_dpm_is_baco_supported(adev)) in soc21_asic_reset_method()
392 static int soc21_asic_reset(struct amdgpu_device *adev) in soc21_asic_reset() argument
396 switch (soc21_asic_reset_method(adev)) { in soc21_asic_reset()
398 dev_info(adev->dev, "PCI reset\n"); in soc21_asic_reset()
399 ret = amdgpu_device_pci_reset(adev); in soc21_asic_reset()
402 dev_info(adev->dev, "BACO reset\n"); in soc21_asic_reset()
403 ret = amdgpu_dpm_baco_reset(adev); in soc21_asic_reset()
406 dev_info(adev->dev, "MODE2 reset\n"); in soc21_asic_reset()
407 ret = amdgpu_dpm_mode2_reset(adev); in soc21_asic_reset()
410 dev_info(adev->dev, "MODE1 reset\n"); in soc21_asic_reset()
411 ret = amdgpu_device_mode1_reset(adev); in soc21_asic_reset()
418 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in soc21_set_uvd_clocks() argument
424 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in soc21_set_vce_clocks() argument
430 static void soc21_program_aspm(struct amdgpu_device *adev) in soc21_program_aspm() argument
432 if (!amdgpu_device_should_use_aspm(adev)) in soc21_program_aspm()
435 if (!(adev->flags & AMD_IS_APU) && in soc21_program_aspm()
436 (adev->nbio.funcs->program_aspm)) in soc21_program_aspm()
437 adev->nbio.funcs->program_aspm(adev); in soc21_program_aspm()
448 static bool soc21_need_full_reset(struct amdgpu_device *adev) in soc21_need_full_reset() argument
450 switch (adev->ip_versions[GC_HWIP][0]) { in soc21_need_full_reset()
452 return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC); in soc21_need_full_reset()
461 static bool soc21_need_reset_on_init(struct amdgpu_device *adev) in soc21_need_reset_on_init() argument
465 if (adev->flags & AMD_IS_APU) in soc21_need_reset_on_init()
478 static void soc21_init_doorbell_index(struct amdgpu_device *adev) in soc21_init_doorbell_index() argument
480 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; in soc21_init_doorbell_index()
481 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; in soc21_init_doorbell_index()
482 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; in soc21_init_doorbell_index()
483 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; in soc21_init_doorbell_index()
484 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; in soc21_init_doorbell_index()
485 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; in soc21_init_doorbell_index()
486 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; in soc21_init_doorbell_index()
487 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; in soc21_init_doorbell_index()
488 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; in soc21_init_doorbell_index()
489 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; in soc21_init_doorbell_index()
490 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; in soc21_init_doorbell_index()
491 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; in soc21_init_doorbell_index()
492 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; in soc21_init_doorbell_index()
493 adev->doorbell_index.gfx_userqueue_start = in soc21_init_doorbell_index()
495 adev->doorbell_index.gfx_userqueue_end = in soc21_init_doorbell_index()
497 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; in soc21_init_doorbell_index()
498 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; in soc21_init_doorbell_index()
499 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; in soc21_init_doorbell_index()
500 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; in soc21_init_doorbell_index()
501 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; in soc21_init_doorbell_index()
502 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; in soc21_init_doorbell_index()
503 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; in soc21_init_doorbell_index()
504 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; in soc21_init_doorbell_index()
505 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; in soc21_init_doorbell_index()
506 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; in soc21_init_doorbell_index()
507 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; in soc21_init_doorbell_index()
509 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; in soc21_init_doorbell_index()
510 adev->doorbell_index.sdma_doorbell_range = 20; in soc21_init_doorbell_index()
513 static void soc21_pre_asic_init(struct amdgpu_device *adev) in soc21_pre_asic_init() argument
517 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev, in soc21_update_umd_stable_pstate() argument
521 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in soc21_update_umd_stable_pstate()
523 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in soc21_update_umd_stable_pstate()
525 if (adev->gfx.funcs->update_perfmon_mgcg) in soc21_update_umd_stable_pstate()
526 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); in soc21_update_umd_stable_pstate()
554 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_early_init() local
556 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; in soc21_common_early_init()
557 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; in soc21_common_early_init()
558 adev->smc_rreg = NULL; in soc21_common_early_init()
559 adev->smc_wreg = NULL; in soc21_common_early_init()
560 adev->pcie_rreg = &amdgpu_device_indirect_rreg; in soc21_common_early_init()
561 adev->pcie_wreg = &amdgpu_device_indirect_wreg; in soc21_common_early_init()
562 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; in soc21_common_early_init()
563 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; in soc21_common_early_init()
564 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; in soc21_common_early_init()
565 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; in soc21_common_early_init()
568 adev->uvd_ctx_rreg = NULL; in soc21_common_early_init()
569 adev->uvd_ctx_wreg = NULL; in soc21_common_early_init()
571 adev->didt_rreg = &soc21_didt_rreg; in soc21_common_early_init()
572 adev->didt_wreg = &soc21_didt_wreg; in soc21_common_early_init()
574 adev->asic_funcs = &soc21_asic_funcs; in soc21_common_early_init()
576 adev->rev_id = amdgpu_device_get_rev_id(adev); in soc21_common_early_init()
577 adev->external_rev_id = 0xff; in soc21_common_early_init()
578 switch (adev->ip_versions[GC_HWIP][0]) { in soc21_common_early_init()
580 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | in soc21_common_early_init()
598 adev->pg_flags = AMD_PG_SUPPORT_VCN | in soc21_common_early_init()
603 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update in soc21_common_early_init()
606 adev->cg_flags = in soc21_common_early_init()
616 adev->pg_flags = in soc21_common_early_init()
622 adev->external_rev_id = adev->rev_id + 0x10; in soc21_common_early_init()
625 adev->cg_flags = in soc21_common_early_init()
643 adev->pg_flags = in soc21_common_early_init()
648 adev->external_rev_id = adev->rev_id + 0x1; in soc21_common_early_init()
651 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | in soc21_common_early_init()
660 adev->pg_flags = AMD_PG_SUPPORT_VCN | in soc21_common_early_init()
663 adev->external_rev_id = adev->rev_id + 0x20; in soc21_common_early_init()
666 adev->cg_flags = in soc21_common_early_init()
684 adev->pg_flags = AMD_PG_SUPPORT_VCN | in soc21_common_early_init()
688 adev->external_rev_id = adev->rev_id + 0x80; in soc21_common_early_init()
696 if (amdgpu_sriov_vf(adev)) { in soc21_common_early_init()
697 amdgpu_virt_init_setting(adev); in soc21_common_early_init()
698 xgpu_nv_mailbox_set_irq_funcs(adev); in soc21_common_early_init()
706 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_late_init() local
708 if (amdgpu_sriov_vf(adev)) { in soc21_common_late_init()
709 xgpu_nv_mailbox_get_irq(adev); in soc21_common_late_init()
710 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || in soc21_common_late_init()
711 !amdgpu_sriov_is_av1_support(adev)) { in soc21_common_late_init()
712 amdgpu_virt_update_sriov_video_codec(adev, in soc21_common_late_init()
718 amdgpu_virt_update_sriov_video_codec(adev, in soc21_common_late_init()
725 if (adev->nbio.ras && in soc21_common_late_init()
726 adev->nbio.ras_err_event_athub_irq.funcs) in soc21_common_late_init()
731 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); in soc21_common_late_init()
737 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); in soc21_common_late_init()
744 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_sw_init() local
746 if (amdgpu_sriov_vf(adev)) in soc21_common_sw_init()
747 xgpu_nv_mailbox_add_irq_id(adev); in soc21_common_sw_init()
759 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_hw_init() local
762 soc21_program_aspm(adev); in soc21_common_hw_init()
764 adev->nbio.funcs->init_registers(adev); in soc21_common_hw_init()
769 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in soc21_common_hw_init()
770 adev->nbio.funcs->remap_hdp_registers(adev); in soc21_common_hw_init()
772 adev->nbio.funcs->enable_doorbell_aperture(adev, true); in soc21_common_hw_init()
779 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_hw_fini() local
786 adev->nbio.funcs->enable_doorbell_aperture(adev, false); in soc21_common_hw_fini()
787 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); in soc21_common_hw_fini()
789 if (amdgpu_sriov_vf(adev)) { in soc21_common_hw_fini()
790 xgpu_nv_mailbox_put_irq(adev); in soc21_common_hw_fini()
792 if (adev->nbio.ras && in soc21_common_hw_fini()
793 adev->nbio.ras_err_event_athub_irq.funcs) in soc21_common_hw_fini()
794 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); in soc21_common_hw_fini()
802 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_suspend() local
804 return soc21_common_hw_fini(adev); in soc21_common_suspend()
809 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_resume() local
811 return soc21_common_hw_init(adev); in soc21_common_resume()
832 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_set_clockgating_state() local
834 switch (adev->ip_versions[NBIO_HWIP][0]) { in soc21_common_set_clockgating_state()
838 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc21_common_set_clockgating_state()
840 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc21_common_set_clockgating_state()
842 adev->hdp.funcs->update_clock_gating(adev, in soc21_common_set_clockgating_state()
854 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_set_powergating_state() local
856 switch (adev->ip_versions[LSDMA_HWIP][0]) { in soc21_common_set_powergating_state()
859 adev->lsdma.funcs->update_memory_power_gating(adev, in soc21_common_set_powergating_state()
871 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_get_clockgating_state() local
873 adev->nbio.funcs->get_clockgating_state(adev, flags); in soc21_common_get_clockgating_state()
875 adev->hdp.funcs->get_clock_gating_state(adev, flags); in soc21_common_get_clockgating_state()