37 	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;  in sienna_cichlid_is_mode2_default()
39 	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7) &&  in sienna_cichlid_is_mode2_default()
40 	    adev->pm.fw_version >= 0x3a5500 && !amdgpu_sriov_vf(adev))  in sienna_cichlid_is_mode2_default()
71 static int sienna_cichlid_mode2_suspend_ip(struct amdgpu_device *adev)  in sienna_cichlid_mode2_suspend_ip()  argument
75 	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);  in sienna_cichlid_mode2_suspend_ip()
76 	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);  in sienna_cichlid_mode2_suspend_ip()
78 	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {  in sienna_cichlid_mode2_suspend_ip()
79 		if (!(adev->ip_blocks[i].version->type ==  in sienna_cichlid_mode2_suspend_ip()
81 		      adev->ip_blocks[i].version->type ==  in sienna_cichlid_mode2_suspend_ip()
85 		r = adev->ip_blocks[i].version->funcs->suspend(adev);  in sienna_cichlid_mode2_suspend_ip()
88 			dev_err(adev->dev,  in sienna_cichlid_mode2_suspend_ip()
90 				adev->ip_blocks[i].version->funcs->name, r);  in sienna_cichlid_mode2_suspend_ip()
93 		adev->ip_blocks[i].status.hw = false;  in sienna_cichlid_mode2_suspend_ip()
104 	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;  in sienna_cichlid_mode2_prepare_hwcontext()  local
106 	if (!amdgpu_sriov_vf(adev)) {  in sienna_cichlid_mode2_prepare_hwcontext()
107 		if (adev->gfxhub.funcs->mode2_save_regs)  in sienna_cichlid_mode2_prepare_hwcontext()
108 			adev->gfxhub.funcs->mode2_save_regs(adev);  in sienna_cichlid_mode2_prepare_hwcontext()
109 		if (adev->gfxhub.funcs->halt)  in sienna_cichlid_mode2_prepare_hwcontext()
110 			adev->gfxhub.funcs->halt(adev);  in sienna_cichlid_mode2_prepare_hwcontext()
111 		r = sienna_cichlid_mode2_suspend_ip(adev);  in sienna_cichlid_mode2_prepare_hwcontext()
122 	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;  in sienna_cichlid_async_reset()  local
127 			dev_dbg(adev->dev, "Resetting device\n");  in sienna_cichlid_async_reset()
128 			handler->do_reset(adev);  in sienna_cichlid_async_reset()
134 static int sienna_cichlid_mode2_reset(struct amdgpu_device *adev)  in sienna_cichlid_mode2_reset()  argument
137 	pci_clear_master(adev->pdev);  in sienna_cichlid_mode2_reset()
138 	return amdgpu_dpm_mode2_reset(adev);  in sienna_cichlid_mode2_reset()
145 	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;  in sienna_cichlid_mode2_perform_reset()  local
148 	r = sienna_cichlid_mode2_reset(adev);  in sienna_cichlid_mode2_perform_reset()
150 		dev_err(adev->dev,  in sienna_cichlid_mode2_perform_reset()
156 static int sienna_cichlid_mode2_restore_ip(struct amdgpu_device *adev)  in sienna_cichlid_mode2_restore_ip()  argument
159 	struct psp_context *psp = &adev->psp;  in sienna_cichlid_mode2_restore_ip()
163 		dev_err(adev->dev, "Failed to start rlc autoload\n");  in sienna_cichlid_mode2_restore_ip()
168 	if (adev->gfxhub.funcs->mode2_restore_regs)  in sienna_cichlid_mode2_restore_ip()
169 		adev->gfxhub.funcs->mode2_restore_regs(adev);  in sienna_cichlid_mode2_restore_ip()
170 	adev->gfxhub.funcs->init(adev);  in sienna_cichlid_mode2_restore_ip()
171 	r = adev->gfxhub.funcs->gart_enable(adev);  in sienna_cichlid_mode2_restore_ip()
173 		dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n");  in sienna_cichlid_mode2_restore_ip()
177 	for (i = 0; i < adev->num_ip_blocks; i++) {  in sienna_cichlid_mode2_restore_ip()
178 		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {  in sienna_cichlid_mode2_restore_ip()
179 			r = adev->ip_blocks[i].version->funcs->resume(adev);  in sienna_cichlid_mode2_restore_ip()
181 				dev_err(adev->dev,  in sienna_cichlid_mode2_restore_ip()
183 					adev->ip_blocks[i].version->funcs->name, r);  in sienna_cichlid_mode2_restore_ip()
187 			adev->ip_blocks[i].status.hw = true;  in sienna_cichlid_mode2_restore_ip()
191 	for (i = 0; i < adev->num_ip_blocks; i++) {  in sienna_cichlid_mode2_restore_ip()
192 		if (!(adev->ip_blocks[i].version->type ==  in sienna_cichlid_mode2_restore_ip()
194 		      adev->ip_blocks[i].version->type ==  in sienna_cichlid_mode2_restore_ip()
197 		r = adev->ip_blocks[i].version->funcs->resume(adev);  in sienna_cichlid_mode2_restore_ip()
199 			dev_err(adev->dev,  in sienna_cichlid_mode2_restore_ip()
201 				adev->ip_blocks[i].version->funcs->name, r);  in sienna_cichlid_mode2_restore_ip()
205 		adev->ip_blocks[i].status.hw = true;  in sienna_cichlid_mode2_restore_ip()
208 	for (i = 0; i < adev->num_ip_blocks; i++) {  in sienna_cichlid_mode2_restore_ip()
209 		if (!(adev->ip_blocks[i].version->type ==  in sienna_cichlid_mode2_restore_ip()
211 		      adev->ip_blocks[i].version->type ==  in sienna_cichlid_mode2_restore_ip()
215 		if (adev->ip_blocks[i].version->funcs->late_init) {  in sienna_cichlid_mode2_restore_ip()
216 			r = adev->ip_blocks[i].version->funcs->late_init(  in sienna_cichlid_mode2_restore_ip()
217 				(void *)adev);  in sienna_cichlid_mode2_restore_ip()
219 				dev_err(adev->dev,  in sienna_cichlid_mode2_restore_ip()
221 					adev->ip_blocks[i].version->funcs->name,  in sienna_cichlid_mode2_restore_ip()
226 		adev->ip_blocks[i].status.late_initialized = true;  in sienna_cichlid_mode2_restore_ip()
229 	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);  in sienna_cichlid_mode2_restore_ip()
230 	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);  in sienna_cichlid_mode2_restore_ip()
284 int sienna_cichlid_reset_init(struct amdgpu_device *adev)  in sienna_cichlid_reset_init()  argument
292 	reset_ctl->handle = adev;  in sienna_cichlid_reset_init()
302 	adev->reset_cntl = reset_ctl;  in sienna_cichlid_reset_init()
307 int sienna_cichlid_reset_fini(struct amdgpu_device *adev)  in sienna_cichlid_reset_fini()  argument
309 	kfree(adev->reset_cntl);  in sienna_cichlid_reset_fini()
310 	adev->reset_cntl = NULL;  in sienna_cichlid_reset_fini()