Lines Matching refs:sdma_cntl
590 u32 sdma_cntl; in si_dma_set_trap_irq_state() local
596 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
597 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
598 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
601 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
602 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
603 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
612 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
613 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
614 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
617 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
618 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
619 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()